From 420ef041b6d633772a2abf9004f8da4af7962b77 Mon Sep 17 00:00:00 2001 From: David Shah Date: Mon, 22 Jan 2018 17:03:16 +0000 Subject: More DSP timing fuzzing, start adding new tiles to icetime --- icetime/icetime.cc | 16 ++++++++++++++-- 1 file changed, 14 insertions(+), 2 deletions(-) (limited to 'icetime') diff --git a/icetime/icetime.cc b/icetime/icetime.cc index 176b4a0..60161c3 100644 --- a/icetime/icetime.cc +++ b/icetime/icetime.cc @@ -104,7 +104,8 @@ std::set declared_nets; int dangling_cnt = 0; std::map>> logic_tile_bits, - io_tile_bits, ramb_tile_bits, ramt_tile_bits; + io_tile_bits, ramb_tile_bits, ramt_tile_bits, ipcon_tile_bits, dsp0_tile_bits, + dsp1_tile_bits, dsp2_tile_bits, dsp3_tile_bits; std::string vstringf(const char *fmt, va_list ap) { @@ -432,7 +433,8 @@ void read_chipdb() gbufpin.push_back(items); } - if (mode == ".logic_tile_bits" || mode == ".io_tile_bits" || mode == ".ramb_tile_bits" || mode == ".ramt_tile_bits") { + if (mode == ".logic_tile_bits" || mode == ".io_tile_bits" || mode == ".ramb_tile_bits" || mode == ".ramt_tile_bits" || + mode == ".ipcon_tile_bits" || mode == ".dsp0_tile_bits" || mode == ".dsp1_tile_bits" || mode == ".dsp2_tile_bits" || mode == ".dsp3_tile_bits") { std::vector> items; while (1) { const char *s = strtok(nullptr, " \t\r\n"); @@ -451,6 +453,16 @@ void read_chipdb() ramb_tile_bits[tok] = items; if (mode == ".ramt_tile_bits") ramt_tile_bits[tok] = items; + if (mode == ".ipcon_tile_bits") + ipcon_tile_bits[tok] = items; + if (mode == ".dsp0_tile_bits") + dsp0_tile_bits[tok] = items; + if (mode == ".dsp1_tile_bits") + dsp1_tile_bits[tok] = items; + if (mode == ".dsp2_tile_bits") + dsp2_tile_bits[tok] = items; + if (mode == ".dsp3_tile_bits") + dsp3_tile_bits[tok] = items; } if (mode == ".extra_bits") { -- cgit v1.2.3