From 2aa02a28d4078c616d96400973d3b5e4cf1e454c Mon Sep 17 00:00:00 2001 From: gatecat Date: Wed, 17 Feb 2021 10:22:12 +0000 Subject: Remove dummy slice from bel-pin generic test Signed-off-by: gatecat --- generic/flow/bel-pin/pre_pack.py | 5 ----- 1 file changed, 5 deletions(-) diff --git a/generic/flow/bel-pin/pre_pack.py b/generic/flow/bel-pin/pre_pack.py index 2ee06d6..31ddbe9 100644 --- a/generic/flow/bel-pin/pre_pack.py +++ b/generic/flow/bel-pin/pre_pack.py @@ -1,7 +1,6 @@ ctx.addWire(name="BEL_A0", type="WIRE", x=0, y=0) ctx.addWire(name="BEL_A1", type="WIRE", x=0, y=0) ctx.addWire(name="BEL_Q", type="WIRE", x=0, y=0) -ctx.addWire(name="SLICE_F", type="WIRE", x=0, y=0) ctx.addPip(name="Q->A0", type="PIP", srcWire="BEL_Q", dstWire="BEL_A0", delay=ctx.getDelayFromNS(0.05), loc=Loc(0, 0, 0)) ctx.addPip(name="Q->A1", type="PIP", srcWire="BEL_Q", dstWire="BEL_A1", delay=ctx.getDelayFromNS(0.05), loc=Loc(0, 0, 0)) @@ -12,10 +11,6 @@ ctx.addBelInput(bel="BEL", name="A0", wire="BEL_A0") ctx.addBelInput(bel="BEL", name="A1", wire="BEL_A1") ctx.addBelOutput(bel="BEL", name="Q", wire="BEL_Q") -ctx.addBel(name="DUMMY_SLICE", type="GENERIC_SLICE", loc=Loc(0, 0, 1), gb=False, hidden=False) -ctx.addBelOutput(bel="DUMMY_SLICE", name="F", wire="SLICE_F") - - ctx.clearCellBelPinMap(cell="cell_i", cell_pin="A") ctx.addCellBelPinMapping(cell="cell_i", cell_pin="A", bel_pin="A0") ctx.addCellBelPinMapping(cell="cell_i", cell_pin="A", bel_pin="A1") -- cgit v1.2.3