From 1cd2901d854b969a8cb1afc66e3f3388766776a0 Mon Sep 17 00:00:00 2001
From: Tomasz Michalak <tmichalak@antmicro.com>
Date: Wed, 9 Jun 2021 23:01:27 +0200
Subject: fpga_interchange: Add initial site router test framework

Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
---
 .../site_router_tests/common/run_script.py         | 29 ++++++++++++++++++++++
 .../site_router_tests/common/synth.tcl             | 14 +++++++++++
 2 files changed, 43 insertions(+)
 create mode 100644 fpga_interchange/site_router_tests/common/run_script.py
 create mode 100644 fpga_interchange/site_router_tests/common/synth.tcl

(limited to 'fpga_interchange/site_router_tests/common')

diff --git a/fpga_interchange/site_router_tests/common/run_script.py b/fpga_interchange/site_router_tests/common/run_script.py
new file mode 100644
index 0000000..07faf89
--- /dev/null
+++ b/fpga_interchange/site_router_tests/common/run_script.py
@@ -0,0 +1,29 @@
+import sys
+import yaml
+import os
+
+def test_case(ctx):
+    with open(os.environ['TEST_YAML'], 'r') as f:
+        test_data = yaml.safe_load(f.read())
+        if 'test_case' in test_data:
+            ctx.pack()
+            for test_step in test_data['test_case']:
+                print(test_step)
+                if "place" in test_step:
+                    for cell, bel in test_step["place"].items():
+                      print("Binding Bel {} to Cell {}".format(bel, cell))
+                      assert cell in ctx.cells, "Cell {} does not exist".format(cell)
+                      ctx.bindBel(bel, ctx.cells[cell], STRENGTH_WEAK)
+                if "test" in test_step:
+                    print(test_step["test"])
+                    for bel, check in test_step["test"].items():
+                      print("Checking if location of bel {} is {}".format(bel, check))
+                      print("Test result: {}, isBelLocationValid: {}, expected: {}".format(ctx.isBelLocationValid(bel) == check, ctx.isBelLocationValid(bel), check))
+                if "unplace" in test_step:
+                    print(test_step["unplace"])
+                    cell = test_step["unplace"]
+                    print("Unbinding Bel {}".format(cell))
+                    ctx.explain_bel_status(cell)
+                    ctx.unbindBel(cell)
+
+test_case(ctx)
diff --git a/fpga_interchange/site_router_tests/common/synth.tcl b/fpga_interchange/site_router_tests/common/synth.tcl
new file mode 100644
index 0000000..cba4503
--- /dev/null
+++ b/fpga_interchange/site_router_tests/common/synth.tcl
@@ -0,0 +1,14 @@
+yosys -import
+
+read_verilog $::env(SOURCES)
+
+synth_xilinx -flatten -abc9 -nosrl -nocarry -nodsp
+
+# opt_expr -undriven makes sure all nets are driven, if only by the $undef
+# net.
+opt_expr -undriven
+opt_clean
+
+setundef -zero -params
+
+write_json $::env(OUT_JSON)
-- 
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