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459, 462, 465, 468 ], "attributes": { "src": "../src/serv-wb_intercon_0/wb_intercon.vh:76|../src/serv-wb_intercon_0/wb_intercon.v:136|../src/wb_intercon_1.2.2/rtl/verilog/wb_mux.v:71" } }, "wb_intercon0.wb_mux_cpu_ibus.wbm_stb_i": { "hide_name": 0, "bits": [ 303 ], "attributes": { "src": "../src/serv-wb_intercon_0/wb_intercon.vh:76|../src/serv-wb_intercon_0/wb_intercon.v:136|../src/wb_intercon_1.2.2/rtl/verilog/wb_mux.v:68" } }, "wb_intercon0.wb_mux_cpu_ibus.wbs_adr_o": { "hide_name": 0, "bits": [ 524, 1595, 833, 835, 837, 839, 841, 843, 845, 847, 849, 851, 853, 1596, 1597, 1598, 324, 325, 341, 342, 343, 344, 337, 338, 339, 340, 333, 334, 335, 336, 331, 332 ], "attributes": { "src": "../src/serv-wb_intercon_0/wb_intercon.vh:76|../src/serv-wb_intercon_0/wb_intercon.v:136|../src/wb_intercon_1.2.2/rtl/verilog/wb_mux.v:76" } }, "wb_intercon0.wb_mux_cpu_ibus.wbs_dat_i": { "hide_name": 0, "bits": [ 375, 378, 381, 384, 387, 390, 393, 396, 399, 402, 405, 408, 411, 414, 417, 420, 423, 426, 429, 432, 435, 438, 441, 444, 447, 450, 453, 456, 459, 462, 465, 468 ], "attributes": { "src": "../src/serv-wb_intercon_0/wb_intercon.vh:76|../src/serv-wb_intercon_0/wb_intercon.v:136|../src/wb_intercon_1.2.2/rtl/verilog/wb_mux.v:84" } }, "wb_intercon0.wb_mux_cpu_ibus.wbs_stb_o": { "hide_name": 0, "bits": [ 303 ], "attributes": { "src": "../src/serv-wb_intercon_0/wb_intercon.vh:76|../src/serv-wb_intercon_0/wb_intercon.v:136|../src/wb_intercon_1.2.2/rtl/verilog/wb_mux.v:81" } }, "wb_intercon0.wb_rst_i": { "hide_name": 0, "bits": [ 960 ], "attributes": { "src": "../src/serv-wb_intercon_0/wb_intercon.vh:76|../src/serv-wb_intercon_0/wb_intercon.v:5" } }, "wb_intercon0.wb_s2m_cpu_dbus_mem_ack": { "hide_name": 0, "bits": [ 1984 ], "attributes": { "src": "../src/serv-wb_intercon_0/wb_intercon.vh:76|../src/serv-wb_intercon_0/wb_intercon.v:88", "unused_bits": "0" } }, "wb_intercon0.wb_s2m_cpu_dbus_mem_dat": { "hide_name": 0, "bits": [ 375, 378, 381, 384, 387, 390, 393, 396, 399, 402, 405, 408, 411, 414, 417, 420, 423, 426, 429, 432, 435, 438, 441, 444, 447, 450, 453, 456, 459, 462, 465, 468 ], "attributes": { "src": "../src/serv-wb_intercon_0/wb_intercon.vh:76|../src/serv-wb_intercon_0/wb_intercon.v:87" } }, "wb_intercon0.wb_s2m_cpu_ibus_mem_dat": { "hide_name": 0, "bits": [ 375, 378, 381, 384, 387, 390, 393, 396, 399, 402, 405, 408, 411, 414, 417, 420, 423, 426, 429, 432, 435, 438, 441, 444, 447, 450, 453, 456, 459, 462, 465, 468 ], "attributes": { "src": "../src/serv-wb_intercon_0/wb_intercon.vh:76|../src/serv-wb_intercon_0/wb_intercon.v:99" } }, "wb_intercon0.wb_testhalt_ack_i": { "hide_name": 0, "bits": [ 266 ], "attributes": { "src": "../src/serv-wb_intercon_0/wb_intercon.vh:76|../src/serv-wb_intercon_0/wb_intercon.v:51" } }, "wb_intercon0.wb_testhalt_adr_o": { "hide_name": 0, "bits": [ 756, 1594, 247, 246, 237, 238, 240, 239, 242, 233, 234, 235, 236, 229, 230, 231, 232, 225, 226, 227, 211, 212, 214, 215, 216, 217, 208, 209, 228, 241, 222, 223 ], "attributes": { "src": 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"wb_m2s_cpu_dbus_stb": { "hide_name": 0, "bits": [ 224 ], "attributes": { "src": "../src/serv-wb_intercon_0/wb_intercon.vh:8" } }, "wb_m2s_cpu_ibus_adr": { "hide_name": 0, "bits": [ 524, 1595, 833, 835, 837, 839, 841, 843, 845, 847, 849, 851, 853, 1596, 1597, 1598, 324, 325, 341, 342, 343, 344, 337, 338, 339, 340, 333, 334, 335, 336, 331, 332 ], "attributes": { "src": "../src/serv-wb_intercon_0/wb_intercon.vh:15" } }, "wb_m2s_cpu_ibus_cyc": { "hide_name": 0, "bits": [ 303 ], "attributes": { "src": "../src/serv-wb_intercon_0/wb_intercon.vh:19" } }, "wb_m2s_cpu_ibus_stb": { "hide_name": 0, "bits": [ 303 ], "attributes": { "src": "../src/serv-wb_intercon_0/wb_intercon.vh:20" } }, "wb_m2s_mem_adr": { "hide_name": 0, "bits": [ "x", "x", 834, 836, 838, 840, 842, 844, 846, 848, 850, 852, 854, "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x" ], "attributes": { "src": "../src/serv-wb_intercon_0/wb_intercon.vh:27" } }, "wb_m2s_mem_dat": { "hide_name": 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769, 771, 773, 775, 777, 779, 781, 783, 785, 787, 789, 791, 793, 795, 797, 799, 801, 803, 805, 807, 809, 811, 813, 815, 817, 819, 821, 823, 825, 827, 829, 831 ], "attributes": { "src": "../src/serv-wb_intercon_0/wb_intercon.vh:64" } }, "wb_m2s_timer_stb": { "hide_name": 0, "bits": [ 224 ], "attributes": { "src": "../src/serv-wb_intercon_0/wb_intercon.vh:68" } }, "wb_rst": { "hide_name": 0, "bits": [ 960 ], "attributes": { "src": "../src/serv_0/bench/serv_wrapper.v:18" } }, "wb_s2m_cpu_ibus_dat": { "hide_name": 0, "bits": [ 375, 378, 381, 384, 387, 390, 393, 396, 399, 402, 405, 408, 411, 414, 417, 420, 423, 426, 429, 432, 435, 438, 441, 444, 447, 450, 453, 456, 459, 462, 465, 468 ], "attributes": { "src": "../src/serv-wb_intercon_0/wb_intercon.vh:23" } }, "wb_s2m_mem_ack": { "hide_name": 0, "bits": [ 281 ], "attributes": { "src": "../src/serv-wb_intercon_0/wb_intercon.vh:36" } }, "wb_s2m_mem_dat": { "hide_name": 0, "bits": [ 375, 378, 381, 384, 387, 390, 393, 396, 399, 402, 405, 408, 411, 414, 417, 420, 423, 426, 429, 432, 435, 438, 441, 444, 447, 450, 453, 456, 459, 462, 465, 468 ], "attributes": { "src": "../src/serv-wb_intercon_0/wb_intercon.vh:35" } }, "wb_s2m_testhalt_ack": { "hide_name": 0, "bits": [ 266 ], "attributes": { "src": "../src/serv-wb_intercon_0/wb_intercon.vh:48" } }, "wb_s2m_testprint_ack": { "hide_name": 0, "bits": [ 270 ], "attributes": { "src": "../src/serv-wb_intercon_0/wb_intercon.vh:60" } }, "wb_s2m_timer_ack": { "hide_name": 0, "bits": [ 263 ], "attributes": { "src": "../src/serv-wb_intercon_0/wb_intercon.vh:72" } }, "wb_s2m_timer_dat": { "hide_name": 0, "bits": [ 1951, 1952, 1953, 1954, 1955, 1956, 1957, 1958, 1959, 1960, 1961, 1962, 1963, 1964, 1965, 1966, 1967, 1968, 1969, 1970, 1971, 1972, 1973, 1974, 1975, 1976, 1977, 1978, 1979, 1980, 1981, 1982 ], "attributes": { "src": "../src/serv-wb_intercon_0/wb_intercon.vh:71", "unused_bits": "0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31" } } } } } }