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author | Miodrag Milanovic <mmicko@gmail.com> | 2018-08-08 10:48:05 +0200 |
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committer | Miodrag Milanovic <mmicko@gmail.com> | 2018-08-08 10:48:05 +0200 |
commit | 5df90bc5a5a273f5c50764f4045012b282e7fa36 (patch) | |
tree | 5f91c9800f958a810441120794dd28572e401c6f /ice40/arch.h | |
parent | b0741e292c7ec7191f2c92fe7695e34018469b67 (diff) | |
parent | 8553573d2485ac2ec60d1c49949c254e02d35490 (diff) | |
download | nextpnr-5df90bc5a5a273f5c50764f4045012b282e7fa36.tar.gz nextpnr-5df90bc5a5a273f5c50764f4045012b282e7fa36.tar.bz2 nextpnr-5df90bc5a5a273f5c50764f4045012b282e7fa36.zip |
Merge remote-tracking branch 'origin/master' into common_main
# Conflicts:
# ecp5/main.cc
# ice40/main.cc
Diffstat (limited to 'ice40/arch.h')
-rw-r--r-- | ice40/arch.h | 93 |
1 files changed, 46 insertions, 47 deletions
diff --git a/ice40/arch.h b/ice40/arch.h index bc968b74..73f1ea0e 100644 --- a/ice40/arch.h +++ b/ice40/arch.h @@ -400,10 +400,10 @@ struct Arch : BaseCtx mutable std::unordered_map<Loc, int> bel_by_loc; std::vector<bool> bel_carry; - std::vector<IdString> bel_to_cell; - std::vector<IdString> wire_to_net; - std::vector<IdString> pip_to_net; - std::vector<IdString> switches_locked; + std::vector<CellInfo*> bel_to_cell; + std::vector<NetInfo*> wire_to_net; + std::vector<NetInfo*> pip_to_net; + std::vector<NetInfo*> switches_locked; ArchArgs args; Arch(ArchArgs args); @@ -438,26 +438,25 @@ struct Arch : BaseCtx uint32_t getBelChecksum(BelId bel) const { return bel.index; } - void bindBel(BelId bel, IdString cell, PlaceStrength strength) + void bindBel(BelId bel, CellInfo *cell, PlaceStrength strength) { NPNR_ASSERT(bel != BelId()); - NPNR_ASSERT(bel_to_cell[bel.index] == IdString()); - auto &c = cells[cell]; + NPNR_ASSERT(bel_to_cell[bel.index] == nullptr); bel_to_cell[bel.index] = cell; - bel_carry[bel.index] = (c->type == id_icestorm_lc && c->lcInfo.carryEnable); - c->bel = bel; - c->belStrength = strength; + bel_carry[bel.index] = (cell->type == id_icestorm_lc && cell->lcInfo.carryEnable); + cell->bel = bel; + cell->belStrength = strength; refreshUiBel(bel); } void unbindBel(BelId bel) { NPNR_ASSERT(bel != BelId()); - NPNR_ASSERT(bel_to_cell[bel.index] != IdString()); - cells[bel_to_cell[bel.index]]->bel = BelId(); - cells[bel_to_cell[bel.index]]->belStrength = STRENGTH_NONE; - bel_to_cell[bel.index] = IdString(); + NPNR_ASSERT(bel_to_cell[bel.index] != nullptr); + bel_to_cell[bel.index]->bel = BelId(); + bel_to_cell[bel.index]->belStrength = STRENGTH_NONE; + bel_to_cell[bel.index] = nullptr; bel_carry[bel.index] = false; refreshUiBel(bel); } @@ -465,16 +464,16 @@ struct Arch : BaseCtx bool checkBelAvail(BelId bel) const { NPNR_ASSERT(bel != BelId()); - return bel_to_cell[bel.index] == IdString(); + return bel_to_cell[bel.index] == nullptr; } - IdString getBoundBelCell(BelId bel) const + CellInfo *getBoundBelCell(BelId bel) const { NPNR_ASSERT(bel != BelId()); return bel_to_cell[bel.index]; } - IdString getConflictingBelCell(BelId bel) const + CellInfo *getConflictingBelCell(BelId bel) const { NPNR_ASSERT(bel != BelId()); return bel_to_cell[bel.index]; @@ -526,49 +525,49 @@ struct Arch : BaseCtx uint32_t getWireChecksum(WireId wire) const { return wire.index; } - void bindWire(WireId wire, IdString net, PlaceStrength strength) + void bindWire(WireId wire, NetInfo *net, PlaceStrength strength) { NPNR_ASSERT(wire != WireId()); - NPNR_ASSERT(wire_to_net[wire.index] == IdString()); + NPNR_ASSERT(wire_to_net[wire.index] == nullptr); wire_to_net[wire.index] = net; - nets[net]->wires[wire].pip = PipId(); - nets[net]->wires[wire].strength = strength; + net->wires[wire].pip = PipId(); + net->wires[wire].strength = strength; refreshUiWire(wire); } void unbindWire(WireId wire) { NPNR_ASSERT(wire != WireId()); - NPNR_ASSERT(wire_to_net[wire.index] != IdString()); + NPNR_ASSERT(wire_to_net[wire.index] != nullptr); - auto &net_wires = nets[wire_to_net[wire.index]]->wires; + auto &net_wires = wire_to_net[wire.index]->wires; auto it = net_wires.find(wire); NPNR_ASSERT(it != net_wires.end()); auto pip = it->second.pip; if (pip != PipId()) { - pip_to_net[pip.index] = IdString(); - switches_locked[chip_info->pip_data[pip.index].switch_index] = IdString(); + pip_to_net[pip.index] = nullptr; + switches_locked[chip_info->pip_data[pip.index].switch_index] = nullptr; } net_wires.erase(it); - wire_to_net[wire.index] = IdString(); + wire_to_net[wire.index] = nullptr; refreshUiWire(wire); } bool checkWireAvail(WireId wire) const { NPNR_ASSERT(wire != WireId()); - return wire_to_net[wire.index] == IdString(); + return wire_to_net[wire.index] == nullptr; } - IdString getBoundWireNet(WireId wire) const + NetInfo *getBoundWireNet(WireId wire) const { NPNR_ASSERT(wire != WireId()); return wire_to_net[wire.index]; } - IdString getConflictingWireNet(WireId wire) const + NetInfo *getConflictingWireNet(WireId wire) const { NPNR_ASSERT(wire != WireId()); return wire_to_net[wire.index]; @@ -606,21 +605,21 @@ struct Arch : BaseCtx PipId getPipByName(IdString name) const; - void bindPip(PipId pip, IdString net, PlaceStrength strength) + void bindPip(PipId pip, NetInfo *net, PlaceStrength strength) { NPNR_ASSERT(pip != PipId()); - NPNR_ASSERT(pip_to_net[pip.index] == IdString()); - NPNR_ASSERT(switches_locked[chip_info->pip_data[pip.index].switch_index] == IdString()); + NPNR_ASSERT(pip_to_net[pip.index] == nullptr); + NPNR_ASSERT(switches_locked[chip_info->pip_data[pip.index].switch_index] == nullptr); pip_to_net[pip.index] = net; switches_locked[chip_info->pip_data[pip.index].switch_index] = net; WireId dst; dst.index = chip_info->pip_data[pip.index].dst; - NPNR_ASSERT(wire_to_net[dst.index] == IdString()); + NPNR_ASSERT(wire_to_net[dst.index] == nullptr); wire_to_net[dst.index] = net; - nets[net]->wires[dst].pip = pip; - nets[net]->wires[dst].strength = strength; + net->wires[dst].pip = pip; + net->wires[dst].strength = strength; refreshUiPip(pip); refreshUiWire(dst); } @@ -628,17 +627,17 @@ struct Arch : BaseCtx void unbindPip(PipId pip) { NPNR_ASSERT(pip != PipId()); - NPNR_ASSERT(pip_to_net[pip.index] != IdString()); - NPNR_ASSERT(switches_locked[chip_info->pip_data[pip.index].switch_index] != IdString()); + NPNR_ASSERT(pip_to_net[pip.index] != nullptr); + NPNR_ASSERT(switches_locked[chip_info->pip_data[pip.index].switch_index] != nullptr); WireId dst; dst.index = chip_info->pip_data[pip.index].dst; - NPNR_ASSERT(wire_to_net[dst.index] != IdString()); - wire_to_net[dst.index] = IdString(); - nets[pip_to_net[pip.index]]->wires.erase(dst); + NPNR_ASSERT(wire_to_net[dst.index] != nullptr); + wire_to_net[dst.index] = nullptr; + pip_to_net[pip.index]->wires.erase(dst); - pip_to_net[pip.index] = IdString(); - switches_locked[chip_info->pip_data[pip.index].switch_index] = IdString(); + pip_to_net[pip.index] = nullptr; + switches_locked[chip_info->pip_data[pip.index].switch_index] = nullptr; refreshUiPip(pip); refreshUiWire(dst); } @@ -649,12 +648,12 @@ struct Arch : BaseCtx auto &pi = chip_info->pip_data[pip.index]; auto &si = chip_info->bits_info->switches[pi.switch_index]; - if (switches_locked[pi.switch_index] != IdString()) + if (switches_locked[pi.switch_index] != nullptr) return false; if (pi.flags & PipInfoPOD::FLAG_ROUTETHRU) { NPNR_ASSERT(si.bel >= 0); - if (bel_to_cell[si.bel] != IdString()) + if (bel_to_cell[si.bel] != nullptr) return false; } @@ -667,13 +666,13 @@ struct Arch : BaseCtx return true; } - IdString getBoundPipNet(PipId pip) const + NetInfo *getBoundPipNet(PipId pip) const { NPNR_ASSERT(pip != PipId()); return pip_to_net[pip.index]; } - IdString getConflictingPipNet(PipId pip) const + NetInfo *getConflictingPipNet(PipId pip) const { NPNR_ASSERT(pip != PipId()); return switches_locked[chip_info->pip_data[pip.index].switch_index]; @@ -768,7 +767,7 @@ struct Arch : BaseCtx delay_t getRipupDelayPenalty() const { return 200; } float getDelayNS(delay_t v) const { return v * 0.001; } uint32_t getDelayChecksum(delay_t v) const { return v; } - delay_t getBudgetOverride(const NetInfo *net_info, const PortRef &sink, delay_t budget) const; + bool getBudgetOverride(const NetInfo *net_info, const PortRef &sink, delay_t &budget) const; // ------------------------------------------------- |