diff options
130 files changed, 13924 insertions, 1344 deletions
diff --git a/.cirrus.yml b/.cirrus.yml new file mode 100644 index 00000000..5cac994e --- /dev/null +++ b/.cirrus.yml @@ -0,0 +1,16 @@ +task: + name: build-test-ubuntu1604 + container: + cpu: 4 + memory: 20 + dockerfile: .cirrus/Dockerfile.ubuntu16.04 + + build_script: mkdir build && cd build && cmake .. -DARCH=all -DTRELLIS_ROOT=/usr/local/src/prjtrellis -DBUILD_TESTS=on && make -j $(nproc) + submodule_script: git submodule sync --recursive && git submodule update --init --recursive + test_generic_script: cd build && ./nextpnr-generic-test + test_ice40_script: cd build && ./nextpnr-ice40-test + smoketest_ice40_script: export NEXTPNR=$(pwd)/build/nextpnr-ice40 && cd ice40/smoketest/attosoc && ./smoketest.sh + test_ecp5_script: cd build && ./nextpnr-ecp5-test + smoketest_generic_script: export NEXTPNR=$(pwd)/build/nextpnr-generic && cd generic/examples && ./simple.sh + regressiontest_ice40_script: make -j $(nproc) -C tests/ice40/regressions NPNR=$(pwd)/build/nextpnr-ice40 + regressiontest_ecp5_script: make -j $(nproc) -C tests/ecp5/regressions NPNR=$(pwd)/build/nextpnr-ecp5 diff --git a/.cirrus/Dockerfile.ubuntu16.04 b/.cirrus/Dockerfile.ubuntu16.04 new file mode 100644 index 00000000..4b149b7b --- /dev/null +++ b/.cirrus/Dockerfile.ubuntu16.04 @@ -0,0 +1,53 @@ +FROM ubuntu:xenial-20181113 + +ENV DEBIAN_FRONTEND=noninteractive + +RUN set -e -x ;\ + apt-get -y update ;\ + apt-get -y upgrade ;\ + apt-get -y install \ + build-essential autoconf cmake clang bison wget flex gperf \ + libreadline-dev gawk tcl-dev libffi-dev graphviz xdot python3-dev \ + libboost-all-dev qt5-default git libftdi-dev pkg-config libeigen3-dev + +RUN set -e -x ;\ + mkdir -p /usr/local/src ;\ + cd /usr/local/src ;\ + git clone --recursive https://github.com/steveicarus/iverilog.git ;\ + cd iverilog ;\ + git reset --hard 172d7eb0a3665f89b91d601b5912c33acedc81e5 ;\ + sh autoconf.sh ;\ + ./configure ;\ + make -j $(nproc) ;\ + make install ;\ + rm -rf /usr/local/src/iverilog + +RUN set -e -x ;\ + mkdir -p /usr/local/src ;\ + cd /usr/local/src ;\ + git clone --recursive https://github.com/cliffordwolf/icestorm.git ;\ + cd icestorm ;\ + git reset --hard 3a2bfee5cbc0558641668114260d3f644d6b7c83 ;\ + make -j $(nproc) ;\ + make install + +RUN set -e -x ;\ + mkdir -p /usr/local/src ;\ + cd /usr/local/src ;\ + git clone --recursive https://github.com/YosysHQ/yosys.git ;\ + cd yosys ;\ + git reset --hard ea8ac0aaad3a1f89ead8eb44b2fef5927f29a099 ;\ + make -j $(nproc) ;\ + make install ;\ + rm -rf /usr/local/src/yosys + +RUN set -e -x ;\ + mkdir -p /usr/local/src ;\ + cd /usr/local/src ;\ + git clone --recursive https://github.com/SymbiFlow/prjtrellis.git ;\ + cd prjtrellis ;\ + git reset --hard 46e95314be7f8850db80ad1ef6b3359b091fad93 ;\ + cd libtrellis ;\ + cmake -DCMAKE_INSTALL_PREFIX=/usr . ;\ + make -j $(nproc) ;\ + make install diff --git a/.gitmodules b/.gitmodules new file mode 100644 index 00000000..52194b76 --- /dev/null +++ b/.gitmodules @@ -0,0 +1,3 @@ +[submodule "tests"] + path = tests + url = https://github.com/YosysHQ/nextpnr-tests diff --git a/3rdparty/python-console/modified/pyinterpreter.cc b/3rdparty/python-console/modified/pyinterpreter.cc index f53207ad..89c9b88c 100644 --- a/3rdparty/python-console/modified/pyinterpreter.cc +++ b/3rdparty/python-console/modified/pyinterpreter.cc @@ -153,3 +153,25 @@ void pyinterpreter_release() { PyEval_ReleaseThread(m_threadState); } + +std::string pyinterpreter_execute_file(const char *python_file, int *errorCode) +{ + PyEval_AcquireThread(m_threadState); + *errorCode = 0; + std::string res; + FILE *fp = fopen(python_file, "r"); + if (fp == NULL) { + *errorCode = 1; + res = "Fatal error: file not found " + std::string(python_file) + "\n"; + return res; + } + + if (PyRun_SimpleFile(fp, python_file)==-1) { + *errorCode = 1; + PyErr_Print(); + } + res = redirector_take_output(m_threadState); + + PyEval_ReleaseThread(m_threadState); + return res; +} diff --git a/3rdparty/python-console/modified/pyinterpreter.h b/3rdparty/python-console/modified/pyinterpreter.h index 1a85c1fb..48512507 100644 --- a/3rdparty/python-console/modified/pyinterpreter.h +++ b/3rdparty/python-console/modified/pyinterpreter.h @@ -33,4 +33,5 @@ void pyinterpreter_initialize(); void pyinterpreter_finalize(); void pyinterpreter_aquire(); void pyinterpreter_release(); +std::string pyinterpreter_execute_file(const char *python_file, int *errorCode); #endif // PYINTERPRETER_H diff --git a/CMakeLists.txt b/CMakeLists.txt index 33a703d5..ade76d60 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -5,8 +5,11 @@ project(nextpnr) option(BUILD_GUI "Build GUI" ON) option(BUILD_PYTHON "Build Python Integration" ON) option(BUILD_TESTS "Build GUI" OFF) +option(BUILD_HEAP "Build HeAP analytic placer" ON) +option(USE_OPENMP "Use OpenMP to accelerate analytic placer" OFF) option(COVERAGE "Add code coverage info" OFF) option(STATIC_BUILD "Create static build" OFF) +option(EXTERNAL_CHIPDB "Create build with pre-built chipdb binaries" OFF) set(link_param "") if (STATIC_BUILD) @@ -16,6 +19,14 @@ if (STATIC_BUILD) endif() endif() +if (EXTERNAL_CHIPDB) + if (NOT DEFINED EXTERNAL_CHIPDB_ROOT) + message(STATUS "EXTERNAL_CHIPDB_ROOT not defined using -DEXTERNAL_CHIPDB_ROOT=/path/to/nextpnr. Default to /usr/share/nextpnr") + set(EXTERNAL_CHIPDB_ROOT "/usr/share/nextpnr") + endif() + add_definitions("-DEXTERNAL_CHIPDB_ROOT=\"${EXTERNAL_CHIPDB_ROOT}\"") +endif() + # List of families to build set(FAMILIES generic ice40 ecp5) @@ -44,12 +55,16 @@ endforeach() set(CMAKE_CXX_STANDARD 11) if (MSVC) -set(CMAKE_CONFIGURATION_TYPES "Debug;Release" CACHE STRING "" FORCE) -set(CMAKE_CXX_FLAGS_DEBUG "${CMAKE_CXX_FLAGS_DEBUG} /D_DEBUG /W4 /wd4100 /wd4244 /wd4125 /wd4800 /wd4456 /wd4458 /wd4305 /wd4459 /wd4121 /wd4996") -set(CMAKE_CXX_FLAGS_RELEASE "${CMAKE_CXX_FLAGS_RELEASE} /W4 /wd4100 /wd4244 /wd4125 /wd4800 /wd4456 /wd4458 /wd4305 /wd4459 /wd4121 /wd4996 /wd4127") + set(CMAKE_CONFIGURATION_TYPES "Debug;Release" CACHE STRING "" FORCE) + set(CMAKE_CXX_FLAGS_DEBUG "${CMAKE_CXX_FLAGS_DEBUG} /D_DEBUG /W4 /wd4100 /wd4244 /wd4125 /wd4800 /wd4456 /wd4458 /wd4305 /wd4459 /wd4121 /wd4996") + set(CMAKE_CXX_FLAGS_RELEASE "${CMAKE_CXX_FLAGS_RELEASE} /W4 /wd4100 /wd4244 /wd4125 /wd4800 /wd4456 /wd4458 /wd4305 /wd4459 /wd4121 /wd4996 /wd4127") else() -set(CMAKE_CXX_FLAGS_DEBUG "-Wall -fPIC -ggdb -pipe") -set(CMAKE_CXX_FLAGS_RELEASE "-Wall -fPIC -O3 -g -pipe") + set(CMAKE_CXX_FLAGS_DEBUG "-Wall -fPIC -ggdb -pipe") + if (USE_OPENMP) + set(CMAKE_CXX_FLAGS_RELEASE "-Wall -fPIC -O3 -g -pipe -fopenmp") + else() + set(CMAKE_CXX_FLAGS_RELEASE "-Wall -fPIC -O3 -g -pipe") + endif() endif() set(CMAKE_DEFIN) @@ -66,7 +81,7 @@ endif() find_package(Sanitizers) # List of Boost libraries to include -set(boost_libs filesystem thread program_options) +set(boost_libs filesystem thread program_options iostreams) if (BUILD_GUI AND NOT BUILD_PYTHON) message(FATAL_ERROR "GUI requires Python to build") @@ -172,6 +187,14 @@ if (BUILD_PYTHON) endif() include_directories(common/ json/ ${Boost_INCLUDE_DIRS} ${PYTHON_INCLUDE_DIRS}) + +if(BUILD_HEAP) + find_package (Eigen3 REQUIRED NO_MODULE) + include_directories(${EIGEN3_INCLUDE_DIRS}) + add_definitions(${EIGEN3_DEFINITIONS}) + add_definitions(-DWITH_HEAP) +endif() + aux_source_directory(common/ COMMON_SRC_FILES) aux_source_directory(json/ JSON_PARSER_FILES) set(COMMON_FILES ${COMMON_SRC_FILES} ${JSON_PARSER_FILES}) @@ -36,10 +36,12 @@ of the selected architecture: - Python 3.5 or later, including development libraries (`python3-dev` for Ubuntu) - on Windows make sure to install same version as supported by [vcpkg](https://github.com/Microsoft/vcpkg/blob/master/ports/python3/CONTROL) - Boost libraries (`libboost-dev libboost-filesystem-dev libboost-thread-dev libboost-program-options-dev libboost-python-dev libboost-dev` or `libboost-all-dev` for Ubuntu) +- Eigen3 (`libeigen3-dev` for Ubuntu) is required to build the analytic placer - Latest git Yosys is required to synthesise the demo design - For building on Windows with MSVC, usage of vcpkg is advised for dependency installation. - - For 32 bit builds: `vcpkg install boost-filesystem boost-program-options boost-thread boost-python qt5-base` - - For 64 bit builds: `vcpkg install boost-filesystem:x64-windows boost-program-options:x64-windows boost-thread:x64-windows boost-python:x64-windows qt5-base:x64-windows` + - For 32 bit builds: `vcpkg install boost-filesystem boost-program-options boost-thread boost-python qt5-base eigen3` + - For 64 bit builds: `vcpkg install boost-filesystem:x64-windows boost-program-options:x64-windows boost-thread:x64-windows boost-python:x64-windows qt5-base:x64-windows eigen3:x64-windows` + - A copy of Python that matches the version in vcpkg (currently Python 3.6.4). You can download the [Embeddable Zip File](https://www.python.org/downloads/release/python-364/) and extract it. You may need to extract `python36.zip` within the embeddable zip file to a new directory called "Lib". - For building on macOS, brew utility is needed. - Install all needed packages `brew install cmake python boost boost-python3 qt5` - Do not forget to add qt5 in path as well `echo 'export PATH="/usr/local/opt/qt/bin:$PATH"' >> ~/.bash_profile` @@ -49,8 +51,9 @@ Getting started ### nextpnr-ice40 -To build the iCE40 version of nextpnr, install [icestorm](http://www.clifford.at/icestorm/) with chipdbs installed in `/usr/local/share/icebox` -(or another location, which should be passed as -DICEBOX_ROOT=/path/to/icebox to CMake). +To build the iCE40 version of nextpnr, install [icestorm](http://www.clifford.at/icestorm/) with chipdbs installed in `/usr/local/share/icebox`, +or another location, which should be passed as `-DICEBOX_ROOT=/path/to/share/icebox` (ensure to point it to `share/icebox` and not where the +icebox binaries are installed) to CMake. Then build and install `nextpnr-ice40` using the following commands: ``` @@ -59,11 +62,18 @@ make -j$(nproc) sudo make install ``` -A simple example that runs on the iCEstick dev board can be found in `ice40/blinky.*`. +On Windows, you may specify paths explicitly: + +``` +cmake -DARCH=ice40 -DICEBOX_ROOT=C:/ProgramData/icestorm/share/icebox -DCMAKE_TOOLCHAIN_FILE=C:/vcpkg/scripts/buildsystems/vcpkg.cmake -DVCPKG_TARGET_TRIPLET=x64-windows -G "Visual Studio 15 2017 Win64" -DPYTHON_EXECUTABLE=C:/Python364/python.exe -DPYTHON_LIBRARY=C:/vcpkg/packages/python3_x64-windows/lib/python36.lib -DPYTHON_INCLUDE_DIR=C:/vcpkg/packages/python3_x64-windows/include/python3.6 +cmake --build . --config Release +``` + +A simple example that runs on the iCEstick dev board can be found in `ice40/examples/blinky/blinky.*`. Usage example: ``` -cd ice40 +cd ice40/examples/blinky yosys -p 'synth_ice40 -top blinky -json blinky.json' blinky.v # synthesize into blinky.json nextpnr-ice40 --hx1k --json blinky.json --pcf blinky.pcf --asc blinky.asc # run place and route icepack blinky.asc blinky.bin # generate binary bitstream file @@ -118,11 +128,11 @@ Use cmake `-D` options to specify which version of nextpnr you want to build. Use `-DARCH=...` to set the architecture. It is a semicolon separated list. Use `cmake . -DARCH=all` to build all supported architectures. -The following runs a debug build of the iCE40 architecture without GUI -and without Python support and only HX1K support: +The following runs a debug build of the iCE40 architecture without GUI, + without Python support, without the HeAP analytic placer and only HX1K support: ``` -cmake -DARCH=ice40 -DCMAKE_BUILD_TYPE=Debug -DBUILD_PYTHON=OFF -DBUILD_GUI=OFF -DICE40_HX1K_ONLY=1 . +cmake -DARCH=ice40 -DCMAKE_BUILD_TYPE=Debug -DBUILD_PYTHON=OFF -DBUILD_GUI=OFF -DBUILD_HEAP=OFF -DICE40_HX1K_ONLY=1 . make -j$(nproc) ``` @@ -133,6 +143,9 @@ cmake -DARCH=ice40 -DBUILD_PYTHON=OFF -DBUILD_GUI=OFF -DSTATIC_BUILD=ON . make -j$(nproc) ``` +The HeAP placer's solver can optionally use OpenMP for a speedup on very large designs. Enable this by passing +`-DUSE_OPENMP=yes` to cmake (compiler support may vary). + You can change the location where nextpnr will be installed (this will usually default to `/usr/local`) by using `-DCMAKE_INSTALL_PREFIX=/install/prefix`. diff --git a/common/chain_utils.h b/common/chain_utils.h index b783e30b..300d96a1 100644 --- a/common/chain_utils.h +++ b/common/chain_utils.h @@ -51,7 +51,8 @@ std::vector<CellChain> find_chains(const Context *ctx, F1 cell_type_predicate, F CellChain chain; CellInfo *end = start; while (end != nullptr) { - chain.cells.push_back(end); + if (chained.insert(end->name).second) + chain.cells.push_back(end); end = get_next(ctx, end); } if (chain.cells.size() >= min_length) { diff --git a/common/command.cc b/common/command.cc index d332375a..49081e72 100644 --- a/common/command.cc +++ b/common/command.cc @@ -27,6 +27,7 @@ #include "pybindings.h" #endif +#include <boost/algorithm/string/join.hpp> #include <boost/filesystem/convenience.hpp> #include <boost/program_options.hpp> #include <fstream> @@ -77,6 +78,20 @@ bool CommandHandler::executeBeforeContext() return true; } validate(); + + if (vm.count("quiet")) { + log_streams.push_back(std::make_pair(&std::cerr, LogLevel::WARNING_MSG)); + } else { + log_streams.push_back(std::make_pair(&std::cerr, LogLevel::LOG_MSG)); + } + + if (vm.count("log")) { + std::string logfilename = vm["log"].as<std::string>(); + logfile.open(logfilename); + if (!logfile.is_open()) + log_error("Failed to open log file '%s' for writing.\n", logfilename.c_str()); + log_streams.push_back(std::make_pair(&logfile, LogLevel::LOG_MSG)); + } return false; } @@ -106,13 +121,26 @@ po::options_description CommandHandler::getGeneralOptions() general.add_options()("json", po::value<std::string>(), "JSON design file to ingest"); general.add_options()("seed", po::value<int>(), "seed value for random number generator"); general.add_options()("randomize-seed,r", "randomize seed value for random number generator"); + + general.add_options()( + "placer", po::value<std::string>(), + std::string("placer algorithm to use; available: " + boost::algorithm::join(Arch::availablePlacers, ", ") + + "; default: " + Arch::defaultPlacer) + .c_str()); + general.add_options()("slack_redist_iter", po::value<int>(), "number of iterations between slack redistribution"); general.add_options()("cstrweight", po::value<float>(), "placer weighting for relative constraint satisfaction"); + general.add_options()("starttemp", po::value<float>(), "placer SA start temperature"); + general.add_options()("placer-budgets", "use budget rather than criticality in placer timing weights"); + general.add_options()("pack-only", "pack design only without placement or routing"); + general.add_options()("ignore-loops", "ignore combinational loops in timing analysis"); + general.add_options()("version,V", "show version"); general.add_options()("test", "check architecture database integrity"); general.add_options()("freq", po::value<double>(), "set target frequency for design in MHz"); + general.add_options()("timing-allow-fail", "allow timing to fail in design"); general.add_options()("no-tmdriv", "disable timing-driven placement"); general.add_options()("save", po::value<std::string>(), "project file to write"); general.add_options()("load", po::value<std::string>(), "project file to read"); @@ -130,20 +158,6 @@ void CommandHandler::setupContext(Context *ctx) ctx->debug = true; } - if (vm.count("quiet")) { - log_streams.push_back(std::make_pair(&std::cerr, LogLevel::WARNING_MSG)); - } else { - log_streams.push_back(std::make_pair(&std::cerr, LogLevel::LOG_MSG)); - } - - if (vm.count("log")) { - std::string logfilename = vm["log"].as<std::string>(); - logfile = std::ofstream(logfilename); - if (!logfile) - log_error("Failed to open log file '%s' for writing.\n", logfilename.c_str()); - log_streams.push_back(std::make_pair(&logfile, LogLevel::LOG_MSG)); - } - if (vm.count("force")) { ctx->force = true; } @@ -172,10 +186,35 @@ void CommandHandler::setupContext(Context *ctx) } } + if (vm.count("ignore-loops")) { + settings->set("timing/ignoreLoops", true); + } + + if (vm.count("timing-allow-fail")) { + settings->set("timing/allowFail", true); + } + + if (vm.count("placer")) { + std::string placer = vm["placer"].as<std::string>(); + if (std::find(Arch::availablePlacers.begin(), Arch::availablePlacers.end(), placer) == + Arch::availablePlacers.end()) + log_error("Placer algorithm '%s' is not supported (available options: %s)\n", placer.c_str(), + boost::algorithm::join(Arch::availablePlacers, ", ").c_str()); + settings->set("placer", placer); + } else { + settings->set("placer", Arch::defaultPlacer); + } + if (vm.count("cstrweight")) { settings->set("placer1/constraintWeight", vm["cstrweight"].as<float>()); } + if (vm.count("starttemp")) { + settings->set("placer1/startTemp", vm["starttemp"].as<float>()); + } + if (vm.count("placer-budgets")) { + settings->set("placer1/budgetBased", true); + } if (vm.count("freq")) { auto freq = vm["freq"].as<double>(); if (freq > 0) diff --git a/common/design_utils.cc b/common/design_utils.cc index a0b87764..bdf5ca5c 100644 --- a/common/design_utils.cc +++ b/common/design_utils.cc @@ -27,6 +27,8 @@ NEXTPNR_NAMESPACE_BEGIN void replace_port(CellInfo *old_cell, IdString old_name, CellInfo *rep_cell, IdString rep_name) { + if (!old_cell->ports.count(old_name)) + return; PortInfo &old = old_cell->ports.at(old_name); PortInfo &rep = rep_cell->ports.at(rep_name); NPNR_ASSERT(old.type == rep.type); @@ -107,6 +109,8 @@ void disconnect_port(const Context *ctx, CellInfo *cell, IdString port_name) return user.cell == cell && user.port == port_name; }), port.net->users.end()); + if (port.net->driver.cell == cell && port.net->driver.port == port_name) + port.net->driver.cell = nullptr; } } @@ -125,4 +129,21 @@ void connect_ports(Context *ctx, CellInfo *cell1, IdString port1_name, CellInfo connect_port(ctx, port1.net, cell2, port2_name); } +void rename_port(Context *ctx, CellInfo *cell, IdString old_name, IdString new_name) +{ + if (!cell->ports.count(old_name)) + return; + PortInfo pi = cell->ports.at(old_name); + if (pi.net != nullptr) { + if (pi.net->driver.cell == cell && pi.net->driver.port == old_name) + pi.net->driver.port = new_name; + for (auto &usr : pi.net->users) + if (usr.cell == cell && usr.port == old_name) + usr.port = new_name; + } + cell->ports.erase(old_name); + pi.name = new_name; + cell->ports[new_name] = pi; +} + NEXTPNR_NAMESPACE_END diff --git a/common/design_utils.h b/common/design_utils.h index 8a42d21f..3eb9024f 100644 --- a/common/design_utils.h +++ b/common/design_utils.h @@ -91,6 +91,9 @@ void disconnect_port(const Context *ctx, CellInfo *cell, IdString port_name); // Connect two ports together void connect_ports(Context *ctx, CellInfo *cell1, IdString port1_name, CellInfo *cell2, IdString port2_name); +// Rename a port if it exists on a cell +void rename_port(Context *ctx, CellInfo *cell, IdString old_name, IdString new_name); + void print_utilisation(const Context *ctx); NEXTPNR_NAMESPACE_END diff --git a/common/nextpnr.cc b/common/nextpnr.cc index bb941d3d..daaadf28 100644 --- a/common/nextpnr.cc +++ b/common/nextpnr.cc @@ -221,6 +221,9 @@ delay_t Context::getNetinfoRouteDelay(const NetInfo *net_info, const PortRef &us return 0; #endif + if (net_info->wires.empty()) + return predictDelay(net_info, user_info); + WireId src_wire = getNetinfoSourceWire(net_info); if (src_wire == WireId()) return 0; @@ -421,4 +424,33 @@ void BaseCtx::addClock(IdString net, float freq) } } +void BaseCtx::createRectangularRegion(IdString name, int x0, int y0, int x1, int y1) +{ + std::unique_ptr<Region> new_region(new Region()); + new_region->name = name; + new_region->constr_bels = true; + new_region->constr_pips = false; + new_region->constr_wires = false; + for (int x = x0; x <= x1; x++) { + for (int y = y0; y <= y1; y++) { + for (auto bel : getCtx()->getBelsByTile(x, y)) + new_region->bels.insert(bel); + } + } + region[name] = std::move(new_region); +} +void BaseCtx::addBelToRegion(IdString name, BelId bel) { region[name]->bels.insert(bel); } +void BaseCtx::constrainCellToRegion(IdString cell, IdString region_name) +{ + cells[cell]->region = region[region_name].get(); +} +DecalXY BaseCtx::constructDecalXY(DecalId decal, float x, float y) +{ + DecalXY dxy; + dxy.decal = decal; + dxy.x = x; + dxy.y = y; + return dxy; +} + NEXTPNR_NAMESPACE_END diff --git a/common/nextpnr.h b/common/nextpnr.h index d58ae529..fc49300e 100644 --- a/common/nextpnr.h +++ b/common/nextpnr.h @@ -181,6 +181,9 @@ struct GraphicElement float x1 = 0, y1 = 0, x2 = 0, y2 = 0, z = 0; std::string text; + GraphicElement(){}; + GraphicElement(type_t type, style_t style, float x1, float y1, float x2, float y2, float z) + : type(type), style(style), x1(x1), y1(y1), x2(x2), y2(y2), z(z){}; }; struct Loc @@ -637,6 +640,12 @@ struct BaseCtx // Intended to simplify Python API void addClock(IdString net, float freq); + void createRectangularRegion(IdString name, int x0, int y0, int x1, int y1); + void addBelToRegion(IdString name, BelId bel); + void constrainCellToRegion(IdString cell, IdString region_name); + + // Workaround for lack of wrappable constructors + DecalXY constructDecalXY(DecalId decal, float x, float y); }; NEXTPNR_NAMESPACE_END diff --git a/common/place_common.cc b/common/place_common.cc index b3eb4267..73a320d0 100644 --- a/common/place_common.cc +++ b/common/place_common.cc @@ -304,7 +304,7 @@ class ConstraintLegaliseWorker // Set the strength to locked on all cells in chain void lockdown_chain(CellInfo *root) { - root->belStrength = STRENGTH_LOCKED; + root->belStrength = STRENGTH_STRONG; for (auto child : root->constr_children) lockdown_chain(child); } @@ -380,7 +380,7 @@ class ConstraintLegaliseWorker rippedCells.insert(confl_cell->name); } } - ctx->bindBel(target, ctx->cells.at(cp.first).get(), STRENGTH_LOCKED); + ctx->bindBel(target, ctx->cells.at(cp.first).get(), STRENGTH_STRONG); rippedCells.erase(cp.first); } for (auto cp : solution) { @@ -529,4 +529,12 @@ int get_constraints_distance(const Context *ctx, const CellInfo *cell) return dist; } +bool check_cell_bel_region(const CellInfo *cell, BelId bel) +{ + if (cell->region != nullptr && cell->region->constr_bels && !cell->region->bels.count(bel)) + return false; + else + return true; +} + NEXTPNR_NAMESPACE_END diff --git a/common/place_common.h b/common/place_common.h index 79dec067..fa5ce4c2 100644 --- a/common/place_common.h +++ b/common/place_common.h @@ -49,6 +49,10 @@ bool legalise_relative_constraints(Context *ctx); // Get the total distance from satisfied constraints for a cell int get_constraints_distance(const Context *ctx, const CellInfo *cell); + +// Check that a Bel is within the region for a cell +bool check_cell_bel_region(const CellInfo *cell, BelId bel); + NEXTPNR_NAMESPACE_END #endif diff --git a/common/placer1.cc b/common/placer1.cc index b42ef2ff..a8ddd8a6 100644 --- a/common/placer1.cc +++ b/common/placer1.cc @@ -24,6 +24,8 @@ #include "placer1.h" #include <algorithm> #include <boost/lexical_cast.hpp> +#include <boost/range/adaptor/reversed.hpp> +#include <chrono> #include <cmath> #include <iostream> #include <limits> @@ -42,10 +44,33 @@ #include "timing.h" #include "util.h" +namespace std { +template <> struct hash<std::pair<NEXTPNR_NAMESPACE_PREFIX IdString, std::size_t>> +{ + std::size_t operator()(const std::pair<NEXTPNR_NAMESPACE_PREFIX IdString, std::size_t> &idp) const noexcept + { + std::size_t seed = 0; + boost::hash_combine(seed, hash<NEXTPNR_NAMESPACE_PREFIX IdString>()(idp.first)); + boost::hash_combine(seed, hash<std::size_t>()(idp.second)); + return seed; + } +}; +} // namespace std + NEXTPNR_NAMESPACE_BEGIN class SAPlacer { + private: + struct BoundingBox + { + // Actual bounding box + int x0 = 0, x1 = 0, y0 = 0, y1 = 0; + // Number of cells at each extremity + int nx0 = 0, nx1 = 0, ny0 = 0, ny1 = 0; + wirelen_t hpwl() const { return wirelen_t((x1 - x0) + (y1 - y0)); } + }; + public: SAPlacer(Context *ctx, Placer1Cfg cfg) : ctx(ctx), cfg(cfg) { @@ -77,13 +102,41 @@ class SAPlacer } diameter = std::max(max_x, max_y) + 1; - costs.resize(ctx->nets.size()); + net_bounds.resize(ctx->nets.size()); + net_arc_tcost.resize(ctx->nets.size()); old_udata.reserve(ctx->nets.size()); + net_by_udata.reserve(ctx->nets.size()); decltype(NetInfo::udata) n = 0; for (auto &net : ctx->nets) { old_udata.emplace_back(net.second->udata); + net_arc_tcost.at(n).resize(net.second->users.size()); net.second->udata = n++; + net_by_udata.push_back(net.second.get()); } + for (auto ®ion : sorted(ctx->region)) { + Region *r = region.second; + BoundingBox bb; + if (r->constr_bels) { + bb.x0 = std::numeric_limits<int>::max(); + bb.x1 = std::numeric_limits<int>::min(); + bb.y0 = std::numeric_limits<int>::max(); + bb.y1 = std::numeric_limits<int>::min(); + for (auto bel : r->bels) { + Loc loc = ctx->getBelLocation(bel); + bb.x0 = std::min(bb.x0, loc.x); + bb.x1 = std::max(bb.x1, loc.x); + bb.y0 = std::min(bb.y0, loc.y); + bb.y1 = std::max(bb.y1, loc.y); + } + } else { + bb.x0 = 0; + bb.y0 = 0; + bb.x1 = max_x; + bb.y1 = max_y; + } + region_bounds[r->name] = bb; + } + build_port_index(); } ~SAPlacer() @@ -92,95 +145,122 @@ class SAPlacer net.second->udata = old_udata[net.second->udata]; } - bool place() + bool place(bool refine = false) { log_break(); ctx->lock(); size_t placed_cells = 0; - // Initial constraints placer - for (auto &cell_entry : ctx->cells) { - CellInfo *cell = cell_entry.second.get(); - auto loc = cell->attrs.find(ctx->id("BEL")); - if (loc != cell->attrs.end()) { - std::string loc_name = loc->second; - BelId bel = ctx->getBelByName(ctx->id(loc_name)); - if (bel == BelId()) { - log_error("No Bel named \'%s\' located for " - "this chip (processing BEL attribute on \'%s\')\n", - loc_name.c_str(), cell->name.c_str(ctx)); - } + std::vector<CellInfo *> autoplaced; + std::vector<CellInfo *> chain_basis; + if (!refine) { + // Initial constraints placer + for (auto &cell_entry : ctx->cells) { + CellInfo *cell = cell_entry.second.get(); + auto loc = cell->attrs.find(ctx->id("BEL")); + if (loc != cell->attrs.end()) { + std::string loc_name = loc->second; + BelId bel = ctx->getBelByName(ctx->id(loc_name)); + if (bel == BelId()) { + log_error("No Bel named \'%s\' located for " + "this chip (processing BEL attribute on \'%s\')\n", + loc_name.c_str(), cell->name.c_str(ctx)); + } - IdString bel_type = ctx->getBelType(bel); - if (bel_type != cell->type) { - log_error("Bel \'%s\' of type \'%s\' does not match cell " - "\'%s\' of type \'%s\'\n", - loc_name.c_str(), bel_type.c_str(ctx), cell->name.c_str(ctx), cell->type.c_str(ctx)); - } - if (!ctx->isValidBelForCell(cell, bel)) { - log_error("Bel \'%s\' of type \'%s\' is not valid for cell " - "\'%s\' of type \'%s\'\n", - loc_name.c_str(), bel_type.c_str(ctx), cell->name.c_str(ctx), cell->type.c_str(ctx)); - } + IdString bel_type = ctx->getBelType(bel); + if (bel_type != cell->type) { + log_error("Bel \'%s\' of type \'%s\' does not match cell " + "\'%s\' of type \'%s\'\n", + loc_name.c_str(), bel_type.c_str(ctx), cell->name.c_str(ctx), cell->type.c_str(ctx)); + } + if (!ctx->isValidBelForCell(cell, bel)) { + log_error("Bel \'%s\' of type \'%s\' is not valid for cell " + "\'%s\' of type \'%s\'\n", + loc_name.c_str(), bel_type.c_str(ctx), cell->name.c_str(ctx), cell->type.c_str(ctx)); + } - auto bound_cell = ctx->getBoundBelCell(bel); - if (bound_cell) { - log_error("Cell \'%s\' cannot be bound to bel \'%s\' since it is already bound to cell \'%s\'\n", - cell->name.c_str(ctx), loc_name.c_str(), bound_cell->name.c_str(ctx)); - } + auto bound_cell = ctx->getBoundBelCell(bel); + if (bound_cell) { + log_error( + "Cell \'%s\' cannot be bound to bel \'%s\' since it is already bound to cell \'%s\'\n", + cell->name.c_str(ctx), loc_name.c_str(), bound_cell->name.c_str(ctx)); + } - ctx->bindBel(bel, cell, STRENGTH_USER); - locked_bels.insert(bel); - placed_cells++; + ctx->bindBel(bel, cell, STRENGTH_USER); + locked_bels.insert(bel); + placed_cells++; + } } - } - int constr_placed_cells = placed_cells; - log_info("Placed %d cells based on constraints.\n", int(placed_cells)); - ctx->yield(); + int constr_placed_cells = placed_cells; + log_info("Placed %d cells based on constraints.\n", int(placed_cells)); + ctx->yield(); - // Sort to-place cells for deterministic initial placement - std::vector<CellInfo *> autoplaced; - for (auto &cell : ctx->cells) { - CellInfo *ci = cell.second.get(); - if (ci->bel == BelId()) { - autoplaced.push_back(cell.second.get()); - } - } - std::sort(autoplaced.begin(), autoplaced.end(), [](CellInfo *a, CellInfo *b) { return a->name < b->name; }); - ctx->shuffle(autoplaced); + // Sort to-place cells for deterministic initial placement - // Place cells randomly initially - log_info("Creating initial placement for remaining %d cells.\n", int(autoplaced.size())); + for (auto &cell : ctx->cells) { + CellInfo *ci = cell.second.get(); + if (ci->bel == BelId()) { + autoplaced.push_back(cell.second.get()); + } + } + std::sort(autoplaced.begin(), autoplaced.end(), [](CellInfo *a, CellInfo *b) { return a->name < b->name; }); + ctx->shuffle(autoplaced); + auto iplace_start = std::chrono::high_resolution_clock::now(); + // Place cells randomly initially + log_info("Creating initial placement for remaining %d cells.\n", int(autoplaced.size())); - for (auto cell : autoplaced) { - place_initial(cell); - placed_cells++; - if ((placed_cells - constr_placed_cells) % 500 == 0) + for (auto cell : autoplaced) { + place_initial(cell); + placed_cells++; + if ((placed_cells - constr_placed_cells) % 500 == 0) + log_info(" initial placement placed %d/%d cells\n", int(placed_cells - constr_placed_cells), + int(autoplaced.size())); + } + if ((placed_cells - constr_placed_cells) % 500 != 0) log_info(" initial placement placed %d/%d cells\n", int(placed_cells - constr_placed_cells), int(autoplaced.size())); + if (cfg.budgetBased && ctx->slack_redist_iter > 0) + assign_budget(ctx); + ctx->yield(); + auto iplace_end = std::chrono::high_resolution_clock::now(); + log_info("Initial placement time %.02fs\n", + std::chrono::duration<float>(iplace_end - iplace_start).count()); + log_info("Running simulated annealing placer.\n"); + } else { + for (auto &cell : ctx->cells) { + CellInfo *ci = cell.second.get(); + if (ci->belStrength > STRENGTH_STRONG) + continue; + else if (ci->constr_parent != nullptr) + continue; + else if (!ci->constr_children.empty() || ci->constr_z != ci->UNCONSTR) + chain_basis.push_back(ci); + else + autoplaced.push_back(ci); + } + require_legal = false; + diameter = 3; + log_info("Running simulated annealing placer for refinement.\n"); } - if ((placed_cells - constr_placed_cells) % 500 != 0) - log_info(" initial placement placed %d/%d cells\n", int(placed_cells - constr_placed_cells), - int(autoplaced.size())); - if (ctx->slack_redist_iter > 0) - assign_budget(ctx); - ctx->yield(); + auto saplace_start = std::chrono::high_resolution_clock::now(); - log_info("Running simulated annealing placer.\n"); + // Invoke timing analysis to obtain criticalities + if (!cfg.budgetBased) + get_criticalities(ctx, &net_crit); - // Calculate metric after initial placement - curr_metric = 0; - curr_tns = 0; - for (auto &net : ctx->nets) { - wirelen_t wl = get_net_metric(ctx, net.second.get(), MetricType::COST, curr_tns); - costs[net.second->udata] = CostChange{wl, -1}; - curr_metric += wl; - } + // Calculate costs after initial placement + setup_costs(); + moveChange.init(this); + curr_wirelen_cost = total_wirelen_cost(); + curr_timing_cost = total_timing_cost(); + last_wirelen_cost = curr_wirelen_cost; + last_timing_cost = curr_timing_cost; + + wirelen_t avg_wirelen = curr_wirelen_cost; + wirelen_t min_wirelen = curr_wirelen_cost; int n_no_progress = 0; - wirelen_t min_metric = curr_metric; - double avg_metric = curr_metric; - temp = 10000; + temp = refine ? 1e-7 : cfg.startTemp; // Main simulated annealing loop for (int iter = 1;; iter++) { @@ -188,9 +268,9 @@ class SAPlacer improved = false; if (iter % 5 == 0 || iter == 1) - log_info(" at iteration #%d: temp = %f, cost = " - "%.0f, est tns = %.02fns\n", - iter, temp, double(curr_metric), curr_tns); + log_info(" at iteration #%d: temp = %f, timing cost = " + "%.0f, wirelen = %.0f\n", + iter, temp, double(curr_timing_cost), double(curr_wirelen_cost)); for (int m = 0; m < 15; ++m) { // Loop through all automatically placed cells @@ -202,10 +282,35 @@ class SAPlacer if (try_bel != BelId() && try_bel != cell->bel) try_swap_position(cell, try_bel); } + // Also try swapping chains, if applicable + for (auto cb : chain_basis) { + Loc chain_base_loc = ctx->getBelLocation(cb->bel); + BelId try_base = random_bel_for_cell(cb, chain_base_loc.z); + if (try_base != BelId() && try_base != cb->bel) + try_swap_chain(cb, try_base); + } + } + + if (ctx->debug) { + // Verify correctness of incremental wirelen updates + for (size_t i = 0; i < net_bounds.size(); i++) { + auto net = net_by_udata[i]; + if (ignore_net(net)) + continue; + auto &incr = net_bounds.at(i), gold = get_net_bounds(net); + NPNR_ASSERT(incr.x0 == gold.x0); + NPNR_ASSERT(incr.x1 == gold.x1); + NPNR_ASSERT(incr.y0 == gold.y0); + NPNR_ASSERT(incr.y1 == gold.y1); + NPNR_ASSERT(incr.nx0 == gold.nx0); + NPNR_ASSERT(incr.nx1 == gold.nx1); + NPNR_ASSERT(incr.ny0 == gold.ny0); + NPNR_ASSERT(incr.ny1 == gold.ny1); + } } - if (curr_metric < min_metric) { - min_metric = curr_metric; + if (curr_wirelen_cost < min_wirelen) { + min_wirelen = curr_wirelen_cost; improved = true; } @@ -215,9 +320,10 @@ class SAPlacer else n_no_progress++; - if (temp <= 1e-3 && n_no_progress >= 5) { - if (iter % 5 != 0) - log_info(" at iteration #%d: temp = %f, cost = %f\n", iter, temp, double(curr_metric)); + if (temp <= 1e-7 && n_no_progress >= (refine ? 1 : 5)) { + log_info(" at iteration #%d: temp = %f, timing cost = " + "%.0f, wirelen = %.0f \n", + iter, temp, double(curr_timing_cost), double(curr_wirelen_cost)); break; } @@ -225,64 +331,75 @@ class SAPlacer int M = std::max(max_x, max_y) + 1; - double upper = 0.6, lower = 0.4; + if (ctx->verbose) + log("iter #%d: temp = %f, timing cost = " + "%.0f, wirelen = %.0f, dia = %d, Ra = %.02f \n", + iter, temp, double(curr_timing_cost), double(curr_wirelen_cost), diameter, Raccept); - if (curr_metric < 0.95 * avg_metric) { - avg_metric = 0.8 * avg_metric + 0.2 * curr_metric; + if (curr_wirelen_cost < 0.95 * avg_wirelen && curr_wirelen_cost > 0) { + avg_wirelen = 0.8 * avg_wirelen + 0.2 * curr_wirelen_cost; } else { - if (Raccept >= 0.8) { - temp *= 0.7; - } else if (Raccept > upper) { - if (diameter < M) - diameter++; - else - temp *= 0.9; - } else if (Raccept > lower) { + double diam_next = diameter * (1.0 - 0.44 + Raccept); + diameter = std::max<int>(1, std::min<int>(M, int(diam_next + 0.5))); + if (Raccept > 0.96) { + temp *= 0.5; + } else if (Raccept > 0.8) { + temp *= 0.9; + } else if (Raccept > 0.15 && diameter > 1) { temp *= 0.95; } else { - // Raccept < 0.3 - if (diameter > 1) - diameter--; - else - temp *= 0.8; + temp *= 0.8; } } // Once cooled below legalise threshold, run legalisation and start requiring // legal moves only - if (temp < legalise_temp && require_legal) { + if (diameter < legalise_dia && require_legal) { if (legalise_relative_constraints(ctx)) { // Only increase temperature if something was moved autoplaced.clear(); + chain_basis.clear(); for (auto cell : sorted(ctx->cells)) { - if (cell.second->belStrength < STRENGTH_STRONG) + if (cell.second->belStrength <= STRENGTH_STRONG && cell.second->constr_parent == nullptr && + !cell.second->constr_children.empty()) + chain_basis.push_back(cell.second); + else if (cell.second->belStrength < STRENGTH_STRONG) autoplaced.push_back(cell.second); } - temp = post_legalise_temp; - diameter *= post_legalise_dia_scale; + // temp = post_legalise_temp; + // diameter = std::min<int>(M, diameter * post_legalise_dia_scale); ctx->shuffle(autoplaced); // Legalisation is a big change so force a slack redistribution here - if (ctx->slack_redist_iter > 0) + if (ctx->slack_redist_iter > 0 && cfg.budgetBased) assign_budget(ctx, true /* quiet */); } require_legal = false; - } else if (ctx->slack_redist_iter > 0 && iter % ctx->slack_redist_iter == 0) { + } else if (cfg.budgetBased && ctx->slack_redist_iter > 0 && iter % ctx->slack_redist_iter == 0) { assign_budget(ctx, true /* quiet */); } + // Invoke timing analysis to obtain criticalities + if (!cfg.budgetBased && ctx->timing_driven) + get_criticalities(ctx, &net_crit); + // Need to rebuild costs after criticalities change + setup_costs(); + // Reset incremental bounds + moveChange.reset(this); + moveChange.new_net_bounds = net_bounds; + // Recalculate total metric entirely to avoid rounding errors // accumulating over time - curr_metric = 0; - curr_tns = 0; - for (auto &net : ctx->nets) { - wirelen_t wl = get_net_metric(ctx, net.second.get(), MetricType::COST, curr_tns); - costs[net.second->udata] = CostChange{wl, -1}; - curr_metric += wl; - } - + curr_wirelen_cost = total_wirelen_cost(); + curr_timing_cost = total_timing_cost(); + last_wirelen_cost = curr_wirelen_cost; + last_timing_cost = curr_timing_cost; // Let the UI show visualization updates. ctx->yield(); } + + auto saplace_end = std::chrono::high_resolution_clock::now(); + log_info("SA placement time %.02fs\n", std::chrono::duration<float>(saplace_end - saplace_start).count()); + // Final post-pacement validitiy check ctx->yield(); for (auto bel : ctx->getBels()) { @@ -327,7 +444,8 @@ class SAPlacer ctx->unbindBel(cell->bel); } IdString targetType = cell->type; - for (auto bel : ctx->getBels()) { + + auto proc_bel = [&](BelId bel) { if (ctx->getBelType(bel) == targetType && ctx->isValidBelForCell(cell, bel)) { if (ctx->checkBelAvail(bel)) { uint64_t score = ctx->rng64(); @@ -345,7 +463,18 @@ class SAPlacer } } } + }; + + if (cell->region != nullptr && cell->region->constr_bels) { + for (auto bel : cell->region->bels) { + proc_bel(bel); + } + } else { + for (auto bel : ctx->getBels()) { + proc_bel(bel); + } } + if (best_bel == BelId()) { if (iters == 0 || ripup_bel == BelId()) log_error("failed to place cell '%s' of type '%s'\n", cell->name.c_str(ctx), cell->type.c_str(ctx)); @@ -366,49 +495,38 @@ class SAPlacer // Attempt a SA position swap, return true on success or false on failure bool try_swap_position(CellInfo *cell, BelId newBel) { - static std::vector<NetInfo *> updates; - updates.clear(); + static const double epsilon = 1e-20; + moveChange.reset(this); + if (!require_legal && is_constrained(cell)) + return false; BelId oldBel = cell->bel; CellInfo *other_cell = ctx->getBoundBelCell(newBel); - if (other_cell != nullptr && other_cell->belStrength > STRENGTH_WEAK) { + if (!require_legal && other_cell != nullptr && + (is_constrained(other_cell) || other_cell->belStrength > STRENGTH_WEAK)) { return false; } int old_dist = get_constraints_distance(ctx, cell); int new_dist; if (other_cell != nullptr) old_dist += get_constraints_distance(ctx, other_cell); - wirelen_t new_metric = 0, delta; + double delta = 0; ctx->unbindBel(oldBel); if (other_cell != nullptr) { ctx->unbindBel(newBel); } - for (const auto &port : cell->ports) { - if (port.second.net != nullptr) { - auto &cost = costs[port.second.net->udata]; - if (cost.new_cost == 0) - continue; - cost.new_cost = 0; - updates.emplace_back(port.second.net); - } - } + ctx->bindBel(newBel, cell, STRENGTH_WEAK); if (other_cell != nullptr) { - for (const auto &port : other_cell->ports) - if (port.second.net != nullptr) { - auto &cost = costs[port.second.net->udata]; - if (cost.new_cost == 0) - continue; - cost.new_cost = 0; - updates.emplace_back(port.second.net); - } + ctx->bindBel(oldBel, other_cell, STRENGTH_WEAK); } - ctx->bindBel(newBel, cell, STRENGTH_WEAK); + add_move_cell(moveChange, cell, oldBel); if (other_cell != nullptr) { - ctx->bindBel(oldBel, other_cell, STRENGTH_WEAK); + add_move_cell(moveChange, other_cell, newBel); } + if (!ctx->isBelLocationValid(newBel) || ((other_cell != nullptr && !ctx->isBelLocationValid(oldBel)))) { ctx->unbindBel(newBel); if (other_cell != nullptr) @@ -416,26 +534,18 @@ class SAPlacer goto swap_fail; } - new_metric = curr_metric; - // Recalculate metrics for all nets touched by the peturbation - for (const auto &net : updates) { - auto &c = costs[net->udata]; - new_metric -= c.curr_cost; - float temp_tns = 0; - wirelen_t net_new_wl = get_net_metric(ctx, net, MetricType::COST, temp_tns); - new_metric += net_new_wl; - c.new_cost = net_new_wl; - } + compute_cost_changes(moveChange); new_dist = get_constraints_distance(ctx, cell); if (other_cell != nullptr) new_dist += get_constraints_distance(ctx, other_cell); - delta = new_metric - curr_metric; - delta += (cfg.constraintWeight / temp) * (new_dist - old_dist); + delta = lambda * (moveChange.timing_delta / std::max<double>(last_timing_cost, epsilon)) + + (1 - lambda) * (double(moveChange.wirelen_delta) / std::max<double>(last_wirelen_cost, epsilon)); + delta += (cfg.constraintWeight / temp) * (new_dist - old_dist) / last_wirelen_cost; n_move++; // SA acceptance criterea - if (delta < 0 || (temp > 1e-6 && (ctx->rng() / float(0x3fffffff)) <= std::exp(-delta / temp))) { + if (delta < 0 || (temp > 1e-8 && (ctx->rng() / float(0x3fffffff)) <= std::exp(-delta / temp))) { n_accept++; } else { if (other_cell != nullptr) @@ -443,32 +553,149 @@ class SAPlacer ctx->unbindBel(newBel); goto swap_fail; } - curr_metric = new_metric; - for (const auto &net : updates) { - auto &c = costs[net->udata]; - c = CostChange{c.new_cost, -1}; - } - + commit_cost_changes(moveChange); +#if 0 + log_info("swap %s -> %s\n", cell->name.c_str(ctx), ctx->getBelName(newBel).c_str(ctx)); + if (other_cell != nullptr) + log_info("swap %s -> %s\n", other_cell->name.c_str(ctx), ctx->getBelName(oldBel).c_str(ctx)); +#endif return true; swap_fail: ctx->bindBel(oldBel, cell, STRENGTH_WEAK); if (other_cell != nullptr) { ctx->bindBel(newBel, other_cell, STRENGTH_WEAK); } - for (const auto &net : updates) - costs[net->udata].new_cost = -1; + return false; + } + + inline bool is_constrained(CellInfo *cell) + { + return cell->constr_parent != nullptr || !cell->constr_children.empty(); + } + + // Swap the Bel of a cell with another, return the original location + BelId swap_cell_bels(CellInfo *cell, BelId newBel) + { + BelId oldBel = cell->bel; +#if 0 + log_info("%s old: %s new: %s\n", cell->name.c_str(ctx), ctx->getBelName(cell->bel).c_str(ctx), ctx->getBelName(newBel).c_str(ctx)); +#endif + CellInfo *bound = ctx->getBoundBelCell(newBel); + if (bound != nullptr) + ctx->unbindBel(newBel); + ctx->unbindBel(oldBel); + ctx->bindBel(newBel, cell, is_constrained(cell) ? STRENGTH_STRONG : STRENGTH_WEAK); + if (bound != nullptr) + ctx->bindBel(oldBel, bound, is_constrained(bound) ? STRENGTH_STRONG : STRENGTH_WEAK); + return oldBel; + } + + // Discover the relative positions of all cells in a chain + void discover_chain(Loc baseLoc, CellInfo *cell, std::vector<std::pair<CellInfo *, Loc>> &cell_rel) + { + Loc cellLoc = ctx->getBelLocation(cell->bel); + Loc rel{cellLoc.x - baseLoc.x, cellLoc.y - baseLoc.y, cellLoc.z}; + cell_rel.emplace_back(std::make_pair(cell, rel)); + for (auto child : cell->constr_children) + discover_chain(baseLoc, child, cell_rel); + } + + // Attempt to swap a chain with a non-chain + bool try_swap_chain(CellInfo *cell, BelId newBase) + { + std::vector<std::pair<CellInfo *, Loc>> cell_rel; + std::unordered_set<IdString> cells; + std::vector<std::pair<CellInfo *, BelId>> moves_made; + std::vector<std::pair<CellInfo *, BelId>> dest_bels; + double delta = 0; + moveChange.reset(this); + if (ctx->debug) + log_info("finding cells for chain swap %s\n", cell->name.c_str(ctx)); + + Loc baseLoc = ctx->getBelLocation(cell->bel); + discover_chain(baseLoc, cell, cell_rel); + Loc newBaseLoc = ctx->getBelLocation(newBase); + NPNR_ASSERT(newBaseLoc.z == baseLoc.z); + for (const auto &cr : cell_rel) + cells.insert(cr.first->name); + + for (const auto &cr : cell_rel) { + Loc targetLoc = {newBaseLoc.x + cr.second.x, newBaseLoc.y + cr.second.y, cr.second.z}; + BelId targetBel = ctx->getBelByLocation(targetLoc); + if (targetBel == BelId()) + return false; + if (ctx->getBelType(targetBel) != cell->type) + return false; + CellInfo *bound = ctx->getBoundBelCell(targetBel); + // We don't consider swapping chains with other chains, at least for the time being - unless it is + // part of this chain + if (bound != nullptr && !cells.count(bound->name) && + (bound->belStrength >= STRENGTH_STRONG || is_constrained(bound))) + return false; + dest_bels.emplace_back(std::make_pair(cr.first, targetBel)); + } + if (ctx->debug) + log_info("trying chain swap %s\n", cell->name.c_str(ctx)); + // <cell, oldBel> + for (const auto &db : dest_bels) { + BelId oldBel = swap_cell_bels(db.first, db.second); + moves_made.emplace_back(std::make_pair(db.first, oldBel)); + CellInfo *bound = ctx->getBoundBelCell(oldBel); + add_move_cell(moveChange, db.first, oldBel); + if (bound != nullptr) + add_move_cell(moveChange, bound, db.second); + } + for (const auto &mm : moves_made) { + if (!ctx->isBelLocationValid(mm.first->bel) || !check_cell_bel_region(mm.first, mm.first->bel)) + goto swap_fail; + if (!ctx->isBelLocationValid(mm.second)) + goto swap_fail; + CellInfo *bound = ctx->getBoundBelCell(mm.second); + if (bound && !check_cell_bel_region(bound, bound->bel)) + goto swap_fail; + } + compute_cost_changes(moveChange); + delta = lambda * (moveChange.timing_delta / last_timing_cost) + + (1 - lambda) * (double(moveChange.wirelen_delta) / last_wirelen_cost); + n_move++; + // SA acceptance criterea + if (delta < 0 || (temp > 1e-9 && (ctx->rng() / float(0x3fffffff)) <= std::exp(-delta / temp))) { + n_accept++; + if (ctx->debug) + log_info("accepted chain swap %s\n", cell->name.c_str(ctx)); + } else { + goto swap_fail; + } + commit_cost_changes(moveChange); + return true; + swap_fail: + for (const auto &entry : boost::adaptors::reverse(moves_made)) + swap_cell_bels(entry.first, entry.second); return false; } // Find a random Bel of the correct type for a cell, within the specified // diameter - BelId random_bel_for_cell(CellInfo *cell) + BelId random_bel_for_cell(CellInfo *cell, int force_z = -1) { IdString targetType = cell->type; Loc curr_loc = ctx->getBelLocation(cell->bel); + int count = 0; + + int dx = diameter, dy = diameter; + if (cell->region != nullptr && cell->region->constr_bels) { + dx = std::min(diameter, (region_bounds[cell->region->name].x1 - region_bounds[cell->region->name].x0) + 1); + dy = std::min(diameter, (region_bounds[cell->region->name].y1 - region_bounds[cell->region->name].y0) + 1); + // Clamp location to within bounds + curr_loc.x = std::max(region_bounds[cell->region->name].x0, curr_loc.x); + curr_loc.x = std::min(region_bounds[cell->region->name].x1, curr_loc.x); + curr_loc.y = std::max(region_bounds[cell->region->name].y0, curr_loc.y); + curr_loc.y = std::min(region_bounds[cell->region->name].y1, curr_loc.y); + } + while (true) { - int nx = ctx->rng(2 * diameter + 1) + std::max(curr_loc.x - diameter, 0); - int ny = ctx->rng(2 * diameter + 1) + std::max(curr_loc.y - diameter, 0); + int nx = ctx->rng(2 * dx + 1) + std::max(curr_loc.x - dx, 0); + int ny = ctx->rng(2 * dy + 1) + std::max(curr_loc.y - dy, 0); int beltype_idx, beltype_cnt; std::tie(beltype_idx, beltype_cnt) = bel_types.at(targetType); if (beltype_cnt < cfg.minBelsForGridPick) @@ -481,41 +708,436 @@ class SAPlacer if (fb.size() == 0) continue; BelId bel = fb.at(ctx->rng(int(fb.size()))); + if (force_z != -1) { + Loc loc = ctx->getBelLocation(bel); + if (loc.z != force_z) + continue; + } + if (!check_cell_bel_region(cell, bel)) + continue; if (locked_bels.find(bel) != locked_bels.end()) continue; + count++; return bel; } } + // Return true if a net is to be entirely ignored + inline bool ignore_net(NetInfo *net) + { + return net->driver.cell == nullptr || net->driver.cell->bel == BelId() || + ctx->getBelGlobalBuf(net->driver.cell->bel); + } + + // Get the bounding box for a net + inline BoundingBox get_net_bounds(NetInfo *net) + { + BoundingBox bb; + NPNR_ASSERT(net->driver.cell != nullptr); + Loc dloc = ctx->getBelLocation(net->driver.cell->bel); + bb.x0 = dloc.x; + bb.x1 = dloc.x; + bb.y0 = dloc.y; + bb.y1 = dloc.y; + bb.nx0 = 1; + bb.nx1 = 1; + bb.ny0 = 1; + bb.ny1 = 1; + for (auto user : net->users) { + if (user.cell->bel == BelId()) + continue; + Loc uloc = ctx->getBelLocation(user.cell->bel); + if (bb.x0 == uloc.x) + ++bb.nx0; + else if (uloc.x < bb.x0) { + bb.x0 = uloc.x; + bb.nx0 = 1; + } + if (bb.x1 == uloc.x) + ++bb.nx1; + else if (uloc.x > bb.x1) { + bb.x1 = uloc.x; + bb.nx1 = 1; + } + if (bb.y0 == uloc.y) + ++bb.ny0; + else if (uloc.y < bb.y0) { + bb.y0 = uloc.y; + bb.ny0 = 1; + } + if (bb.y1 == uloc.y) + ++bb.ny1; + else if (uloc.y > bb.y1) { + bb.y1 = uloc.y; + bb.ny1 = 1; + } + } + + return bb; + } + + // Get the timing cost for an arc of a net + inline double get_timing_cost(NetInfo *net, size_t user) + { + int cc; + if (net->driver.cell == nullptr) + return 0; + if (ctx->getPortTimingClass(net->driver.cell, net->driver.port, cc) == TMG_IGNORE) + return 0; + if (cfg.budgetBased) { + double delay = ctx->getDelayNS(ctx->predictDelay(net, net->users.at(user))); + return std::min(10.0, std::exp(delay - ctx->getDelayNS(net->users.at(user).budget) / 10)); + } else { + auto crit = net_crit.find(net->name); + if (crit == net_crit.end() || crit->second.criticality.empty()) + return 0; + double delay = ctx->getDelayNS(ctx->predictDelay(net, net->users.at(user))); + return delay * std::pow(crit->second.criticality.at(user), crit_exp); + } + } + + // Set up the cost maps + void setup_costs() + { + for (auto net : sorted(ctx->nets)) { + NetInfo *ni = net.second; + if (ignore_net(ni)) + continue; + net_bounds[ni->udata] = get_net_bounds(ni); + if (ctx->timing_driven && int(ni->users.size()) < cfg.timingFanoutThresh) + for (size_t i = 0; i < ni->users.size(); i++) + net_arc_tcost[ni->udata][i] = get_timing_cost(ni, i); + } + } + + // Get the total wiring cost for the design + wirelen_t total_wirelen_cost() + { + wirelen_t cost = 0; + for (const auto &net : net_bounds) + cost += net.hpwl(); + return cost; + } + + // Get the total timing cost for the design + double total_timing_cost() + { + double cost = 0; + for (const auto &net : net_arc_tcost) { + for (auto arc_cost : net) { + cost += arc_cost; + } + } + return cost; + } + + // Cost-change-related data for a move + struct MoveChangeData + { + + enum BoundChangeType + { + NO_CHANGE, + CELL_MOVED_INWARDS, + CELL_MOVED_OUTWARDS, + FULL_RECOMPUTE + }; + + std::vector<decltype(NetInfo::udata)> bounds_changed_nets_x, bounds_changed_nets_y; + std::vector<std::pair<decltype(NetInfo::udata), size_t>> changed_arcs; + + std::vector<BoundChangeType> already_bounds_changed_x, already_bounds_changed_y; + std::vector<std::vector<bool>> already_changed_arcs; + + std::vector<BoundingBox> new_net_bounds; + std::vector<std::pair<std::pair<decltype(NetInfo::udata), size_t>, double>> new_arc_costs; + + wirelen_t wirelen_delta = 0; + double timing_delta = 0; + + void init(SAPlacer *p) + { + already_bounds_changed_x.resize(p->ctx->nets.size()); + already_bounds_changed_y.resize(p->ctx->nets.size()); + already_changed_arcs.resize(p->ctx->nets.size()); + for (auto &net : p->ctx->nets) { + already_changed_arcs.at(net.second->udata).resize(net.second->users.size()); + } + new_net_bounds = p->net_bounds; + } + + void reset(SAPlacer *p) + { + for (auto bc : bounds_changed_nets_x) { + new_net_bounds[bc] = p->net_bounds[bc]; + already_bounds_changed_x[bc] = NO_CHANGE; + } + for (auto bc : bounds_changed_nets_y) { + new_net_bounds[bc] = p->net_bounds[bc]; + already_bounds_changed_y[bc] = NO_CHANGE; + } + for (const auto &tc : changed_arcs) + already_changed_arcs[tc.first][tc.second] = false; + bounds_changed_nets_x.clear(); + bounds_changed_nets_y.clear(); + changed_arcs.clear(); + new_arc_costs.clear(); + wirelen_delta = 0; + timing_delta = 0; + } + + } moveChange; + + void add_move_cell(MoveChangeData &mc, CellInfo *cell, BelId old_bel) + { + Loc curr_loc = ctx->getBelLocation(cell->bel); + Loc old_loc = ctx->getBelLocation(old_bel); + // Check net bounds + for (const auto &port : cell->ports) { + NetInfo *pn = port.second.net; + if (pn == nullptr) + continue; + if (ignore_net(pn)) + continue; + BoundingBox &curr_bounds = mc.new_net_bounds[pn->udata]; + // Incremental bounding box updates + // Note that everything other than full updates are applied immediately rather than being queued, + // so further updates to the same net in the same move are dealt with correctly. + // If a full update is already queued, this can be considered a no-op + if (mc.already_bounds_changed_x[pn->udata] != MoveChangeData::FULL_RECOMPUTE) { + // Bounds x0 + if (curr_loc.x < curr_bounds.x0) { + // Further out than current bounds x0 + curr_bounds.x0 = curr_loc.x; + curr_bounds.nx0 = 1; + if (mc.already_bounds_changed_x[pn->udata] == MoveChangeData::NO_CHANGE) { + // Checking already_bounds_changed_x ensures that each net is only added once + // to bounds_changed_nets, lest we add its HPWL change multiple times skewing the + // overall cost change + mc.already_bounds_changed_x[pn->udata] = MoveChangeData::CELL_MOVED_OUTWARDS; + mc.bounds_changed_nets_x.push_back(pn->udata); + } + } else if (curr_loc.x == curr_bounds.x0 && old_loc.x > curr_bounds.x0) { + curr_bounds.nx0++; + if (mc.already_bounds_changed_x[pn->udata] == MoveChangeData::NO_CHANGE) { + mc.already_bounds_changed_x[pn->udata] = MoveChangeData::CELL_MOVED_OUTWARDS; + mc.bounds_changed_nets_x.push_back(pn->udata); + } + } else if (old_loc.x == curr_bounds.x0 && curr_loc.x > curr_bounds.x0) { + if (mc.already_bounds_changed_x[pn->udata] == MoveChangeData::NO_CHANGE) + mc.bounds_changed_nets_x.push_back(pn->udata); + if (curr_bounds.nx0 == 1) { + mc.already_bounds_changed_x[pn->udata] = MoveChangeData::FULL_RECOMPUTE; + } else { + curr_bounds.nx0--; + if (mc.already_bounds_changed_x[pn->udata] == MoveChangeData::NO_CHANGE) + mc.already_bounds_changed_x[pn->udata] = MoveChangeData::CELL_MOVED_INWARDS; + } + } + + // Bounds x1 + if (curr_loc.x > curr_bounds.x1) { + // Further out than current bounds x1 + curr_bounds.x1 = curr_loc.x; + curr_bounds.nx1 = 1; + if (mc.already_bounds_changed_x[pn->udata] == MoveChangeData::NO_CHANGE) { + // Checking already_bounds_changed_x ensures that each net is only added once + // to bounds_changed_nets, lest we add its HPWL change multiple times skewing the + // overall cost change + mc.already_bounds_changed_x[pn->udata] = MoveChangeData::CELL_MOVED_OUTWARDS; + mc.bounds_changed_nets_x.push_back(pn->udata); + } + } else if (curr_loc.x == curr_bounds.x1 && old_loc.x < curr_bounds.x1) { + curr_bounds.nx1++; + if (mc.already_bounds_changed_x[pn->udata] == MoveChangeData::NO_CHANGE) { + mc.already_bounds_changed_x[pn->udata] = MoveChangeData::CELL_MOVED_OUTWARDS; + mc.bounds_changed_nets_x.push_back(pn->udata); + } + } else if (old_loc.x == curr_bounds.x1 && curr_loc.x < curr_bounds.x1) { + if (mc.already_bounds_changed_x[pn->udata] == MoveChangeData::NO_CHANGE) + mc.bounds_changed_nets_x.push_back(pn->udata); + if (curr_bounds.nx1 == 1) { + mc.already_bounds_changed_x[pn->udata] = MoveChangeData::FULL_RECOMPUTE; + } else { + curr_bounds.nx1--; + if (mc.already_bounds_changed_x[pn->udata] == MoveChangeData::NO_CHANGE) + mc.already_bounds_changed_x[pn->udata] = MoveChangeData::CELL_MOVED_INWARDS; + } + } + } + if (mc.already_bounds_changed_y[pn->udata] != MoveChangeData::FULL_RECOMPUTE) { + // Bounds y0 + if (curr_loc.y < curr_bounds.y0) { + // Further out than current bounds y0 + curr_bounds.y0 = curr_loc.y; + curr_bounds.ny0 = 1; + if (mc.already_bounds_changed_y[pn->udata] == MoveChangeData::NO_CHANGE) { + mc.already_bounds_changed_y[pn->udata] = MoveChangeData::CELL_MOVED_OUTWARDS; + mc.bounds_changed_nets_y.push_back(pn->udata); + } + } else if (curr_loc.y == curr_bounds.y0 && old_loc.y > curr_bounds.y0) { + curr_bounds.ny0++; + if (mc.already_bounds_changed_y[pn->udata] == MoveChangeData::NO_CHANGE) { + mc.already_bounds_changed_y[pn->udata] = MoveChangeData::CELL_MOVED_OUTWARDS; + mc.bounds_changed_nets_y.push_back(pn->udata); + } + } else if (old_loc.y == curr_bounds.y0 && curr_loc.y > curr_bounds.y0) { + if (mc.already_bounds_changed_y[pn->udata] == MoveChangeData::NO_CHANGE) + mc.bounds_changed_nets_y.push_back(pn->udata); + if (curr_bounds.ny0 == 1) { + mc.already_bounds_changed_y[pn->udata] = MoveChangeData::FULL_RECOMPUTE; + } else { + curr_bounds.ny0--; + if (mc.already_bounds_changed_y[pn->udata] == MoveChangeData::NO_CHANGE) + mc.already_bounds_changed_y[pn->udata] = MoveChangeData::CELL_MOVED_INWARDS; + } + } + + // Bounds y1 + if (curr_loc.y > curr_bounds.y1) { + // Further out than current bounds y1 + curr_bounds.y1 = curr_loc.y; + curr_bounds.ny1 = 1; + if (mc.already_bounds_changed_y[pn->udata] == MoveChangeData::NO_CHANGE) { + mc.already_bounds_changed_y[pn->udata] = MoveChangeData::CELL_MOVED_OUTWARDS; + mc.bounds_changed_nets_y.push_back(pn->udata); + } + } else if (curr_loc.y == curr_bounds.y1 && old_loc.y < curr_bounds.y1) { + curr_bounds.ny1++; + if (mc.already_bounds_changed_y[pn->udata] == MoveChangeData::NO_CHANGE) { + mc.already_bounds_changed_y[pn->udata] = MoveChangeData::CELL_MOVED_OUTWARDS; + mc.bounds_changed_nets_y.push_back(pn->udata); + } + } else if (old_loc.y == curr_bounds.y1 && curr_loc.y < curr_bounds.y1) { + if (mc.already_bounds_changed_y[pn->udata] == MoveChangeData::NO_CHANGE) + mc.bounds_changed_nets_y.push_back(pn->udata); + if (curr_bounds.ny1 == 1) { + mc.already_bounds_changed_y[pn->udata] = MoveChangeData::FULL_RECOMPUTE; + } else { + curr_bounds.ny1--; + if (mc.already_bounds_changed_y[pn->udata] == MoveChangeData::NO_CHANGE) + mc.already_bounds_changed_y[pn->udata] = MoveChangeData::CELL_MOVED_INWARDS; + } + } + } + + if (ctx->timing_driven && int(pn->users.size()) < cfg.timingFanoutThresh) { + // Output ports - all arcs change timing + if (port.second.type == PORT_OUT) { + int cc; + TimingPortClass cls = ctx->getPortTimingClass(cell, port.first, cc); + if (cls != TMG_IGNORE) + for (size_t i = 0; i < pn->users.size(); i++) + if (!mc.already_changed_arcs[pn->udata][i]) { + mc.changed_arcs.emplace_back(std::make_pair(pn->udata, i)); + mc.already_changed_arcs[pn->udata][i] = true; + } + } else if (port.second.type == PORT_IN) { + auto usr = fast_port_to_user.at(&port.second); + if (!mc.already_changed_arcs[pn->udata][usr]) { + mc.changed_arcs.emplace_back(std::make_pair(pn->udata, usr)); + mc.already_changed_arcs[pn->udata][usr] = true; + } + } + } + } + } + + void compute_cost_changes(MoveChangeData &md) + { + for (const auto &bc : md.bounds_changed_nets_x) { + if (md.already_bounds_changed_x[bc] == MoveChangeData::FULL_RECOMPUTE) + md.new_net_bounds[bc] = get_net_bounds(net_by_udata[bc]); + } + for (const auto &bc : md.bounds_changed_nets_y) { + if (md.already_bounds_changed_x[bc] != MoveChangeData::FULL_RECOMPUTE && + md.already_bounds_changed_y[bc] == MoveChangeData::FULL_RECOMPUTE) + md.new_net_bounds[bc] = get_net_bounds(net_by_udata[bc]); + } + + for (const auto &bc : md.bounds_changed_nets_x) + md.wirelen_delta += md.new_net_bounds[bc].hpwl() - net_bounds[bc].hpwl(); + for (const auto &bc : md.bounds_changed_nets_y) + if (md.already_bounds_changed_x[bc] == MoveChangeData::NO_CHANGE) + md.wirelen_delta += md.new_net_bounds[bc].hpwl() - net_bounds[bc].hpwl(); + + if (ctx->timing_driven) { + for (const auto &tc : md.changed_arcs) { + double old_cost = net_arc_tcost.at(tc.first).at(tc.second); + double new_cost = get_timing_cost(net_by_udata.at(tc.first), tc.second); + md.new_arc_costs.emplace_back(std::make_pair(tc, new_cost)); + md.timing_delta += (new_cost - old_cost); + md.already_changed_arcs[tc.first][tc.second] = false; + } + } + } + + void commit_cost_changes(MoveChangeData &md) + { + for (const auto &bc : md.bounds_changed_nets_x) + net_bounds[bc] = md.new_net_bounds[bc]; + for (const auto &bc : md.bounds_changed_nets_y) + net_bounds[bc] = md.new_net_bounds[bc]; + for (const auto &tc : md.new_arc_costs) + net_arc_tcost[tc.first.first].at(tc.first.second) = tc.second; + curr_wirelen_cost += md.wirelen_delta; + curr_timing_cost += md.timing_delta; + } + // Build the cell port -> user index + void build_port_index() + { + for (auto net : sorted(ctx->nets)) { + NetInfo *ni = net.second; + for (size_t i = 0; i < ni->users.size(); i++) { + auto &usr = ni->users.at(i); + fast_port_to_user[&(usr.cell->ports.at(usr.port))] = i; + } + } + } + + // Get the combined wirelen/timing metric + inline double curr_metric() { return lambda * curr_timing_cost + (1 - lambda) * curr_wirelen_cost; } + + // Map nets to their bounding box (so we can skip recompute for moves that do not exceed the bounds + std::vector<BoundingBox> net_bounds; + // Map net arcs to their timing cost (criticality * delay ns) + std::vector<std::vector<double>> net_arc_tcost; + + // Fast lookup for cell port to net user index + std::unordered_map<const PortInfo *, size_t> fast_port_to_user; + + // Wirelength and timing cost at last and current iteration + wirelen_t last_wirelen_cost, curr_wirelen_cost; + double last_timing_cost, curr_timing_cost; + + // Criticality data from timing analysis + NetCriticalityMap net_crit; + Context *ctx; - wirelen_t curr_metric = std::numeric_limits<wirelen_t>::max(); - float curr_tns = 0; - float temp = 1000; + float temp = 10; + float crit_exp = 8; + float lambda = 0.5; bool improved = false; int n_move, n_accept; int diameter = 35, max_x = 1, max_y = 1; std::unordered_map<IdString, std::tuple<int, int>> bel_types; + std::unordered_map<IdString, BoundingBox> region_bounds; std::vector<std::vector<std::vector<std::vector<BelId>>>> fast_bels; std::unordered_set<BelId> locked_bels; + std::vector<NetInfo *> net_by_udata; + std::vector<decltype(NetInfo::udata)> old_udata; bool require_legal = true; - const float legalise_temp = 1; - const float post_legalise_temp = 10; - const float post_legalise_dia_scale = 1.5; + const int legalise_dia = 4; Placer1Cfg cfg; - - struct CostChange - { - wirelen_t curr_cost; - wirelen_t new_cost; - }; - std::vector<CostChange> costs; - std::vector<decltype(NetInfo::udata)> old_udata; }; Placer1Cfg::Placer1Cfg(Context *ctx) : Settings(ctx) { constraintWeight = get<float>("placer1/constraintWeight", 10); minBelsForGridPick = get<int>("placer1/minBelsForGridPick", 64); + budgetBased = get<bool>("placer1/budgetBased", false); + startTemp = get<float>("placer1/startTemp", 1); + timingFanoutThresh = std::numeric_limits<int>::max(); } bool placer1(Context *ctx, Placer1Cfg cfg) @@ -538,4 +1160,24 @@ bool placer1(Context *ctx, Placer1Cfg cfg) } } +bool placer1_refine(Context *ctx, Placer1Cfg cfg) +{ + try { + SAPlacer placer(ctx, cfg); + placer.place(true); + log_info("Checksum: 0x%08x\n", ctx->checksum()); +#ifndef NDEBUG + ctx->lock(); + ctx->check(); + ctx->unlock(); +#endif + return true; + } catch (log_execution_error_exception) { +#ifndef NDEBUG + ctx->check(); +#endif + return false; + } +} + NEXTPNR_NAMESPACE_END diff --git a/common/placer1.h b/common/placer1.h index 7305f4b1..4c7c7339 100644 --- a/common/placer1.h +++ b/common/placer1.h @@ -29,9 +29,13 @@ struct Placer1Cfg : public Settings Placer1Cfg(Context *ctx); float constraintWeight; int minBelsForGridPick; + bool budgetBased; + float startTemp; + int timingFanoutThresh; }; extern bool placer1(Context *ctx, Placer1Cfg cfg); +extern bool placer1_refine(Context *ctx, Placer1Cfg cfg); NEXTPNR_NAMESPACE_END diff --git a/common/placer_heap.cc b/common/placer_heap.cc new file mode 100644 index 00000000..f9b639f8 --- /dev/null +++ b/common/placer_heap.cc @@ -0,0 +1,1545 @@ +/* + * nextpnr -- Next Generation Place and Route + * + * Copyright (C) 2019 David Shah <david@symbioticeda.com> + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + * [[cite]] HeAP + * Analytical Placement for Heterogeneous FPGAs, Marcel Gort and Jason H. Anderson + * https://janders.eecg.utoronto.ca/pdfs/marcelfpl12.pdf + * + * [[cite]] SimPL + * SimPL: An Effective Placement Algorithm, Myung-Chul Kim, Dong-Jin Lee and Igor L. Markov + * http://www.ece.umich.edu/cse/awards/pdfs/iccad10-simpl.pdf + * + * Notable changes from the original algorithm + * - Following the other nextpnr placer, Bels are placed rather than CLBs. This means a strict legalisation pass is + * added in addition to coarse legalisation (referred to as "spreading" to avoid confusion with strict legalisation) + * as described in HeAP to ensure validity. This searches random bels in the vicinity of the position chosen by + * spreading, with diameter increasing over iterations, with a heuristic to prefer lower wirelength choices. + * - To make the placer timing-driven, the bound2bound weights are multiplied by (1 + 10 * crit^2) + */ + +#ifdef WITH_HEAP + +#include "placer_heap.h" +#include <Eigen/Core> +#include <Eigen/IterativeLinearSolvers> +#include <boost/optional.hpp> +#include <chrono> +#include <deque> +#include <fstream> +#include <numeric> +#include <queue> +#include <thread> +#include <tuple> +#include <unordered_map> +#include "log.h" +#include "nextpnr.h" +#include "place_common.h" +#include "placer1.h" +#include "timing.h" +#include "util.h" +NEXTPNR_NAMESPACE_BEGIN + +namespace { +// A simple internal representation for a sparse system of equations Ax = rhs +// This is designed to decouple the functions that build the matrix to the engine that +// solves it, and the representation that requires +template <typename T> struct EquationSystem +{ + + EquationSystem(size_t rows, size_t cols) + { + A.resize(cols); + rhs.resize(rows); + } + + // Simple sparse format, easy to convert to CCS for solver + std::vector<std::vector<std::pair<int, T>>> A; // col -> (row, x[row, col]) sorted by row + std::vector<T> rhs; // RHS vector + void reset() + { + for (auto &col : A) + col.clear(); + std::fill(rhs.begin(), rhs.end(), T()); + } + + void add_coeff(int row, int col, T val) + { + auto &Ac = A.at(col); + // Binary search + int b = 0, e = int(Ac.size()) - 1; + while (b <= e) { + int i = (b + e) / 2; + if (Ac.at(i).first == row) { + Ac.at(i).second += val; + return; + } + if (Ac.at(i).first > row) + e = i - 1; + else + b = i + 1; + } + Ac.insert(Ac.begin() + b, std::make_pair(row, val)); + } + + void add_rhs(int row, T val) { rhs[row] += val; } + + void solve(std::vector<T> &x) + { + using namespace Eigen; + if (x.empty()) + return; + NPNR_ASSERT(x.size() == A.size()); + + VectorXd vx(x.size()), vb(rhs.size()); + SparseMatrix<T> mat(A.size(), A.size()); + + std::vector<int> colnnz; + for (auto &Ac : A) + colnnz.push_back(int(Ac.size())); + mat.reserve(colnnz); + for (int col = 0; col < int(A.size()); col++) { + auto &Ac = A.at(col); + for (auto &el : Ac) + mat.insert(el.first, col) = el.second; + } + + for (int i = 0; i < int(x.size()); i++) + vx[i] = x.at(i); + for (int i = 0; i < int(rhs.size()); i++) + vb[i] = rhs.at(i); + + ConjugateGradient<SparseMatrix<T>, Lower | Upper> solver; + solver.setTolerance(1e-5); + VectorXd xr = solver.compute(mat).solveWithGuess(vb, vx); + for (int i = 0; i < int(x.size()); i++) + x.at(i) = xr[i]; + // for (int i = 0; i < int(x.size()); i++) + // log_info("x[%d] = %f\n", i, x.at(i)); + } +}; + +} // namespace + +class HeAPPlacer +{ + public: + HeAPPlacer(Context *ctx, PlacerHeapCfg cfg) : ctx(ctx), cfg(cfg) { Eigen::initParallel(); } + + bool place() + { + auto startt = std::chrono::high_resolution_clock::now(); + + ctx->lock(); + place_constraints(); + build_fast_bels(); + seed_placement(); + update_all_chains(); + wirelen_t hpwl = total_hpwl(); + log_info("Creating initial analytic placement for %d cells, random placement wirelen = %d.\n", + int(place_cells.size()), int(hpwl)); + for (int i = 0; i < 4; i++) { + setup_solve_cells(); + auto solve_startt = std::chrono::high_resolution_clock::now(); + std::thread xaxis([&]() { build_solve_direction(false, -1); }); + build_solve_direction(true, -1); + xaxis.join(); + auto solve_endt = std::chrono::high_resolution_clock::now(); + solve_time += std::chrono::duration<double>(solve_endt - solve_startt).count(); + + update_all_chains(); + + hpwl = total_hpwl(); + log_info(" at initial placer iter %d, wirelen = %d\n", i, int(hpwl)); + } + + wirelen_t solved_hpwl = 0, spread_hpwl = 0, legal_hpwl = 0, best_hpwl = std::numeric_limits<wirelen_t>::max(); + int iter = 0, stalled = 0; + + std::vector<std::tuple<CellInfo *, BelId, PlaceStrength>> solution; + + std::vector<std::unordered_set<IdString>> heap_runs; + std::unordered_set<IdString> all_celltypes; + std::unordered_map<IdString, int> ct_count; + + for (auto cell : place_cells) { + if (!all_celltypes.count(cell->type)) { + heap_runs.push_back(std::unordered_set<IdString>{cell->type}); + all_celltypes.insert(cell->type); + } + ct_count[cell->type]++; + } + // If more than 98% of cells are one cell type, always solve all at once + // Otherwise, follow full HeAP strategy of rotate&all + for (auto &c : ct_count) + if (c.second >= 0.98 * int(place_cells.size())) { + heap_runs.clear(); + break; + } + + heap_runs.push_back(all_celltypes); + // The main HeAP placer loop + log_info("Running main analytical placer.\n"); + while (stalled < 5 && (solved_hpwl <= legal_hpwl * 0.8)) { + // Alternate between particular Bel types and all bels + for (auto &run : heap_runs) { + auto run_startt = std::chrono::high_resolution_clock::now(); + + setup_solve_cells(&run); + if (solve_cells.empty()) + continue; + // Heuristic: don't bother with threading below a certain size + auto solve_startt = std::chrono::high_resolution_clock::now(); + + if (solve_cells.size() < 500) { + build_solve_direction(false, (iter == 0) ? -1 : iter); + build_solve_direction(true, (iter == 0) ? -1 : iter); + } else { + std::thread xaxis([&]() { build_solve_direction(false, (iter == 0) ? -1 : iter); }); + build_solve_direction(true, (iter == 0) ? -1 : iter); + xaxis.join(); + } + auto solve_endt = std::chrono::high_resolution_clock::now(); + solve_time += std::chrono::duration<double>(solve_endt - solve_startt).count(); + update_all_chains(); + solved_hpwl = total_hpwl(); + + update_all_chains(); + for (auto type : sorted(run)) + CutSpreader(this, type).run(); + + update_all_chains(); + spread_hpwl = total_hpwl(); + legalise_placement_strict(true); + update_all_chains(); + + legal_hpwl = total_hpwl(); + auto run_stopt = std::chrono::high_resolution_clock::now(); + log_info(" at iteration #%d, type %s: wirelen solved = %d, spread = %d, legal = %d; time = %.02fs\n", + iter + 1, (run.size() > 1 ? "ALL" : run.begin()->c_str(ctx)), int(solved_hpwl), + int(spread_hpwl), int(legal_hpwl), + std::chrono::duration<double>(run_stopt - run_startt).count()); + } + + if (ctx->timing_driven) + get_criticalities(ctx, &net_crit); + + if (legal_hpwl < best_hpwl) { + best_hpwl = legal_hpwl; + stalled = 0; + // Save solution + solution.clear(); + for (auto cell : sorted(ctx->cells)) { + solution.emplace_back(cell.second, cell.second->bel, cell.second->belStrength); + } + } else { + ++stalled; + } + for (auto &cl : cell_locs) { + cl.second.legal_x = cl.second.x; + cl.second.legal_y = cl.second.y; + } + ctx->yield(); + ++iter; + } + + // Apply saved solution + for (auto &sc : solution) { + CellInfo *cell = std::get<0>(sc); + if (cell->bel != BelId()) + ctx->unbindBel(cell->bel); + } + for (auto &sc : solution) { + CellInfo *cell; + BelId bel; + PlaceStrength strength; + std::tie(cell, bel, strength) = sc; + ctx->bindBel(bel, cell, strength); + } + + for (auto cell : sorted(ctx->cells)) { + if (cell.second->bel == BelId()) + log_error("Found unbound cell %s\n", cell.first.c_str(ctx)); + if (ctx->getBoundBelCell(cell.second->bel) != cell.second) + log_error("Found cell %s with mismatched binding\n", cell.first.c_str(ctx)); + if (ctx->debug) + log_info("AP soln: %s -> %s\n", cell.first.c_str(ctx), ctx->getBelName(cell.second->bel).c_str(ctx)); + } + + ctx->unlock(); + auto endtt = std::chrono::high_resolution_clock::now(); + log_info("HeAP Placer Time: %.02fs\n", std::chrono::duration<double>(endtt - startt).count()); + log_info(" of which solving equations: %.02fs\n", solve_time); + log_info(" of which spreading cells: %.02fs\n", cl_time); + log_info(" of which strict legalisation: %.02fs\n", sl_time); + + ctx->check(); + + placer1_refine(ctx, Placer1Cfg(ctx)); + + return true; + } + + private: + Context *ctx; + PlacerHeapCfg cfg; + + int max_x = 0, max_y = 0; + std::vector<std::vector<std::vector<std::vector<BelId>>>> fast_bels; + std::unordered_map<IdString, std::tuple<int, int>> bel_types; + + // For fast handling of heterogeneosity during initial placement without full legalisation, + // for each Bel type this goes from x or y to the nearest x or y where a Bel of a given type exists + // This is particularly important for the iCE40 architecture, where multipliers and BRAM only exist at the + // edges and corners respectively + std::vector<std::vector<int>> nearest_row_with_bel; + std::vector<std::vector<int>> nearest_col_with_bel; + + // In some cases, we can't use bindBel because we allow overlap in the earlier stages. So we use this custom + // structure instead + struct CellLocation + { + int x, y; + int legal_x, legal_y; + double rawx, rawy; + bool locked, global; + }; + std::unordered_map<IdString, CellLocation> cell_locs; + // The set of cells that we will actually place. This excludes locked cells and children cells of macros/chains + // (only the root of each macro is placed.) + std::vector<CellInfo *> place_cells; + + // The cells in the current equation being solved (a subset of place_cells in some cases, where we only place + // cells of a certain type) + std::vector<CellInfo *> solve_cells; + + // For cells in a chain, this is the ultimate root cell of the chain (sometimes this is not constr_parent + // where chains are within chains + std::unordered_map<IdString, CellInfo *> chain_root; + std::unordered_map<IdString, int> chain_size; + + // The offset from chain_root to a cell in the chain + std::unordered_map<IdString, std::pair<int, int>> cell_offsets; + + // Performance counting + double solve_time = 0, cl_time = 0, sl_time = 0; + + NetCriticalityMap net_crit; + + // Place cells with the BEL attribute set to constrain them + void place_constraints() + { + size_t placed_cells = 0; + // Initial constraints placer + for (auto &cell_entry : ctx->cells) { + CellInfo *cell = cell_entry.second.get(); + auto loc = cell->attrs.find(ctx->id("BEL")); + if (loc != cell->attrs.end()) { + std::string loc_name = loc->second; + BelId bel = ctx->getBelByName(ctx->id(loc_name)); + if (bel == BelId()) { + log_error("No Bel named \'%s\' located for " + "this chip (processing BEL attribute on \'%s\')\n", + loc_name.c_str(), cell->name.c_str(ctx)); + } + + IdString bel_type = ctx->getBelType(bel); + if (bel_type != cell->type) { + log_error("Bel \'%s\' of type \'%s\' does not match cell " + "\'%s\' of type \'%s\'\n", + loc_name.c_str(), bel_type.c_str(ctx), cell->name.c_str(ctx), cell->type.c_str(ctx)); + } + if (!ctx->isValidBelForCell(cell, bel)) { + log_error("Bel \'%s\' of type \'%s\' is not valid for cell " + "\'%s\' of type \'%s\'\n", + loc_name.c_str(), bel_type.c_str(ctx), cell->name.c_str(ctx), cell->type.c_str(ctx)); + } + + auto bound_cell = ctx->getBoundBelCell(bel); + if (bound_cell) { + log_error("Cell \'%s\' cannot be bound to bel \'%s\' since it is already bound to cell \'%s\'\n", + cell->name.c_str(ctx), loc_name.c_str(), bound_cell->name.c_str(ctx)); + } + + ctx->bindBel(bel, cell, STRENGTH_USER); + placed_cells++; + } + } + log_info("Placed %d cells based on constraints.\n", int(placed_cells)); + ctx->yield(); + } + + // Construct the fast_bels, nearest_row_with_bel and nearest_col_with_bel + void build_fast_bels() + { + + int num_bel_types = 0; + for (auto bel : ctx->getBels()) { + IdString type = ctx->getBelType(bel); + if (bel_types.find(type) == bel_types.end()) { + bel_types[type] = std::tuple<int, int>(num_bel_types++, 1); + } else { + std::get<1>(bel_types.at(type))++; + } + } + for (auto bel : ctx->getBels()) { + if (!ctx->checkBelAvail(bel)) + continue; + Loc loc = ctx->getBelLocation(bel); + IdString type = ctx->getBelType(bel); + int type_idx = std::get<0>(bel_types.at(type)); + if (int(fast_bels.size()) < type_idx + 1) + fast_bels.resize(type_idx + 1); + if (int(fast_bels.at(type_idx).size()) < (loc.x + 1)) + fast_bels.at(type_idx).resize(loc.x + 1); + if (int(fast_bels.at(type_idx).at(loc.x).size()) < (loc.y + 1)) + fast_bels.at(type_idx).at(loc.x).resize(loc.y + 1); + max_x = std::max(max_x, loc.x); + max_y = std::max(max_y, loc.y); + fast_bels.at(type_idx).at(loc.x).at(loc.y).push_back(bel); + } + + nearest_row_with_bel.resize(num_bel_types, std::vector<int>(max_y + 1, -1)); + nearest_col_with_bel.resize(num_bel_types, std::vector<int>(max_x + 1, -1)); + for (auto bel : ctx->getBels()) { + if (!ctx->checkBelAvail(bel)) + continue; + Loc loc = ctx->getBelLocation(bel); + int type_idx = std::get<0>(bel_types.at(ctx->getBelType(bel))); + auto &nr = nearest_row_with_bel.at(type_idx), &nc = nearest_col_with_bel.at(type_idx); + // Traverse outwards through nearest_row_with_bel and nearest_col_with_bel, stopping once + // another row/col is already recorded as being nearer + for (int x = loc.x; x <= max_x; x++) { + if (nc.at(x) != -1 && std::abs(loc.x - nc.at(x)) <= (x - loc.x)) + break; + nc.at(x) = loc.x; + } + for (int x = loc.x - 1; x >= 0; x--) { + if (nc.at(x) != -1 && std::abs(loc.x - nc.at(x)) <= (loc.x - x)) + break; + nc.at(x) = loc.x; + } + for (int y = loc.y; y <= max_y; y++) { + if (nr.at(y) != -1 && std::abs(loc.y - nr.at(y)) <= (y - loc.y)) + break; + nr.at(y) = loc.y; + } + for (int y = loc.y - 1; y >= 0; y--) { + if (nr.at(y) != -1 && std::abs(loc.y - nr.at(y)) <= (loc.y - y)) + break; + nr.at(y) = loc.y; + } + } + } + + // Build and solve in one direction + void build_solve_direction(bool yaxis, int iter) + { + for (int i = 0; i < 5; i++) { + EquationSystem<double> esx(solve_cells.size(), solve_cells.size()); + build_equations(esx, yaxis, iter); + solve_equations(esx, yaxis); + } + } + + // Check if a cell has any meaningful connectivity + bool has_connectivity(CellInfo *cell) + { + for (auto port : cell->ports) { + if (port.second.net != nullptr && port.second.net->driver.cell != nullptr && + !port.second.net->users.empty()) + return true; + } + return false; + } + + // Build up a random initial placement, without regard to legality + // FIXME: Are there better approaches to the initial placement (e.g. greedy?) + void seed_placement() + { + std::unordered_map<IdString, std::deque<BelId>> available_bels; + for (auto bel : ctx->getBels()) { + if (!ctx->checkBelAvail(bel)) + continue; + available_bels[ctx->getBelType(bel)].push_back(bel); + } + for (auto &t : available_bels) { + std::random_shuffle(t.second.begin(), t.second.end(), [&](size_t n) { return ctx->rng(int(n)); }); + } + for (auto cell : sorted(ctx->cells)) { + CellInfo *ci = cell.second; + if (ci->bel != BelId()) { + Loc loc = ctx->getBelLocation(ci->bel); + cell_locs[cell.first].x = loc.x; + cell_locs[cell.first].y = loc.y; + cell_locs[cell.first].locked = true; + cell_locs[cell.first].global = ctx->getBelGlobalBuf(ci->bel); + } else if (ci->constr_parent == nullptr) { + bool placed = false; + while (!placed) { + if (!available_bels.count(ci->type) || available_bels.at(ci->type).empty()) + log_error("Unable to place cell '%s', no Bels remaining of type '%s'\n", ci->name.c_str(ctx), + ci->type.c_str(ctx)); + BelId bel = available_bels.at(ci->type).back(); + available_bels.at(ci->type).pop_back(); + Loc loc = ctx->getBelLocation(bel); + cell_locs[cell.first].x = loc.x; + cell_locs[cell.first].y = loc.y; + cell_locs[cell.first].locked = false; + cell_locs[cell.first].global = ctx->getBelGlobalBuf(bel); + // FIXME + if (has_connectivity(cell.second) && !cfg.ioBufTypes.count(ci->type)) { + place_cells.push_back(ci); + placed = true; + } else { + if (ctx->isValidBelForCell(ci, bel)) { + ctx->bindBel(bel, ci, STRENGTH_STRONG); + cell_locs[cell.first].locked = true; + placed = true; + } else { + available_bels.at(ci->type).push_front(bel); + } + } + } + } + } + } + + // Setup the cells to be solved, returns the number of rows + int setup_solve_cells(std::unordered_set<IdString> *celltypes = nullptr) + { + int row = 0; + solve_cells.clear(); + // First clear the udata of all cells + for (auto cell : sorted(ctx->cells)) + cell.second->udata = dont_solve; + // Then update cells to be placed, which excludes cell children + for (auto cell : place_cells) { + if (celltypes && !celltypes->count(cell->type)) + continue; + cell->udata = row++; + solve_cells.push_back(cell); + } + // Finally, update the udata of children + for (auto chained : chain_root) + ctx->cells.at(chained.first)->udata = chained.second->udata; + return row; + } + + // Update the location of all children of a chain + void update_chain(CellInfo *cell, CellInfo *root) + { + const auto &base = cell_locs[cell->name]; + for (auto child : cell->constr_children) { + chain_size[root->name]++; + if (child->constr_x != child->UNCONSTR) + cell_locs[child->name].x = std::min(max_x, base.x + child->constr_x); + else + cell_locs[child->name].x = base.x; // better handling of UNCONSTR? + if (child->constr_y != child->UNCONSTR) + cell_locs[child->name].y = std::min(max_y, base.y + child->constr_y); + else + cell_locs[child->name].y = base.y; // better handling of UNCONSTR? + chain_root[child->name] = root; + if (!child->constr_children.empty()) + update_chain(child, root); + } + } + + // Update all chains + void update_all_chains() + { + for (auto cell : place_cells) { + chain_size[cell->name] = 1; + if (!cell->constr_children.empty()) + update_chain(cell, cell); + } + } + + // Run a function on all ports of a net - including the driver and all users + template <typename Tf> void foreach_port(NetInfo *net, Tf func) + { + if (net->driver.cell != nullptr) + func(net->driver, -1); + for (size_t i = 0; i < net->users.size(); i++) + func(net->users.at(i), i); + } + + // Build the system of equations for either X or Y + void build_equations(EquationSystem<double> &es, bool yaxis, int iter = -1) + { + // Return the x or y position of a cell, depending on ydir + auto cell_pos = [&](CellInfo *cell) { return yaxis ? cell_locs.at(cell->name).y : cell_locs.at(cell->name).x; }; + auto legal_pos = [&](CellInfo *cell) { + return yaxis ? cell_locs.at(cell->name).legal_y : cell_locs.at(cell->name).legal_x; + }; + + es.reset(); + + for (auto net : sorted(ctx->nets)) { + NetInfo *ni = net.second; + if (ni->driver.cell == nullptr) + continue; + if (ni->users.empty()) + continue; + if (cell_locs.at(ni->driver.cell->name).global) + continue; + // Find the bounds of the net in this axis, and the ports that correspond to these bounds + PortRef *lbport = nullptr, *ubport = nullptr; + int lbpos = std::numeric_limits<int>::max(), ubpos = std::numeric_limits<int>::min(); + foreach_port(ni, [&](PortRef &port, int user_idx) { + int pos = cell_pos(port.cell); + if (pos < lbpos) { + lbpos = pos; + lbport = &port; + } + if (pos > ubpos) { + ubpos = pos; + ubport = &port; + } + }); + NPNR_ASSERT(lbport != nullptr); + NPNR_ASSERT(ubport != nullptr); + + auto stamp_equation = [&](PortRef &var, PortRef &eqn, double weight) { + if (eqn.cell->udata == dont_solve) + return; + int row = eqn.cell->udata; + int v_pos = cell_pos(var.cell); + if (var.cell->udata != dont_solve) { + es.add_coeff(row, var.cell->udata, weight); + } else { + es.add_rhs(row, -v_pos * weight); + } + if (cell_offsets.count(var.cell->name)) { + es.add_rhs(row, -(yaxis ? cell_offsets.at(var.cell->name).second + : cell_offsets.at(var.cell->name).first) * + weight); + } + }; + + // Add all relevant connections to the matrix + foreach_port(ni, [&](PortRef &port, int user_idx) { + int this_pos = cell_pos(port.cell); + auto process_arc = [&](PortRef *other) { + if (other == &port) + return; + int o_pos = cell_pos(other->cell); + double weight = 1.0 / (ni->users.size() * std::max<double>(1, std::abs(o_pos - this_pos))); + + if (user_idx != -1 && net_crit.count(ni->name)) { + auto &nc = net_crit.at(ni->name); + if (user_idx < int(nc.criticality.size())) + weight *= (1.0 + cfg.timingWeight * + std::pow(nc.criticality.at(user_idx), cfg.criticalityExponent)); + } + + // If cell 0 is not fixed, it will stamp +w on its equation and -w on the other end's equation, + // if the other end isn't fixed + stamp_equation(port, port, weight); + stamp_equation(port, *other, -weight); + stamp_equation(*other, *other, weight); + stamp_equation(*other, port, -weight); + }; + process_arc(lbport); + process_arc(ubport); + }); + } + if (iter != -1) { + float alpha = cfg.alpha; + for (size_t row = 0; row < solve_cells.size(); row++) { + int l_pos = legal_pos(solve_cells.at(row)); + int c_pos = cell_pos(solve_cells.at(row)); + + double weight = alpha * iter / std::max<double>(1, std::abs(l_pos - c_pos)); + // Add an arc from legalised to current position + es.add_coeff(row, row, weight); + es.add_rhs(row, weight * l_pos); + } + } + } + + // Build the system of equations for either X or Y + void solve_equations(EquationSystem<double> &es, bool yaxis) + { + // Return the x or y position of a cell, depending on ydir + auto cell_pos = [&](CellInfo *cell) { return yaxis ? cell_locs.at(cell->name).y : cell_locs.at(cell->name).x; }; + std::vector<double> vals; + std::transform(solve_cells.begin(), solve_cells.end(), std::back_inserter(vals), cell_pos); + es.solve(vals); + for (size_t i = 0; i < vals.size(); i++) + if (yaxis) { + cell_locs.at(solve_cells.at(i)->name).rawy = vals.at(i); + cell_locs.at(solve_cells.at(i)->name).y = std::min(max_y, std::max(0, int(vals.at(i)))); + } else { + cell_locs.at(solve_cells.at(i)->name).rawx = vals.at(i); + cell_locs.at(solve_cells.at(i)->name).x = std::min(max_x, std::max(0, int(vals.at(i)))); + } + } + + // Compute HPWL + wirelen_t total_hpwl() + { + wirelen_t hpwl = 0; + for (auto net : sorted(ctx->nets)) { + NetInfo *ni = net.second; + if (ni->driver.cell == nullptr) + continue; + CellLocation &drvloc = cell_locs.at(ni->driver.cell->name); + if (drvloc.global) + continue; + int xmin = drvloc.x, xmax = drvloc.x, ymin = drvloc.y, ymax = drvloc.y; + for (auto &user : ni->users) { + CellLocation &usrloc = cell_locs.at(user.cell->name); + xmin = std::min(xmin, usrloc.x); + xmax = std::max(xmax, usrloc.x); + ymin = std::min(ymin, usrloc.y); + ymax = std::max(ymax, usrloc.y); + } + hpwl += (xmax - xmin) + (ymax - ymin); + } + return hpwl; + } + + // Strict placement legalisation, performed after the initial HeAP spreading + void legalise_placement_strict(bool require_validity = false) + { + auto startt = std::chrono::high_resolution_clock::now(); + + // Unbind all cells placed in this solution + for (auto cell : sorted(ctx->cells)) { + CellInfo *ci = cell.second; + if (ci->bel != BelId() && (ci->udata != dont_solve || + (chain_root.count(ci->name) && chain_root.at(ci->name)->udata != dont_solve))) + ctx->unbindBel(ci->bel); + } + + // At the moment we don't follow the full HeAP algorithm using cuts for legalisation, instead using + // the simple greedy largest-macro-first approach. + std::priority_queue<std::pair<int, IdString>> remaining; + for (auto cell : solve_cells) { + remaining.emplace(chain_size[cell->name], cell->name); + } + int ripup_radius = 2; + int total_iters = 0; + while (!remaining.empty()) { + auto top = remaining.top(); + remaining.pop(); + + CellInfo *ci = ctx->cells.at(top.second).get(); + // Was now placed, ignore + if (ci->bel != BelId()) + continue; + // log_info(" Legalising %s (%s)\n", top.second.c_str(ctx), ci->type.c_str(ctx)); + int bt = std::get<0>(bel_types.at(ci->type)); + auto &fb = fast_bels.at(bt); + int radius = 0; + int iter = 0; + int iter_at_radius = 0; + bool placed = false; + BelId bestBel; + int best_inp_len = std::numeric_limits<int>::max(); + + total_iters++; + if (total_iters > int(solve_cells.size())) { + total_iters = 0; + ripup_radius = std::max(std::max(max_x, max_y), ripup_radius * 2); + } + + while (!placed) { + + int nx = ctx->rng(2 * radius + 1) + std::max(cell_locs.at(ci->name).x - radius, 0); + int ny = ctx->rng(2 * radius + 1) + std::max(cell_locs.at(ci->name).y - radius, 0); + + iter++; + iter_at_radius++; + if (iter >= (10 * (radius + 1))) { + radius = std::min(std::max(max_x, max_y), radius + 1); + while (radius < std::max(max_x, max_y)) { + for (int x = std::max(0, cell_locs.at(ci->name).x - radius); + x <= std::min(max_x, cell_locs.at(ci->name).x + radius); x++) { + if (x >= int(fb.size())) + break; + for (int y = std::max(0, cell_locs.at(ci->name).y - radius); + y <= std::min(max_y, cell_locs.at(ci->name).y + radius); y++) { + if (y >= int(fb.at(x).size())) + break; + if (fb.at(x).at(y).size() > 0) + goto notempty; + } + } + radius = std::min(std::max(max_x, max_y), radius + 1); + } + notempty: + iter_at_radius = 0; + iter = 0; + } + if (nx < 0 || nx > max_x) + continue; + if (ny < 0 || ny > max_y) + continue; + + // ny = nearest_row_with_bel.at(bt).at(ny); + // nx = nearest_col_with_bel.at(bt).at(nx); + + if (nx >= int(fb.size())) + continue; + if (ny >= int(fb.at(nx).size())) + continue; + if (fb.at(nx).at(ny).empty()) + continue; + + int need_to_explore = 2 * radius; + + if (iter_at_radius >= need_to_explore && bestBel != BelId()) { + CellInfo *bound = ctx->getBoundBelCell(bestBel); + if (bound != nullptr) { + ctx->unbindBel(bound->bel); + remaining.emplace(chain_size[bound->name], bound->name); + } + ctx->bindBel(bestBel, ci, STRENGTH_WEAK); + placed = true; + Loc loc = ctx->getBelLocation(bestBel); + cell_locs[ci->name].x = loc.x; + cell_locs[ci->name].y = loc.y; + break; + } + + if (ci->constr_children.empty() && !ci->constr_abs_z) { + for (auto sz : fb.at(nx).at(ny)) { + if (ctx->checkBelAvail(sz) || (radius > ripup_radius || ctx->rng(20000) < 10)) { + CellInfo *bound = ctx->getBoundBelCell(sz); + if (bound != nullptr) { + if (bound->constr_parent != nullptr || !bound->constr_children.empty() || + bound->constr_abs_z) + continue; + ctx->unbindBel(bound->bel); + } + ctx->bindBel(sz, ci, STRENGTH_WEAK); + if (require_validity && !ctx->isBelLocationValid(sz)) { + ctx->unbindBel(sz); + if (bound != nullptr) + ctx->bindBel(sz, bound, STRENGTH_WEAK); + } else if (iter_at_radius < need_to_explore) { + ctx->unbindBel(sz); + if (bound != nullptr) + ctx->bindBel(sz, bound, STRENGTH_WEAK); + int input_len = 0; + for (auto &port : ci->ports) { + auto &p = port.second; + if (p.type != PORT_IN || p.net == nullptr || p.net->driver.cell == nullptr) + continue; + CellInfo *drv = p.net->driver.cell; + auto drv_loc = cell_locs.find(drv->name); + if (drv_loc == cell_locs.end()) + continue; + if (drv_loc->second.global) + continue; + input_len += std::abs(drv_loc->second.x - nx) + std::abs(drv_loc->second.y - ny); + } + if (input_len < best_inp_len) { + best_inp_len = input_len; + bestBel = sz; + } + break; + } else { + if (bound != nullptr) + remaining.emplace(chain_size[bound->name], bound->name); + Loc loc = ctx->getBelLocation(sz); + cell_locs[ci->name].x = loc.x; + cell_locs[ci->name].y = loc.y; + placed = true; + break; + } + } + } + } else { + for (auto sz : fb.at(nx).at(ny)) { + Loc loc = ctx->getBelLocation(sz); + if (ci->constr_abs_z && loc.z != ci->constr_z) + continue; + std::vector<std::pair<CellInfo *, BelId>> targets; + std::vector<std::pair<BelId, CellInfo *>> swaps_made; + std::queue<std::pair<CellInfo *, Loc>> visit; + visit.emplace(ci, loc); + while (!visit.empty()) { + CellInfo *vc = visit.front().first; + NPNR_ASSERT(vc->bel == BelId()); + Loc ploc = visit.front().second; + visit.pop(); + BelId target = ctx->getBelByLocation(ploc); + CellInfo *bound; + if (target == BelId() || ctx->getBelType(target) != vc->type) + goto fail; + bound = ctx->getBoundBelCell(target); + // Chains cannot overlap + if (bound != nullptr) + if (bound->constr_z != bound->UNCONSTR || bound->constr_parent != nullptr || + !bound->constr_children.empty() || bound->belStrength > STRENGTH_WEAK) + goto fail; + targets.emplace_back(vc, target); + for (auto child : vc->constr_children) { + Loc cloc = ploc; + if (child->constr_x != child->UNCONSTR) + cloc.x += child->constr_x; + if (child->constr_y != child->UNCONSTR) + cloc.y += child->constr_y; + if (child->constr_z != child->UNCONSTR) + cloc.z = child->constr_abs_z ? child->constr_z : (ploc.z + child->constr_z); + visit.emplace(child, cloc); + } + } + + for (auto &target : targets) { + CellInfo *bound = ctx->getBoundBelCell(target.second); + if (bound != nullptr) + ctx->unbindBel(target.second); + ctx->bindBel(target.second, target.first, STRENGTH_STRONG); + swaps_made.emplace_back(target.second, bound); + } + + for (auto &sm : swaps_made) { + if (!ctx->isBelLocationValid(sm.first)) + goto fail; + } + + if (false) { + fail: + for (auto &swap : swaps_made) { + ctx->unbindBel(swap.first); + if (swap.second != nullptr) + ctx->bindBel(swap.first, swap.second, STRENGTH_WEAK); + } + continue; + } + for (auto &target : targets) { + Loc loc = ctx->getBelLocation(target.second); + cell_locs[target.first->name].x = loc.x; + cell_locs[target.first->name].y = loc.y; + // log_info("%s %d %d %d\n", target.first->name.c_str(ctx), loc.x, loc.y, loc.z); + } + for (auto &swap : swaps_made) { + if (swap.second != nullptr) + remaining.emplace(chain_size[swap.second->name], swap.second->name); + } + + placed = true; + break; + } + } + } + } + auto endt = std::chrono::high_resolution_clock::now(); + sl_time += std::chrono::duration<float>(endt - startt).count(); + } + // Implementation of the cut-based spreading as described in the HeAP/SimPL papers + static constexpr float beta = 0.9; + + struct ChainExtent + { + int x0, y0, x1, y1; + }; + + struct SpreaderRegion + { + int id; + int x0, y0, x1, y1; + int cells, bels; + bool overused() const + { + if (bels < 4) + return cells > bels; + else + return cells > beta * bels; + } + }; + + class CutSpreader + { + public: + CutSpreader(HeAPPlacer *p, IdString beltype) + : p(p), ctx(p->ctx), beltype(beltype), fb(p->fast_bels.at(std::get<0>(p->bel_types.at(beltype)))) + { + } + static int seq; + void run() + { + auto startt = std::chrono::high_resolution_clock::now(); + init(); + find_overused_regions(); + for (auto &r : regions) { + if (merged_regions.count(r.id)) + continue; +#if 0 + log_info("%s (%d, %d) |_> (%d, %d) %d/%d\n", beltype.c_str(ctx), r.x0, r.y0, r.x1, r.y1, r.cells, + r.bels); +#endif + } + expand_regions(); + std::queue<std::pair<int, bool>> workqueue; +#if 0 + std::vector<std::pair<double, double>> orig; + if (ctx->debug) + for (auto c : p->solve_cells) + orig.emplace_back(p->cell_locs[c->name].rawx, p->cell_locs[c->name].rawy); +#endif + for (auto &r : regions) { + if (merged_regions.count(r.id)) + continue; +#if 0 + log_info("%s (%d, %d) |_> (%d, %d) %d/%d\n", beltype.c_str(ctx), r.x0, r.y0, r.x1, r.y1, r.cells, + r.bels); +#endif + workqueue.emplace(r.id, false); + // cut_region(r, false); + } + while (!workqueue.empty()) { + auto front = workqueue.front(); + workqueue.pop(); + auto &r = regions.at(front.first); + if (r.cells == 0) + continue; + auto res = cut_region(r, front.second); + if (res) { + workqueue.emplace(res->first, !front.second); + workqueue.emplace(res->second, !front.second); + } else { + // Try the other dir, in case stuck in one direction only + auto res2 = cut_region(r, !front.second); + if (res2) { + // log_info("RETRY SUCCESS\n"); + workqueue.emplace(res2->first, front.second); + workqueue.emplace(res2->second, front.second); + } + } + } +#if 0 + if (ctx->debug) { + std::ofstream sp("spread" + std::to_string(seq) + ".csv"); + for (size_t i = 0; i < p->solve_cells.size(); i++) { + auto &c = p->solve_cells.at(i); + if (c->type != beltype) + continue; + sp << orig.at(i).first << "," << orig.at(i).second << "," << p->cell_locs[c->name].rawx << "," << p->cell_locs[c->name].rawy << std::endl; + } + std::ofstream oc("cells" + std::to_string(seq) + ".csv"); + for (size_t y = 0; y <= p->max_y; y++) { + for (size_t x = 0; x <= p->max_x; x++) { + oc << cells_at_location.at(x).at(y).size() << ", "; + } + oc << std::endl; + } + ++seq; + } +#endif + auto endt = std::chrono::high_resolution_clock::now(); + p->cl_time += std::chrono::duration<float>(endt - startt).count(); + } + + private: + HeAPPlacer *p; + Context *ctx; + IdString beltype; + std::vector<std::vector<int>> occupancy; + std::vector<std::vector<int>> groups; + std::vector<std::vector<ChainExtent>> chaines; + std::map<IdString, ChainExtent> cell_extents; + + std::vector<std::vector<std::vector<BelId>>> &fb; + + std::vector<SpreaderRegion> regions; + std::unordered_set<int> merged_regions; + // Cells at a location, sorted by real (not integer) x and y + std::vector<std::vector<std::vector<CellInfo *>>> cells_at_location; + + int occ_at(int x, int y) { return occupancy.at(x).at(y); } + + int bels_at(int x, int y) + { + if (x >= int(fb.size()) || y >= int(fb.at(x).size())) + return 0; + return int(fb.at(x).at(y).size()); + } + + void init() + { + occupancy.resize(p->max_x + 1, std::vector<int>(p->max_y + 1, 0)); + groups.resize(p->max_x + 1, std::vector<int>(p->max_y + 1, -1)); + chaines.resize(p->max_x + 1, std::vector<ChainExtent>(p->max_y + 1)); + cells_at_location.resize(p->max_x + 1, std::vector<std::vector<CellInfo *>>(p->max_y + 1)); + for (int x = 0; x <= p->max_x; x++) + for (int y = 0; y <= p->max_y; y++) { + occupancy.at(x).at(y) = 0; + groups.at(x).at(y) = -1; + chaines.at(x).at(y) = {x, y, x, y}; + } + + auto set_chain_ext = [&](IdString cell, int x, int y) { + if (!cell_extents.count(cell)) + cell_extents[cell] = {x, y, x, y}; + else { + cell_extents[cell].x0 = std::min(cell_extents[cell].x0, x); + cell_extents[cell].y0 = std::min(cell_extents[cell].y0, y); + cell_extents[cell].x1 = std::max(cell_extents[cell].x1, x); + cell_extents[cell].y1 = std::max(cell_extents[cell].y1, y); + } + }; + + for (auto &cell : p->cell_locs) { + if (ctx->cells.at(cell.first)->type != beltype) + continue; + if (ctx->cells.at(cell.first)->belStrength > STRENGTH_STRONG) + continue; + occupancy.at(cell.second.x).at(cell.second.y)++; + // Compute ultimate extent of each chain root + if (p->chain_root.count(cell.first)) { + set_chain_ext(p->chain_root.at(cell.first)->name, cell.second.x, cell.second.y); + } else if (!ctx->cells.at(cell.first)->constr_children.empty()) { + set_chain_ext(cell.first, cell.second.x, cell.second.y); + } + } + for (auto &cell : p->cell_locs) { + if (ctx->cells.at(cell.first)->type != beltype) + continue; + // Transfer chain extents to the actual chaines structure + ChainExtent *ce = nullptr; + if (p->chain_root.count(cell.first)) + ce = &(cell_extents.at(p->chain_root.at(cell.first)->name)); + else if (!ctx->cells.at(cell.first)->constr_children.empty()) + ce = &(cell_extents.at(cell.first)); + if (ce) { + auto &lce = chaines.at(cell.second.x).at(cell.second.y); + lce.x0 = std::min(lce.x0, ce->x0); + lce.y0 = std::min(lce.y0, ce->y0); + lce.x1 = std::max(lce.x1, ce->x1); + lce.y1 = std::max(lce.y1, ce->y1); + } + } + for (auto cell : p->solve_cells) { + if (cell->type != beltype) + continue; + cells_at_location.at(p->cell_locs.at(cell->name).x).at(p->cell_locs.at(cell->name).y).push_back(cell); + } + } + void merge_regions(SpreaderRegion &merged, SpreaderRegion &mergee) + { + // Prevent grow_region from recursing while doing this + for (int x = mergee.x0; x <= mergee.x1; x++) + for (int y = mergee.y0; y <= mergee.y1; y++) { + // log_info("%d %d\n", groups.at(x).at(y), mergee.id); + NPNR_ASSERT(groups.at(x).at(y) == mergee.id); + groups.at(x).at(y) = merged.id; + merged.cells += occ_at(x, y); + merged.bels += bels_at(x, y); + } + merged_regions.insert(mergee.id); + grow_region(merged, mergee.x0, mergee.y0, mergee.x1, mergee.y1); + } + + void grow_region(SpreaderRegion &r, int x0, int y0, int x1, int y1, bool init = false) + { + // log_info("growing to (%d, %d) |_> (%d, %d)\n", x0, y0, x1, y1); + if ((x0 >= r.x0 && y0 >= r.y0 && x1 <= r.x1 && y1 <= r.y1) || init) + return; + int old_x0 = r.x0 + (init ? 1 : 0), old_y0 = r.y0, old_x1 = r.x1, old_y1 = r.y1; + r.x0 = std::min(r.x0, x0); + r.y0 = std::min(r.y0, y0); + r.x1 = std::max(r.x1, x1); + r.y1 = std::max(r.y1, y1); + + auto process_location = [&](int x, int y) { + // Merge with any overlapping regions + if (groups.at(x).at(y) == -1) { + r.bels += bels_at(x, y); + r.cells += occ_at(x, y); + } + if (groups.at(x).at(y) != -1 && groups.at(x).at(y) != r.id) + merge_regions(r, regions.at(groups.at(x).at(y))); + groups.at(x).at(y) = r.id; + // Grow to cover any chains + auto &chaine = chaines.at(x).at(y); + grow_region(r, chaine.x0, chaine.y0, chaine.x1, chaine.y1); + }; + for (int x = r.x0; x < old_x0; x++) + for (int y = r.y0; y <= r.y1; y++) + process_location(x, y); + for (int x = old_x1 + 1; x <= x1; x++) + for (int y = r.y0; y <= r.y1; y++) + process_location(x, y); + for (int y = r.y0; y < old_y0; y++) + for (int x = r.x0; x <= r.x1; x++) + process_location(x, y); + for (int y = old_y1 + 1; y <= r.y1; y++) + for (int x = r.x0; x <= r.x1; x++) + process_location(x, y); + } + + void find_overused_regions() + { + for (int x = 0; x <= p->max_x; x++) + for (int y = 0; y <= p->max_y; y++) { + // Either already in a group, or not overutilised. Ignore + if (groups.at(x).at(y) != -1 || (occ_at(x, y) <= bels_at(x, y))) + continue; + // log_info("%d %d %d\n", x, y, occ_at(x, y)); + int id = int(regions.size()); + groups.at(x).at(y) = id; + SpreaderRegion reg; + reg.id = id; + reg.x0 = reg.x1 = x; + reg.y0 = reg.y1 = y; + reg.bels = bels_at(x, y); + reg.cells = occ_at(x, y); + // Make sure we cover carries, etc + grow_region(reg, reg.x0, reg.y0, reg.x1, reg.y1, true); + + bool expanded = true; + while (expanded) { + expanded = false; + // Keep trying expansion in x and y, until we find no over-occupancy cells + // or hit grouped cells + + // First try expanding in x + if (reg.x1 < p->max_x) { + bool over_occ_x = false; + for (int y1 = reg.y0; y1 <= reg.y1; y1++) { + if (occ_at(reg.x1 + 1, y1) > bels_at(reg.x1 + 1, y1)) { + // log_info("(%d, %d) occ %d bels %d\n", reg.x1+ 1, y1, occ_at(reg.x1 + 1, y1), + // bels_at(reg.x1 + 1, y1)); + over_occ_x = true; + break; + } + } + if (over_occ_x) { + expanded = true; + grow_region(reg, reg.x0, reg.y0, reg.x1 + 1, reg.y1); + } + } + + if (reg.y1 < p->max_y) { + bool over_occ_y = false; + for (int x1 = reg.x0; x1 <= reg.x1; x1++) { + if (occ_at(x1, reg.y1 + 1) > bels_at(x1, reg.y1 + 1)) { + // log_info("(%d, %d) occ %d bels %d\n", x1, reg.y1 + 1, occ_at(x1, reg.y1 + 1), + // bels_at(x1, reg.y1 + 1)); + over_occ_y = true; + break; + } + } + if (over_occ_y) { + expanded = true; + grow_region(reg, reg.x0, reg.y0, reg.x1, reg.y1 + 1); + } + } + } + regions.push_back(reg); + } + } + + void expand_regions() + { + std::queue<int> overu_regions; + for (auto &r : regions) { + if (!merged_regions.count(r.id) && r.overused()) + overu_regions.push(r.id); + } + while (!overu_regions.empty()) { + int rid = overu_regions.front(); + overu_regions.pop(); + if (merged_regions.count(rid)) + continue; + auto ® = regions.at(rid); + while (reg.overused()) { + bool changed = false; + if (reg.x0 > 0) { + grow_region(reg, reg.x0 - 1, reg.y0, reg.x1, reg.y1); + changed = true; + if (!reg.overused()) + break; + } + if (reg.x1 < p->max_x) { + grow_region(reg, reg.x0, reg.y0, reg.x1 + 1, reg.y1); + changed = true; + if (!reg.overused()) + break; + } + if (reg.y0 > 0) { + grow_region(reg, reg.x0, reg.y0 - 1, reg.x1, reg.y1); + changed = true; + if (!reg.overused()) + break; + } + if (reg.y1 < p->max_y) { + grow_region(reg, reg.x0, reg.y0, reg.x1, reg.y1 + 1); + changed = true; + if (!reg.overused()) + break; + } + if (!changed) { + if (reg.cells > reg.bels) + log_error("Failed to expand region (%d, %d) |_> (%d, %d) of %d %ss\n", reg.x0, reg.y0, + reg.x1, reg.y1, reg.cells, beltype.c_str(ctx)); + else + break; + } + } + } + } + + // Implementation of the recursive cut-based spreading as described in the HeAP paper + // Note we use "left" to mean "-x/-y" depending on dir and "right" to mean "+x/+y" depending on dir + + std::vector<CellInfo *> cut_cells; + + boost::optional<std::pair<int, int>> cut_region(SpreaderRegion &r, bool dir) + { + cut_cells.clear(); + auto &cal = cells_at_location; + int total_cells = 0, total_bels = 0; + for (int x = r.x0; x <= r.x1; x++) { + for (int y = r.y0; y <= r.y1; y++) { + std::copy(cal.at(x).at(y).begin(), cal.at(x).at(y).end(), std::back_inserter(cut_cells)); + total_bels += bels_at(x, y); + } + } + for (auto &cell : cut_cells) { + total_cells += p->chain_size.count(cell->name) ? p->chain_size.at(cell->name) : 1; + } + std::sort(cut_cells.begin(), cut_cells.end(), [&](const CellInfo *a, const CellInfo *b) { + return dir ? (p->cell_locs.at(a->name).rawy < p->cell_locs.at(b->name).rawy) + : (p->cell_locs.at(a->name).rawx < p->cell_locs.at(b->name).rawx); + }); + + if (cut_cells.size() < 2) + return {}; + // Find the cells midpoint, counting chains in terms of their total size - making the initial source cut + int pivot_cells = 0; + int pivot = 0; + for (auto &cell : cut_cells) { + pivot_cells += p->chain_size.count(cell->name) ? p->chain_size.at(cell->name) : 1; + if (pivot_cells >= total_cells / 2) + break; + pivot++; + } + if (pivot == int(cut_cells.size())) + pivot = int(cut_cells.size()) - 1; + // log_info("orig pivot %d lc %d rc %d\n", pivot, pivot_cells, r.cells - pivot_cells); + + // Find the clearance required either side of the pivot + int clearance_l = 0, clearance_r = 0; + for (size_t i = 0; i < cut_cells.size(); i++) { + int size; + if (cell_extents.count(cut_cells.at(i)->name)) { + auto &ce = cell_extents.at(cut_cells.at(i)->name); + size = dir ? (ce.y1 - ce.y0 + 1) : (ce.x1 - ce.x0 + 1); + } else { + size = 1; + } + if (int(i) < pivot) + clearance_l = std::max(clearance_l, size); + else + clearance_r = std::max(clearance_r, size); + } + // Find the target cut that minimises difference in utilisation, whilst trying to ensure that all chains + // still fit + + // First trim the boundaries of the region in the axis-of-interest, skipping any rows/cols without any + // bels of the appropriate type + int trimmed_l = dir ? r.y0 : r.x0, trimmed_r = dir ? r.y1 : r.x1; + while (trimmed_l < (dir ? r.y1 : r.x1)) { + bool have_bels = false; + for (int i = dir ? r.x0 : r.y0; i <= (dir ? r.x1 : r.y1); i++) + if (bels_at(dir ? i : trimmed_l, dir ? trimmed_l : i) > 0) { + have_bels = true; + break; + } + if (have_bels) + break; + trimmed_l++; + } + while (trimmed_r > (dir ? r.y0 : r.x0)) { + bool have_bels = false; + for (int i = dir ? r.x0 : r.y0; i <= (dir ? r.x1 : r.y1); i++) + if (bels_at(dir ? i : trimmed_r, dir ? trimmed_r : i) > 0) { + have_bels = true; + break; + } + if (have_bels) + break; + trimmed_r--; + } + // log_info("tl %d tr %d cl %d cr %d\n", trimmed_l, trimmed_r, clearance_l, clearance_r); + if ((trimmed_r - trimmed_l + 1) <= std::max(clearance_l, clearance_r)) + return {}; + // Now find the initial target cut that minimises utilisation imbalance, whilst + // meeting the clearance requirements for any large macros + int left_cells = pivot_cells, right_cells = total_cells - pivot_cells; + int left_bels = 0, right_bels = total_bels; + int best_tgt_cut = -1; + double best_deltaU = std::numeric_limits<double>::max(); + std::pair<int, int> target_cut_bels; + for (int i = trimmed_l; i <= trimmed_r; i++) { + int slither_bels = 0; + for (int j = dir ? r.x0 : r.y0; j <= (dir ? r.x1 : r.y1); j++) { + slither_bels += dir ? bels_at(j, i) : bels_at(i, j); + } + left_bels += slither_bels; + right_bels -= slither_bels; + if (((i - trimmed_l) + 1) >= clearance_l && ((trimmed_r - i) + 1) >= clearance_r) { + // Solution is potentially valid + double aU = + std::abs(double(left_cells) / double(left_bels) - double(right_cells) / double(right_bels)); + if (aU < best_deltaU) { + best_deltaU = aU; + best_tgt_cut = i; + target_cut_bels = std::make_pair(left_bels, right_bels); + } + } + } + if (best_tgt_cut == -1) + return {}; + left_bels = target_cut_bels.first; + right_bels = target_cut_bels.second; + // log_info("pivot %d target cut %d lc %d lb %d rc %d rb %d\n", pivot, best_tgt_cut, left_cells, left_bels, + // right_cells, right_bels); + + // Peturb the source cut to eliminate overutilisation + while (pivot > 0 && (double(left_cells) / double(left_bels) > double(right_cells) / double(right_bels))) { + auto &move_cell = cut_cells.at(pivot); + int size = p->chain_size.count(move_cell->name) ? p->chain_size.at(move_cell->name) : 1; + left_cells -= size; + right_cells += size; + pivot--; + } + while (pivot < int(cut_cells.size()) - 1 && + (double(left_cells) / double(left_bels) < double(right_cells) / double(right_bels))) { + auto &move_cell = cut_cells.at(pivot + 1); + int size = p->chain_size.count(move_cell->name) ? p->chain_size.at(move_cell->name) : 1; + left_cells += size; + right_cells -= size; + pivot++; + } + // log_info("peturbed pivot %d lc %d lb %d rc %d rb %d\n", pivot, left_cells, left_bels, right_cells, + // right_bels); + // Split regions into bins, and then spread cells by linear interpolation within those bins + auto spread_binlerp = [&](int cells_start, int cells_end, double area_l, double area_r) { + int N = cells_end - cells_start; + if (N <= 2) { + for (int i = cells_start; i < cells_end; i++) { + auto &pos = dir ? p->cell_locs.at(cut_cells.at(i)->name).rawy + : p->cell_locs.at(cut_cells.at(i)->name).rawx; + pos = area_l + i * ((area_r - area_l) / N); + } + return; + } + // Split region into up to 10 (K) bins + int K = std::min<int>(N, 10); + std::vector<std::pair<int, double>> bin_bounds; // [(cell start, area start)] + bin_bounds.emplace_back(cells_start, area_l); + for (int i = 1; i < K; i++) + bin_bounds.emplace_back(cells_start + (N * i) / K, area_l + ((area_r - area_l + 0.99) * i) / K); + bin_bounds.emplace_back(cells_end, area_r + 0.99); + for (int i = 0; i < K; i++) { + auto &bl = bin_bounds.at(i), br = bin_bounds.at(i + 1); + double orig_left = dir ? p->cell_locs.at(cut_cells.at(bl.first)->name).rawy + : p->cell_locs.at(cut_cells.at(bl.first)->name).rawx; + double orig_right = dir ? p->cell_locs.at(cut_cells.at(br.first - 1)->name).rawy + : p->cell_locs.at(cut_cells.at(br.first - 1)->name).rawx; + double m = (br.second - bl.second) / std::max(0.00001, orig_right - orig_left); + for (int j = bl.first; j < br.first; j++) { + auto &pos = dir ? p->cell_locs.at(cut_cells.at(j)->name).rawy + : p->cell_locs.at(cut_cells.at(j)->name).rawx; + NPNR_ASSERT(pos >= orig_left && pos <= orig_right); + pos = bl.second + m * (pos - orig_left); + // log("[%f, %f] -> [%f, %f]: %f -> %f\n", orig_left, orig_right, bl.second, br.second, + // orig_pos, pos); + } + } + }; + spread_binlerp(0, pivot + 1, trimmed_l, best_tgt_cut); + spread_binlerp(pivot + 1, int(cut_cells.size()), best_tgt_cut + 1, trimmed_r); + // Update various data structures + for (int x = r.x0; x <= r.x1; x++) + for (int y = r.y0; y <= r.y1; y++) { + cells_at_location.at(x).at(y).clear(); + } + for (auto cell : cut_cells) { + auto &cl = p->cell_locs.at(cell->name); + cl.x = std::min(r.x1, std::max(r.x0, int(cl.rawx))); + cl.y = std::min(r.y1, std::max(r.y0, int(cl.rawy))); + cells_at_location.at(cl.x).at(cl.y).push_back(cell); + // log_info("spread pos %d %d\n", cl.x, cl.y); + } + SpreaderRegion rl, rr; + rl.id = int(regions.size()); + rl.x0 = r.x0; + rl.y0 = r.y0; + rl.x1 = dir ? r.x1 : best_tgt_cut; + rl.y1 = dir ? best_tgt_cut : r.y1; + rl.cells = left_cells; + rl.bels = left_bels; + rr.id = int(regions.size()) + 1; + rr.x0 = dir ? r.x0 : (best_tgt_cut + 1); + rr.y0 = dir ? (best_tgt_cut + 1) : r.y0; + rr.x1 = r.x1; + rr.y1 = r.y1; + rr.cells = right_cells; + rr.bels = right_bels; + regions.push_back(rl); + regions.push_back(rr); + for (int x = rl.x0; x <= rl.x1; x++) + for (int y = rl.y0; y <= rl.y1; y++) + groups.at(x).at(y) = rl.id; + for (int x = rr.x0; x <= rr.x1; x++) + for (int y = rr.y0; y <= rr.y1; y++) + groups.at(x).at(y) = rr.id; + return std::make_pair(rl.id, rr.id); + }; + }; + typedef decltype(CellInfo::udata) cell_udata_t; + cell_udata_t dont_solve = std::numeric_limits<cell_udata_t>::max(); +}; +int HeAPPlacer::CutSpreader::seq = 0; + +bool placer_heap(Context *ctx, PlacerHeapCfg cfg) { return HeAPPlacer(ctx, cfg).place(); } + +PlacerHeapCfg::PlacerHeapCfg(Context *ctx) : Settings(ctx) +{ + alpha = get<float>("placerHeap/alpha", 0.1); + criticalityExponent = get<int>("placerHeap/criticalityExponent", 2); + timingWeight = get<int>("placerHeap/timingWeight", 10); +} + +NEXTPNR_NAMESPACE_END + +#else + +#include "log.h" +#include "nextpnr.h" +#include "placer_heap.h" + +NEXTPNR_NAMESPACE_BEGIN +bool placer_heap(Context *ctx, PlacerHeapCfg cfg) +{ + log_error("nextpnr was built without the HeAP placer\n"); + return false; +} + +PlacerHeapCfg::PlacerHeapCfg(Context *ctx) : Settings(ctx) {} + +NEXTPNR_NAMESPACE_END + +#endif diff --git a/tests/ice40/main.cc b/common/placer_heap.h index 60b9fdaa..841aa0d9 100644 --- a/tests/ice40/main.cc +++ b/common/placer_heap.h @@ -1,7 +1,7 @@ /* * nextpnr -- Next Generation Place and Route * - * Copyright (C) 2018 Miodrag Milanovic <miodrag@symbioticeda.com> + * Copyright (C) 2019 David Shah <david@symbioticeda.com> * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above @@ -15,13 +15,33 @@ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. * + * [[cite]] HeAP + * Analytical Placement for Heterogeneous FPGAs, Marcel Gort and Jason H. Anderson + * https://janders.eecg.utoronto.ca/pdfs/marcelfpl12.pdf + * + * [[cite]] SimPL + * SimPL: An Effective Placement Algorithm, Myung-Chul Kim, Dong-Jin Lee and Igor L. Markov + * http://www.ece.umich.edu/cse/awards/pdfs/iccad10-simpl.pdf */ -#include <vector> -#include "gtest/gtest.h" +#ifndef PLACER_HEAP_H +#define PLACER_HEAP_H +#include "nextpnr.h" +#include "settings.h" + +NEXTPNR_NAMESPACE_BEGIN -int main(int argc, char **argv) +struct PlacerHeapCfg : public Settings { - ::testing::InitGoogleTest(&argc, argv); - return RUN_ALL_TESTS(); -} + PlacerHeapCfg(Context *ctx); + + float alpha; + float criticalityExponent; + float timingWeight; + + std::unordered_set<IdString> ioBufTypes; +}; + +extern bool placer_heap(Context *ctx, PlacerHeapCfg cfg); +NEXTPNR_NAMESPACE_END +#endif diff --git a/common/pybindings.cc b/common/pybindings.cc index 6cae889d..60f87e27 100644 --- a/common/pybindings.cc +++ b/common/pybindings.cc @@ -23,8 +23,10 @@ #include "pybindings.h" #include "arch_pybindings.h" #include "jsonparse.h" +#include "log.h" #include "nextpnr.h" +#include <boost/filesystem.hpp> #include <fstream> #include <memory> #include <signal.h> @@ -87,7 +89,26 @@ BOOST_PYTHON_MODULE(MODULE_NAME) using namespace PythonConversion; + enum_<GraphicElement::type_t>("GraphicElementType") + .value("TYPE_NONE", GraphicElement::TYPE_NONE) + .value("TYPE_LINE", GraphicElement::TYPE_LINE) + .value("TYPE_ARROW", GraphicElement::TYPE_ARROW) + .value("TYPE_BOX", GraphicElement::TYPE_BOX) + .value("TYPE_CIRCLE", GraphicElement::TYPE_CIRCLE) + .value("TYPE_LABEL", GraphicElement::TYPE_LABEL) + .export_values(); + + enum_<GraphicElement::style_t>("GraphicElementStyle") + .value("STYLE_GRID", GraphicElement::STYLE_GRID) + .value("STYLE_FRAME", GraphicElement::STYLE_FRAME) + .value("STYLE_HIDDEN", GraphicElement::STYLE_HIDDEN) + .value("STYLE_INACTIVE", GraphicElement::STYLE_INACTIVE) + .value("STYLE_ACTIVE", GraphicElement::STYLE_ACTIVE) + .export_values(); + class_<GraphicElement>("GraphicElement") + .def(init<GraphicElement::type_t, GraphicElement::style_t, float, float, float, float, float>( + (args("type"), "style", "x1", "y1", "x2", "y2", "z"))) .def_readwrite("type", &GraphicElement::type) .def_readwrite("x1", &GraphicElement::x1) .def_readwrite("y1", &GraphicElement::y1) @@ -104,9 +125,16 @@ BOOST_PYTHON_MODULE(MODULE_NAME) typedef std::unordered_map<IdString, std::string> AttrMap; typedef std::unordered_map<IdString, PortInfo> PortMap; typedef std::unordered_map<IdString, IdString> PinMap; + typedef std::unordered_map<IdString, std::unique_ptr<Region>> RegionMap; class_<BaseCtx, BaseCtx *, boost::noncopyable>("BaseCtx", no_init); + auto loc_cls = class_<Loc>("Loc") + .def(init<int, int, int>()) + .def_readwrite("x", &Loc::x) + .def_readwrite("y", &Loc::y) + .def_readwrite("z", &Loc::z); + auto ci_cls = class_<ContextualWrapper<CellInfo &>>("CellInfo", no_init); readwrite_wrapper<CellInfo &, decltype(&CellInfo::name), &CellInfo::name, conv_to_str<IdString>, conv_from_str<IdString>>::def_wrap(ci_cls, "name"); @@ -135,6 +163,8 @@ BOOST_PYTHON_MODULE(MODULE_NAME) typedef std::vector<PortRef> PortRefVector; typedef std::unordered_map<WireId, PipMap> WireMap; + typedef std::unordered_set<BelId> BelSet; + typedef std::unordered_set<WireId> WireSet; auto ni_cls = class_<ContextualWrapper<NetInfo &>>("NetInfo", no_init); readwrite_wrapper<NetInfo &, decltype(&NetInfo::name), &NetInfo::name, conv_to_str<IdString>, @@ -163,10 +193,25 @@ BOOST_PYTHON_MODULE(MODULE_NAME) def("parse_json", parse_json_shim); def("load_design", load_design_shim, return_value_policy<manage_new_object>()); + auto region_cls = class_<ContextualWrapper<Region &>>("Region", no_init); + readwrite_wrapper<Region &, decltype(&Region::name), &Region::name, conv_to_str<IdString>, + conv_from_str<IdString>>::def_wrap(region_cls, "name"); + readwrite_wrapper<Region &, decltype(&Region::constr_bels), &Region::constr_bels, pass_through<bool>, + pass_through<bool>>::def_wrap(region_cls, "constr_bels"); + readwrite_wrapper<Region &, decltype(&Region::constr_wires), &Region::constr_wires, pass_through<bool>, + pass_through<bool>>::def_wrap(region_cls, "constr_bels"); + readwrite_wrapper<Region &, decltype(&Region::constr_pips), &Region::constr_pips, pass_through<bool>, + pass_through<bool>>::def_wrap(region_cls, "constr_pips"); + readonly_wrapper<Region &, decltype(&Region::bels), &Region::bels, wrap_context<BelSet &>>::def_wrap(region_cls, + "bels"); + readonly_wrapper<Region &, decltype(&Region::wires), &Region::wires, wrap_context<WireSet &>>::def_wrap(region_cls, + "wires"); + WRAP_MAP(AttrMap, pass_through<std::string>, "AttrMap"); WRAP_MAP(PortMap, wrap_context<PortInfo &>, "PortMap"); WRAP_MAP(PinMap, conv_to_str<IdString>, "PinMap"); WRAP_MAP(WireMap, wrap_context<PipMap &>, "WireMap"); + WRAP_MAP_UPTR(RegionMap, "RegionMap"); WRAP_VECTOR(PortRefVector, wrap_context<PortRef &>); @@ -190,8 +235,14 @@ void init_python(const char *executable, bool first) PyImport_AppendInittab(TOSTRING(MODULE_NAME), PYINIT_MODULE_NAME); Py_SetProgramName(program); Py_Initialize(); - if (first) - PyImport_ImportModule(TOSTRING(MODULE_NAME)); + + // Add cwd to Python's search path so `import` can be used in user scripts + boost::filesystem::path cwd = boost::filesystem::absolute("./").normalize(); + PyObject *sys_path = PySys_GetObject("path"); + PyList_Insert(sys_path, 0, PyUnicode_FromString(cwd.string().c_str())); + + PyImport_ImportModule(TOSTRING(MODULE_NAME)); + PyRun_SimpleString("from " TOSTRING(MODULE_NAME) " import *"); } catch (boost::python::error_already_set const &) { // Parse and output the exception std::string perror_str = parse_python_exception(); @@ -217,12 +268,15 @@ void execute_python_file(const char *python_file) fprintf(stderr, "Fatal error: file not found %s\n", python_file); exit(1); } - PyRun_SimpleFile(fp, python_file); + int result = PyRun_SimpleFile(fp, python_file); fclose(fp); + if (result == -1) { + log_error("Error occurred while executing Python script %s\n", python_file); + } } catch (boost::python::error_already_set const &) { // Parse and output the exception std::string perror_str = parse_python_exception(); - std::cout << "Error in Python: " << perror_str << std::endl; + log_error("Error in Python: %s\n", perror_str.c_str()); } } diff --git a/common/pycontainers.h b/common/pycontainers.h index 70f69c51..5de2f6d2 100644 --- a/common/pycontainers.h +++ b/common/pycontainers.h @@ -345,6 +345,12 @@ template <typename T, typename value_conv> struct map_wrapper std::terminate(); } + static bool contains(wrapped_map &x, std::string const &i) + { + K k = PythonConversion::string_converter<K>().from_str(x.ctx, i); + return x.base.count(k); + } + static void wrap(const char *map_name, const char *kv_name, const char *kv_iter_name, const char *iter_name) { map_pair_wrapper<typename KV::first_type, typename KV::second_type, value_conv>::wrap(kv_name, kv_iter_name); @@ -353,6 +359,7 @@ template <typename T, typename value_conv> struct map_wrapper class_<wrapped_map>(map_name, no_init) .def("__iter__", rw::iter) .def("__len__", len) + .def("__contains__", contains) .def("__getitem__", get) .def("__setitem__", set, with_custodian_and_ward<1, 2>()); } @@ -465,6 +472,12 @@ template <typename T> struct map_wrapper_uptr std::terminate(); } + static bool contains(wrapped_map &x, std::string const &i) + { + K k = PythonConversion::string_converter<K>().from_str(x.ctx, i); + return x.base.count(k); + } + static void wrap(const char *map_name, const char *kv_name, const char *kv_iter_name, const char *iter_name) { map_pair_wrapper_uptr<typename KV::first_type, typename KV::second_type>::wrap(kv_name, kv_iter_name); @@ -473,6 +486,7 @@ template <typename T> struct map_wrapper_uptr class_<wrapped_map>(map_name, no_init) .def("__iter__", rw::iter) .def("__len__", len) + .def("__contains__", contains) .def("__getitem__", get) .def("__setitem__", set, with_custodian_and_ward<1, 2>()); } diff --git a/common/pywrappers.h b/common/pywrappers.h index 4e463afd..1d970985 100644 --- a/common/pywrappers.h +++ b/common/pywrappers.h @@ -155,11 +155,15 @@ template <typename Class, typename FuncT, FuncT fn, typename rv_conv> struct fn_ using class_type = typename WrapIfNotContext<Class>::maybe_wrapped_t; using conv_result_type = typename rv_conv::ret_type; - static conv_result_type wrapped_fn(class_type &cls) + static object wrapped_fn(class_type &cls) { Context *ctx = get_ctx<Class>(cls); Class &base = get_base<Class>(cls); - return rv_conv()(ctx, (base.*fn)()); + try { + return object(rv_conv()(ctx, (base.*fn)())); + } catch (bad_wrap &) { + return object(); + } } template <typename WrapCls> static void def_wrap(WrapCls cls_, const char *name) { cls_.def(name, wrapped_fn); } @@ -172,11 +176,15 @@ template <typename Class, typename FuncT, FuncT fn, typename rv_conv, typename a using conv_result_type = typename rv_conv::ret_type; using conv_arg1_type = typename arg1_conv::arg_type; - static conv_result_type wrapped_fn(class_type &cls, conv_arg1_type arg1) + static object wrapped_fn(class_type &cls, conv_arg1_type arg1) { Context *ctx = get_ctx<Class>(cls); Class &base = get_base<Class>(cls); - return rv_conv()(ctx, (base.*fn)(arg1_conv()(ctx, arg1))); + try { + return object(rv_conv()(ctx, (base.*fn)(arg1_conv()(ctx, arg1)))); + } catch (bad_wrap &) { + return object(); + } } template <typename WrapCls> static void def_wrap(WrapCls cls_, const char *name) { cls_.def(name, wrapped_fn); } @@ -191,11 +199,15 @@ struct fn_wrapper_2a using conv_arg1_type = typename arg1_conv::arg_type; using conv_arg2_type = typename arg2_conv::arg_type; - static conv_result_type wrapped_fn(class_type &cls, conv_arg1_type arg1, conv_arg2_type arg2) + static object wrapped_fn(class_type &cls, conv_arg1_type arg1, conv_arg2_type arg2) { Context *ctx = get_ctx<Class>(cls); Class &base = get_base<Class>(cls); - return rv_conv()(ctx, (base.*fn)(arg1_conv()(ctx, arg1), arg2_conv()(ctx, arg2))); + try { + return object(rv_conv()(ctx, (base.*fn)(arg1_conv()(ctx, arg1), arg2_conv()(ctx, arg2)))); + } catch (bad_wrap &) { + return object(); + } } template <typename WrapCls> static void def_wrap(WrapCls cls_, const char *name) { cls_.def(name, wrapped_fn); } @@ -212,11 +224,16 @@ struct fn_wrapper_3a using conv_arg2_type = typename arg2_conv::arg_type; using conv_arg3_type = typename arg3_conv::arg_type; - static conv_result_type wrapped_fn(class_type &cls, conv_arg1_type arg1, conv_arg2_type arg2, conv_arg3_type arg3) + static object wrapped_fn(class_type &cls, conv_arg1_type arg1, conv_arg2_type arg2, conv_arg3_type arg3) { Context *ctx = get_ctx<Class>(cls); Class &base = get_base<Class>(cls); - return rv_conv()(ctx, (base.*fn)(arg1_conv()(ctx, arg1), arg2_conv()(ctx, arg2), arg3_conv()(ctx, arg3))); + try { + return object( + rv_conv()(ctx, (base.*fn)(arg1_conv()(ctx, arg1), arg2_conv()(ctx, arg2), arg3_conv()(ctx, arg3)))); + } catch (bad_wrap &) { + return object(); + } } template <typename WrapCls> static void def_wrap(WrapCls cls_, const char *name) { cls_.def(name, wrapped_fn); } @@ -250,6 +267,11 @@ template <typename Class, typename FuncT, FuncT fn, typename arg1_conv> struct f } template <typename WrapCls> static void def_wrap(WrapCls cls_, const char *name) { cls_.def(name, wrapped_fn); } + + template <typename WrapCls, typename Ta> static void def_wrap(WrapCls cls_, const char *name, Ta a = arg("arg1")) + { + cls_.def(name, wrapped_fn, a); + } }; // Two parameters, one return @@ -267,9 +289,14 @@ template <typename Class, typename FuncT, FuncT fn, typename arg1_conv, typename } template <typename WrapCls> static void def_wrap(WrapCls cls_, const char *name) { cls_.def(name, wrapped_fn); } + + template <typename WrapCls, typename Ta> static void def_wrap(WrapCls cls_, const char *name, const Ta &a) + { + cls_.def(name, wrapped_fn, a); + } }; -// Three parameters, one return +// Three parameters, no return template <typename Class, typename FuncT, FuncT fn, typename arg1_conv, typename arg2_conv, typename arg3_conv> struct fn_wrapper_3a_v { @@ -286,6 +313,98 @@ struct fn_wrapper_3a_v } template <typename WrapCls> static void def_wrap(WrapCls cls_, const char *name) { cls_.def(name, wrapped_fn); } + + template <typename WrapCls, typename Ta> static void def_wrap(WrapCls cls_, const char *name, const Ta &a) + { + cls_.def(name, wrapped_fn, a); + } +}; + +// Four parameters, no return +template <typename Class, typename FuncT, FuncT fn, typename arg1_conv, typename arg2_conv, typename arg3_conv, + typename arg4_conv> +struct fn_wrapper_4a_v +{ + using class_type = typename WrapIfNotContext<Class>::maybe_wrapped_t; + using conv_arg1_type = typename arg1_conv::arg_type; + using conv_arg2_type = typename arg2_conv::arg_type; + using conv_arg3_type = typename arg3_conv::arg_type; + using conv_arg4_type = typename arg4_conv::arg_type; + + static void wrapped_fn(class_type &cls, conv_arg1_type arg1, conv_arg2_type arg2, conv_arg3_type arg3, + conv_arg4_type arg4) + { + Context *ctx = get_ctx<Class>(cls); + Class &base = get_base<Class>(cls); + return (base.*fn)(arg1_conv()(ctx, arg1), arg2_conv()(ctx, arg2), arg3_conv()(ctx, arg3), + arg4_conv()(ctx, arg4)); + } + + template <typename WrapCls> static void def_wrap(WrapCls cls_, const char *name) { cls_.def(name, wrapped_fn); } + + template <typename WrapCls, typename Ta> static void def_wrap(WrapCls cls_, const char *name, const Ta &a) + { + cls_.def(name, wrapped_fn, a); + } +}; + +// Five parameters, no return +template <typename Class, typename FuncT, FuncT fn, typename arg1_conv, typename arg2_conv, typename arg3_conv, + typename arg4_conv, typename arg5_conv> +struct fn_wrapper_5a_v +{ + using class_type = typename WrapIfNotContext<Class>::maybe_wrapped_t; + using conv_arg1_type = typename arg1_conv::arg_type; + using conv_arg2_type = typename arg2_conv::arg_type; + using conv_arg3_type = typename arg3_conv::arg_type; + using conv_arg4_type = typename arg4_conv::arg_type; + using conv_arg5_type = typename arg5_conv::arg_type; + + static void wrapped_fn(class_type &cls, conv_arg1_type arg1, conv_arg2_type arg2, conv_arg3_type arg3, + conv_arg4_type arg4, conv_arg5_type arg5) + { + Context *ctx = get_ctx<Class>(cls); + Class &base = get_base<Class>(cls); + return (base.*fn)(arg1_conv()(ctx, arg1), arg2_conv()(ctx, arg2), arg3_conv()(ctx, arg3), + arg4_conv()(ctx, arg4), arg5_conv()(ctx, arg5)); + } + + template <typename WrapCls> static void def_wrap(WrapCls cls_, const char *name) { cls_.def(name, wrapped_fn); } + + template <typename WrapCls, typename Ta> static void def_wrap(WrapCls cls_, const char *name, const Ta &a) + { + cls_.def(name, wrapped_fn, a); + } +}; + +// Six parameters, no return +template <typename Class, typename FuncT, FuncT fn, typename arg1_conv, typename arg2_conv, typename arg3_conv, + typename arg4_conv, typename arg5_conv, typename arg6_conv> +struct fn_wrapper_6a_v +{ + using class_type = typename WrapIfNotContext<Class>::maybe_wrapped_t; + using conv_arg1_type = typename arg1_conv::arg_type; + using conv_arg2_type = typename arg2_conv::arg_type; + using conv_arg3_type = typename arg3_conv::arg_type; + using conv_arg4_type = typename arg4_conv::arg_type; + using conv_arg5_type = typename arg5_conv::arg_type; + using conv_arg6_type = typename arg6_conv::arg_type; + + static void wrapped_fn(class_type &cls, conv_arg1_type arg1, conv_arg2_type arg2, conv_arg3_type arg3, + conv_arg4_type arg4, conv_arg5_type arg5, conv_arg6_type arg6) + { + Context *ctx = get_ctx<Class>(cls); + Class &base = get_base<Class>(cls); + return (base.*fn)(arg1_conv()(ctx, arg1), arg2_conv()(ctx, arg2), arg3_conv()(ctx, arg3), + arg4_conv()(ctx, arg4), arg5_conv()(ctx, arg5), arg6_conv()(ctx, arg6)); + } + + template <typename WrapCls> static void def_wrap(WrapCls cls_, const char *name) { cls_.def(name, wrapped_fn); } + + template <typename WrapCls, typename Ta> static void def_wrap(WrapCls cls_, const char *name, const Ta &a) + { + cls_.def(name, wrapped_fn, a); + } }; // Wrapped getter diff --git a/common/router1.cc b/common/router1.cc index cbc0df90..28a422c8 100644 --- a/common/router1.cc +++ b/common/router1.cc @@ -17,6 +17,7 @@ * */ +#include <chrono> #include <cmath> #include <queue> @@ -752,6 +753,7 @@ bool router1(Context *ctx, const Router1Cfg &cfg) log_break(); log_info("Routing..\n"); ctx->lock(); + auto rstart = std::chrono::high_resolution_clock::now(); log_info("Setting up routing queue.\n"); @@ -803,7 +805,9 @@ bool router1(Context *ctx, const Router1Cfg &cfg) router.arcs_with_ripup - last_arcs_with_ripup, router.arcs_without_ripup - last_arcs_without_ripup, int(router.arc_queue.size())); log_info("Routing complete.\n"); + auto rend = std::chrono::high_resolution_clock::now(); ctx->yield(); + log_info("Route time %.02fs\n", std::chrono::duration<float>(rend - rstart).count()); #ifndef NDEBUG router.check(); diff --git a/common/settings.h b/common/settings.h index 0c4a67db..b57947c9 100644 --- a/common/settings.h +++ b/common/settings.h @@ -45,19 +45,30 @@ class Settings return defaultValue; } - template <typename T> void set(const char *name, T value) - { - IdString id = ctx->id(name); - auto pair = ctx->settings.emplace(id, std::to_string(value)); - if (!pair.second) { - ctx->settings[pair.first->first] = value; - } - } + template <typename T> void set(const char *name, T value); private: Context *ctx; }; +template <typename T> inline void Settings::set(const char *name, T value) +{ + IdString id = ctx->id(name); + auto pair = ctx->settings.emplace(id, std::to_string(value)); + if (!pair.second) { + ctx->settings[pair.first->first] = value; + } +} + +template <> inline void Settings::set<std::string>(const char *name, std::string value) +{ + IdString id = ctx->id(name); + auto pair = ctx->settings.emplace(id, value); + if (!pair.second) { + ctx->settings[pair.first->first] = value; + } +} + NEXTPNR_NAMESPACE_END #endif // SETTINGS_H diff --git a/common/timing.cc b/common/timing.cc index 88ab14c2..2ce9eea3 100644 --- a/common/timing.cc +++ b/common/timing.cc @@ -86,6 +86,7 @@ struct CriticalPath }; typedef std::unordered_map<ClockPair, CriticalPath> CriticalPathMap; +typedef std::unordered_map<IdString, NetCriticalityInfo> NetCriticalityMap; struct Timing { @@ -95,6 +96,7 @@ struct Timing delay_t min_slack; CriticalPathMap *crit_path; DelayFrequency *slack_histogram; + NetCriticalityMap *net_crit; IdString async_clock; struct TimingData @@ -105,13 +107,15 @@ struct Timing unsigned max_path_length = 0; delay_t min_remaining_budget; bool false_startpoint = false; + std::vector<delay_t> min_required; std::unordered_map<ClockEvent, delay_t> arrival_time; }; Timing(Context *ctx, bool net_delays, bool update, CriticalPathMap *crit_path = nullptr, - DelayFrequency *slack_histogram = nullptr) + DelayFrequency *slack_histogram = nullptr, NetCriticalityMap *net_crit = nullptr) : ctx(ctx), net_delays(net_delays), update(update), min_slack(1.0e12 / ctx->target_freq), - crit_path(crit_path), slack_histogram(slack_histogram), async_clock(ctx->id("$async$")) + crit_path(crit_path), slack_histogram(slack_histogram), net_crit(net_crit), + async_clock(ctx->id("$async$")) { } @@ -221,7 +225,7 @@ struct Timing } // Sanity check to ensure that all ports where fanins were recorded were indeed visited - if (!port_fanin.empty()) { + if (!port_fanin.empty() && !bool_or_default(ctx->settings, ctx->id("timing/ignoreLoops"), false)) { for (auto fanin : port_fanin) { NetInfo *net = fanin.first->net; if (net != nullptr) { @@ -263,8 +267,7 @@ struct Timing auto net_delay = net_delays ? ctx->getNetinfoRouteDelay(net, usr) : delay_t(); auto usr_arrival = net_arrival + net_delay; - if (portClass == TMG_REGISTER_INPUT || portClass == TMG_ENDPOINT || portClass == TMG_IGNORE || - portClass == TMG_CLOCK_INPUT) { + if (portClass == TMG_ENDPOINT || portClass == TMG_IGNORE || portClass == TMG_CLOCK_INPUT) { // Skip } else { auto budget_override = ctx->getBudgetOverride(net, usr, net_delay); @@ -410,7 +413,6 @@ struct Timing while (crit_net) { const PortInfo *crit_ipin = nullptr; delay_t max_arrival = std::numeric_limits<delay_t>::min(); - // Look at all input ports on its driving cell for (const auto &port : crit_net->driver.cell->ports) { if (port.second.type != PORT_IN || !port.second.net) @@ -424,14 +426,21 @@ struct Timing int port_clocks; TimingPortClass portClass = ctx->getPortTimingClass(crit_net->driver.cell, port.first, port_clocks); - if (portClass == TMG_REGISTER_INPUT || portClass == TMG_CLOCK_INPUT || - portClass == TMG_ENDPOINT || portClass == TMG_IGNORE) + if (portClass == TMG_CLOCK_INPUT || portClass == TMG_ENDPOINT || portClass == TMG_IGNORE || + portClass == TMG_REGISTER_INPUT) continue; - // And find the fanin net with the latest arrival time if (net_data.count(port.second.net) && net_data.at(port.second.net).count(crit_pair.first.start)) { - const auto net_arrival = net_data.at(port.second.net).at(crit_pair.first.start).max_arrival; + auto net_arrival = net_data.at(port.second.net).at(crit_pair.first.start).max_arrival; + if (net_delays) { + for (auto &user : port.second.net->users) + if (user.port == port.first && user.cell == crit_net->driver.cell) { + net_arrival += ctx->getNetinfoRouteDelay(port.second.net, user); + break; + } + } + net_arrival += comb_delay.maxDelay(); if (net_arrival > max_arrival) { max_arrival = net_arrival; crit_ipin = &port.second; @@ -441,7 +450,6 @@ struct Timing if (!crit_ipin) break; - // Now convert PortInfo* into a PortRef* for (auto &usr : crit_ipin->net->users) { if (usr.cell->name == crit_net->driver.cell->name && usr.port == crit_ipin->name) { @@ -454,6 +462,181 @@ struct Timing std::reverse(cp_ports.begin(), cp_ports.end()); } } + + if (net_crit) { + NPNR_ASSERT(crit_path); + // Go through in reverse topographical order to set required times + for (auto net : boost::adaptors::reverse(topographical_order)) { + if (!net_data.count(net)) + continue; + auto &nd_map = net_data.at(net); + for (auto &startdomain : nd_map) { + auto &nd = startdomain.second; + if (nd.false_startpoint) + continue; + if (startdomain.first.clock == async_clock) + continue; + if (nd.min_required.empty()) + nd.min_required.resize(net->users.size(), std::numeric_limits<delay_t>::max()); + delay_t net_min_required = std::numeric_limits<delay_t>::max(); + for (size_t i = 0; i < net->users.size(); i++) { + auto &usr = net->users.at(i); + auto net_delay = ctx->getNetinfoRouteDelay(net, usr); + int port_clocks; + TimingPortClass portClass = ctx->getPortTimingClass(usr.cell, usr.port, port_clocks); + if (portClass == TMG_REGISTER_INPUT || portClass == TMG_ENDPOINT) { + auto process_endpoint = [&](IdString clksig, ClockEdge edge, delay_t setup) { + delay_t period; + // Set default period + if (edge == startdomain.first.edge) { + period = clk_period; + } else { + period = clk_period / 2; + } + if (clksig != async_clock) { + if (ctx->nets.at(clksig)->clkconstr) { + if (edge == startdomain.first.edge) { + // same edge + period = ctx->nets.at(clksig)->clkconstr->period.minDelay(); + } else if (edge == RISING_EDGE) { + // falling -> rising + period = ctx->nets.at(clksig)->clkconstr->low.minDelay(); + } else if (edge == FALLING_EDGE) { + // rising -> falling + period = ctx->nets.at(clksig)->clkconstr->high.minDelay(); + } + } + } + nd.min_required.at(i) = std::min(period - setup, nd.min_required.at(i)); + }; + if (portClass == TMG_REGISTER_INPUT) { + for (int j = 0; j < port_clocks; j++) { + TimingClockingInfo clkInfo = ctx->getPortClockingInfo(usr.cell, usr.port, j); + const NetInfo *clknet = get_net_or_empty(usr.cell, clkInfo.clock_port); + IdString clksig = clknet ? clknet->name : async_clock; + process_endpoint(clksig, clknet ? clkInfo.edge : RISING_EDGE, + clkInfo.setup.maxDelay()); + } + } else { + process_endpoint(async_clock, RISING_EDGE, 0); + } + } + net_min_required = std::min(net_min_required, nd.min_required.at(i) - net_delay); + } + PortRef &drv = net->driver; + if (drv.cell == nullptr) + continue; + for (const auto &port : drv.cell->ports) { + if (port.second.type != PORT_IN || !port.second.net) + continue; + DelayInfo comb_delay; + bool is_path = ctx->getCellDelay(drv.cell, port.first, drv.port, comb_delay); + if (!is_path) + continue; + int cc; + auto pclass = ctx->getPortTimingClass(drv.cell, port.first, cc); + if (pclass != TMG_COMB_INPUT) + continue; + NetInfo *sink_net = port.second.net; + if (net_data.count(sink_net) && net_data.at(sink_net).count(startdomain.first)) { + auto &sink_nd = net_data.at(sink_net).at(startdomain.first); + if (sink_nd.min_required.empty()) + sink_nd.min_required.resize(sink_net->users.size(), + std::numeric_limits<delay_t>::max()); + for (size_t i = 0; i < sink_net->users.size(); i++) { + auto &user = sink_net->users.at(i); + if (user.cell == drv.cell && user.port == port.first) { + sink_nd.min_required.at(i) = net_min_required - comb_delay.maxDelay(); + break; + } + } + } + } + } + } + std::unordered_map<ClockEvent, delay_t> worst_slack; + + // Assign slack values + for (auto &net_entry : net_data) { + const NetInfo *net = net_entry.first; + for (auto &startdomain : net_entry.second) { + auto &nd = startdomain.second; + if (startdomain.first.clock == async_clock) + continue; + if (nd.min_required.empty()) + continue; + auto &nc = (*net_crit)[net->name]; + if (nc.slack.empty()) + nc.slack.resize(net->users.size(), std::numeric_limits<delay_t>::max()); +#if 0 + if (ctx->debug) + log_info("Net %s cd %s\n", net->name.c_str(ctx), startdomain.first.clock.c_str(ctx)); +#endif + for (size_t i = 0; i < net->users.size(); i++) { + delay_t slack = nd.min_required.at(i) - + (nd.max_arrival + ctx->getNetinfoRouteDelay(net, net->users.at(i))); +#if 0 + if (ctx->debug) + log_info(" user %s.%s required %.02fns arrival %.02f route %.02f slack %.02f\n", + net->users.at(i).cell->name.c_str(ctx), net->users.at(i).port.c_str(ctx), + ctx->getDelayNS(nd.min_required.at(i)), ctx->getDelayNS(nd.max_arrival), + ctx->getDelayNS(ctx->getNetinfoRouteDelay(net, net->users.at(i))), ctx->getDelayNS(slack)); +#endif + if (worst_slack.count(startdomain.first)) + worst_slack.at(startdomain.first) = std::min(worst_slack.at(startdomain.first), slack); + else + worst_slack[startdomain.first] = slack; + nc.slack.at(i) = slack; + } + if (ctx->debug) + log_break(); + } + } + // Assign criticality values + for (auto &net_entry : net_data) { + const NetInfo *net = net_entry.first; + for (auto &startdomain : net_entry.second) { + if (startdomain.first.clock == async_clock) + continue; + auto &nd = startdomain.second; + if (nd.min_required.empty()) + continue; + auto &nc = (*net_crit)[net->name]; + if (nc.slack.empty()) + continue; + if (nc.criticality.empty()) + nc.criticality.resize(net->users.size(), 0); + // Only consider intra-clock paths for criticality + if (!crit_path->count(ClockPair{startdomain.first, startdomain.first})) + continue; + delay_t dmax = crit_path->at(ClockPair{startdomain.first, startdomain.first}).path_delay; + for (size_t i = 0; i < net->users.size(); i++) { + float criticality = + 1.0f - ((float(nc.slack.at(i)) - float(worst_slack.at(startdomain.first))) / dmax); + nc.criticality.at(i) = std::min<double>(1.0, std::max<double>(0.0, criticality)); + } + nc.max_path_length = nd.max_path_length; + nc.cd_worst_slack = worst_slack.at(startdomain.first); + } + } +#if 0 + if (ctx->debug) { + for (auto &nc : *net_crit) { + NetInfo *net = ctx->nets.at(nc.first).get(); + log_info("Net %s maxlen %d worst_slack %.02fns: \n", nc.first.c_str(ctx), nc.second.max_path_length, + ctx->getDelayNS(nc.second.cd_worst_slack)); + if (!nc.second.criticality.empty() && !nc.second.slack.empty()) { + for (size_t i = 0; i < net->users.size(); i++) { + log_info(" user %s.%s slack %.02fns crit %.03f\n", net->users.at(i).cell->name.c_str(ctx), + net->users.at(i).port.c_str(ctx), ctx->getDelayNS(nc.second.slack.at(i)), + nc.second.criticality.at(i)); + } + } + log_break(); + } + } +#endif + } return min_slack; } @@ -601,6 +784,7 @@ void timing_analysis(Context *ctx, bool print_histogram, bool print_fmax, bool p int port_clocks; auto portClass = ctx->getPortTimingClass(front_driver.cell, front_driver.port, port_clocks); IdString last_port = front_driver.port; + int clock_start = -1; if (portClass == TMG_REGISTER_OUTPUT) { for (int i = 0; i < port_clocks; i++) { TimingClockingInfo clockInfo = ctx->getPortClockingInfo(front_driver.cell, front_driver.port, i); @@ -608,8 +792,7 @@ void timing_analysis(Context *ctx, bool print_histogram, bool print_fmax, bool p if (clknet != nullptr && clknet->name == clocks.start.clock && clockInfo.edge == clocks.start.edge) { last_port = clockInfo.clock_port; - total += clockInfo.clockToQ.maxDelay(); - logic_total += clockInfo.clockToQ.maxDelay(); + clock_start = i; break; } } @@ -623,11 +806,15 @@ void timing_analysis(Context *ctx, bool print_histogram, bool print_fmax, bool p auto &driver = net->driver; auto driver_cell = driver.cell; DelayInfo comb_delay; - if (last_port == driver.port) { + if (clock_start != -1) { + auto clockInfo = ctx->getPortClockingInfo(driver_cell, driver.port, clock_start); + comb_delay = clockInfo.clockToQ; + clock_start = -1; + } else if (last_port == driver.port) { // Case where we start with a STARTPOINT etc comb_delay = ctx->getDelayFromNS(0); } else { - ctx->getCellDelay(sink_cell, last_port, driver.port, comb_delay); + ctx->getCellDelay(driver_cell, last_port, driver.port, comb_delay); } total += comb_delay.maxDelay(); logic_total += comb_delay.maxDelay(); @@ -651,6 +838,10 @@ void timing_analysis(Context *ctx, bool print_histogram, bool print_fmax, bool p auto cursor = sink_wire; delay_t delay; while (driver_wire != cursor) { +#ifdef ARCH_ECP5 + if (net->is_global) + break; +#endif auto it = net->wires.find(cursor); assert(it != net->wires.end()); auto pip = it->second.pip; @@ -713,6 +904,9 @@ void timing_analysis(Context *ctx, bool print_histogram, bool print_fmax, bool p if (!warn_on_failure || passed) log_info("Max frequency for clock %*s'%s': %.02f MHz (%s at %.02f MHz)\n", width, "", clock_name.c_str(), clock_fmax[clock.first], passed ? "PASS" : "FAIL", target); + else if (bool_or_default(ctx->settings, ctx->id("timing/allowFail"), false)) + log_warning("Max frequency for clock %*s'%s': %.02f MHz (%s at %.02f MHz)\n", width, "", + clock_name.c_str(), clock_fmax[clock.first], passed ? "PASS" : "FAIL", target); else log_nonfatal_error("Max frequency for clock %*s'%s': %.02f MHz (%s at %.02f MHz)\n", width, "", clock_name.c_str(), clock_fmax[clock.first], passed ? "PASS" : "FAIL", target); @@ -744,8 +938,7 @@ void timing_analysis(Context *ctx, bool print_histogram, bool print_fmax, bool p unsigned bar_width = 60; auto min_slack = slack_histogram.begin()->first; auto max_slack = slack_histogram.rbegin()->first; - auto bin_size = std::max(1u, (max_slack - min_slack) / num_bins); - num_bins = std::min((max_slack - min_slack) / bin_size, num_bins) + 1; + auto bin_size = std::max<unsigned>(1, ceil((max_slack - min_slack + 1) / float(num_bins))); std::vector<unsigned> bins(num_bins); unsigned max_freq = 0; for (const auto &i : slack_histogram) { @@ -766,4 +959,12 @@ void timing_analysis(Context *ctx, bool print_histogram, bool print_fmax, bool p } } +void get_criticalities(Context *ctx, NetCriticalityMap *net_crit) +{ + CriticalPathMap crit_paths; + net_crit->clear(); + Timing timing(ctx, true, true, &crit_paths, nullptr, net_crit); + timing.walk_paths(); +} + NEXTPNR_NAMESPACE_END diff --git a/common/timing.h b/common/timing.h index 42f928dc..f1d18e8a 100644 --- a/common/timing.h +++ b/common/timing.h @@ -32,6 +32,19 @@ void assign_budget(Context *ctx, bool quiet = false); void timing_analysis(Context *ctx, bool slack_histogram = true, bool print_fmax = true, bool print_path = false, bool warn_on_failure = false); +// Data for the timing optimisation algorithm +struct NetCriticalityInfo +{ + // One each per user + std::vector<delay_t> slack; + std::vector<float> criticality; + unsigned max_path_length = 0; + delay_t cd_worst_slack = std::numeric_limits<delay_t>::max(); +}; + +typedef std::unordered_map<IdString, NetCriticalityInfo> NetCriticalityMap; +void get_criticalities(Context *ctx, NetCriticalityMap *net_crit); + NEXTPNR_NAMESPACE_END #endif diff --git a/common/timing_opt.cc b/common/timing_opt.cc new file mode 100644 index 00000000..898222ab --- /dev/null +++ b/common/timing_opt.cc @@ -0,0 +1,626 @@ +/* + * nextpnr -- Next Generation Place and Route + * + * Copyright (C) 2018 David Shah <david@symbioticeda.com> + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +/* + * Timing-optimised detailed placement algorithm using BFS of the neighbour graph created from cells + * on a critical path + * + * Based on "An Effective Timing-Driven Detailed Placement Algorithm for FPGAs" + * https://www.cerc.utexas.edu/utda/publications/C205.pdf + * + * Modifications made to deal with the smaller Bels that nextpnr uses instead of swapping whole tiles, + * and deal with the fact that not every cell on the crit path may be swappable. + */ + +#include "timing_opt.h" +#include <boost/range/adaptor/reversed.hpp> +#include <queue> +#include "nextpnr.h" +#include "timing.h" +#include "util.h" + +namespace std { + +template <> struct hash<std::pair<NEXTPNR_NAMESPACE_PREFIX IdString, NEXTPNR_NAMESPACE_PREFIX IdString>> +{ + std::size_t + operator()(const std::pair<NEXTPNR_NAMESPACE_PREFIX IdString, NEXTPNR_NAMESPACE_PREFIX IdString> &idp) const + noexcept + { + std::size_t seed = 0; + boost::hash_combine(seed, hash<NEXTPNR_NAMESPACE_PREFIX IdString>()(idp.first)); + boost::hash_combine(seed, hash<NEXTPNR_NAMESPACE_PREFIX IdString>()(idp.second)); + return seed; + } +}; + +template <> struct hash<std::pair<int, NEXTPNR_NAMESPACE_PREFIX BelId>> +{ + std::size_t operator()(const std::pair<int, NEXTPNR_NAMESPACE_PREFIX BelId> &idp) const noexcept + { + std::size_t seed = 0; + boost::hash_combine(seed, hash<int>()(idp.first)); + boost::hash_combine(seed, hash<NEXTPNR_NAMESPACE_PREFIX BelId>()(idp.second)); + return seed; + } +}; +#ifndef ARCH_GENERIC +template <> struct hash<std::pair<NEXTPNR_NAMESPACE_PREFIX IdString, NEXTPNR_NAMESPACE_PREFIX BelId>> +{ + std::size_t + operator()(const std::pair<NEXTPNR_NAMESPACE_PREFIX IdString, NEXTPNR_NAMESPACE_PREFIX BelId> &idp) const noexcept + { + std::size_t seed = 0; + boost::hash_combine(seed, hash<NEXTPNR_NAMESPACE_PREFIX IdString>()(idp.first)); + boost::hash_combine(seed, hash<NEXTPNR_NAMESPACE_PREFIX BelId>()(idp.second)); + return seed; + } +}; +#endif +} // namespace std + +NEXTPNR_NAMESPACE_BEGIN + +class TimingOptimiser +{ + public: + TimingOptimiser(Context *ctx, TimingOptCfg cfg) : ctx(ctx), cfg(cfg){}; + bool optimise() + { + log_info("Running timing-driven placement optimisation...\n"); + ctx->lock(); + if (ctx->verbose) + timing_analysis(ctx, false, true, false, false); + for (int i = 0; i < 30; i++) { + log_info(" Iteration %d...\n", i); + get_criticalities(ctx, &net_crit); + setup_delay_limits(); + auto crit_paths = find_crit_paths(0.98, 50000); + for (auto &path : crit_paths) + optimise_path(path); + if (ctx->verbose) + timing_analysis(ctx, false, true, false, false); + } + ctx->unlock(); + return true; + } + + private: + void setup_delay_limits() + { + max_net_delay.clear(); + for (auto net : sorted(ctx->nets)) { + NetInfo *ni = net.second; + for (auto usr : ni->users) { + max_net_delay[std::make_pair(usr.cell->name, usr.port)] = std::numeric_limits<delay_t>::max(); + } + if (!net_crit.count(net.first)) + continue; + auto &nc = net_crit.at(net.first); + if (nc.slack.empty()) + continue; + for (size_t i = 0; i < ni->users.size(); i++) { + auto &usr = ni->users.at(i); + delay_t net_delay = ctx->getNetinfoRouteDelay(ni, usr); + if (nc.max_path_length != 0) { + max_net_delay[std::make_pair(usr.cell->name, usr.port)] = + net_delay + ((nc.slack.at(i) - nc.cd_worst_slack) / 10); + } + } + } + } + + bool check_cell_delay_limits(CellInfo *cell) + { + for (const auto &port : cell->ports) { + int nc; + if (ctx->getPortTimingClass(cell, port.first, nc) == TMG_IGNORE) + continue; + NetInfo *net = port.second.net; + if (net == nullptr) + continue; + if (port.second.type == PORT_IN) { + if (net->driver.cell == nullptr || net->driver.cell->bel == BelId()) + continue; + for (auto user : net->users) { + if (user.cell == cell && user.port == port.first) { + if (ctx->predictDelay(net, user) > + 1.1 * max_net_delay.at(std::make_pair(cell->name, port.first))) + return false; + } + } + + } else if (port.second.type == PORT_OUT) { + for (auto user : net->users) { + // This could get expensive for high-fanout nets?? + BelId dstBel = user.cell->bel; + if (dstBel == BelId()) + continue; + if (ctx->predictDelay(net, user) > + 1.1 * max_net_delay.at(std::make_pair(user.cell->name, user.port))) { + + return false; + } + } + } + } + return true; + } + + BelId cell_swap_bel(CellInfo *cell, BelId newBel) + { + BelId oldBel = cell->bel; + if (oldBel == newBel) + return oldBel; + CellInfo *other_cell = ctx->getBoundBelCell(newBel); + NPNR_ASSERT(other_cell == nullptr || other_cell->belStrength <= STRENGTH_WEAK); + ctx->unbindBel(oldBel); + if (other_cell != nullptr) { + ctx->unbindBel(newBel); + ctx->bindBel(oldBel, other_cell, STRENGTH_WEAK); + } + ctx->bindBel(newBel, cell, STRENGTH_WEAK); + return oldBel; + } + + // Check that a series of moves are both legal and remain within maximum delay bounds + // Moves are specified as a vector of pairs <cell, oldBel> + bool acceptable_move(std::vector<std::pair<CellInfo *, BelId>> &move, bool check_delays = true) + { + for (auto &entry : move) { + if (!ctx->isBelLocationValid(entry.first->bel)) + return false; + if (!ctx->isBelLocationValid(entry.second)) + return false; + if (!check_delays) + continue; + if (!check_cell_delay_limits(entry.first)) + return false; + // We might have swapped another cell onto the original bel. Check this for max delay violations + // too + CellInfo *swapped = ctx->getBoundBelCell(entry.second); + if (swapped != nullptr && !check_cell_delay_limits(swapped)) + return false; + } + return true; + } + + int find_neighbours(CellInfo *cell, IdString prev_cell, int d, bool allow_swap) + { + BelId curr = cell->bel; + Loc curr_loc = ctx->getBelLocation(curr); + int found_count = 0; + cell_neighbour_bels[cell->name] = std::unordered_set<BelId>{}; + for (int dy = -d; dy <= d; dy++) { + for (int dx = -d; dx <= d; dx++) { + // Go through all the Bels at this location + // First, find all bels of the correct type that are either unbound or bound normally + // Strongly bound bels are ignored + // FIXME: This means that we cannot touch carry chains or similar relatively constrained macros + std::vector<BelId> free_bels_at_loc; + std::vector<BelId> bound_bels_at_loc; + for (auto bel : ctx->getBelsByTile(curr_loc.x + dx, curr_loc.y + dy)) { + if (ctx->getBelType(bel) != cell->type) + continue; + CellInfo *bound = ctx->getBoundBelCell(bel); + if (bound == nullptr) { + free_bels_at_loc.push_back(bel); + } else if (bound->belStrength <= STRENGTH_WEAK && bound->constr_parent == nullptr && + bound->constr_children.empty()) { + bound_bels_at_loc.push_back(bel); + } + } + BelId candidate; + + while (!free_bels_at_loc.empty() || !bound_bels_at_loc.empty()) { + BelId try_bel; + if (!free_bels_at_loc.empty()) { + int try_idx = ctx->rng(int(free_bels_at_loc.size())); + try_bel = free_bels_at_loc.at(try_idx); + free_bels_at_loc.erase(free_bels_at_loc.begin() + try_idx); + } else { + int try_idx = ctx->rng(int(bound_bels_at_loc.size())); + try_bel = bound_bels_at_loc.at(try_idx); + bound_bels_at_loc.erase(bound_bels_at_loc.begin() + try_idx); + } + if (bel_candidate_cells.count(try_bel) && !allow_swap) { + // Overlap is only allowed if it is with the previous cell (this is handled by removing those + // edges in the graph), or if allow_swap is true to deal with cases where overlap means few + // neighbours are identified + if (bel_candidate_cells.at(try_bel).size() > 1 || + (bel_candidate_cells.at(try_bel).size() == 1 && + *(bel_candidate_cells.at(try_bel).begin()) != prev_cell)) + continue; + } + // TODO: what else to check here? + candidate = try_bel; + break; + } + + if (candidate != BelId()) { + cell_neighbour_bels[cell->name].insert(candidate); + bel_candidate_cells[candidate].insert(cell->name); + // Work out if we need to delete any overlap + std::vector<IdString> overlap; + for (auto other : bel_candidate_cells[candidate]) + if (other != cell->name && other != prev_cell) + overlap.push_back(other); + if (overlap.size() > 0) + NPNR_ASSERT(allow_swap); + for (auto ov : overlap) { + bel_candidate_cells[candidate].erase(ov); + cell_neighbour_bels[ov].erase(candidate); + } + } + } + } + return found_count; + } + + std::vector<std::vector<PortRef *>> find_crit_paths(float crit_thresh, size_t max_count) + { + std::vector<std::vector<PortRef *>> crit_paths; + std::vector<std::pair<NetInfo *, int>> crit_nets; + std::vector<IdString> netnames; + std::transform(ctx->nets.begin(), ctx->nets.end(), std::back_inserter(netnames), + [](const std::pair<const IdString, std::unique_ptr<NetInfo>> &kv) { return kv.first; }); + ctx->sorted_shuffle(netnames); + for (auto net : netnames) { + if (crit_nets.size() >= max_count) + break; + if (!net_crit.count(net)) + continue; + auto crit_user = std::max_element(net_crit[net].criticality.begin(), net_crit[net].criticality.end()); + if (*crit_user > crit_thresh) + crit_nets.push_back( + std::make_pair(ctx->nets[net].get(), crit_user - net_crit[net].criticality.begin())); + } + + auto port_user_index = [](CellInfo *cell, PortInfo &port) -> size_t { + NPNR_ASSERT(port.net != nullptr); + for (size_t i = 0; i < port.net->users.size(); i++) { + auto &usr = port.net->users.at(i); + if (usr.cell == cell && usr.port == port.name) + return i; + } + NPNR_ASSERT_FALSE("port user not found on net"); + }; + std::unordered_set<PortRef *> used_ports; + + for (auto crit_net : crit_nets) { + + if (used_ports.count(&(crit_net.first->users.at(crit_net.second)))) + continue; + + std::deque<PortRef *> crit_path; + + // FIXME: This will fail badly on combinational loops + + // Iterate backwards following greatest criticality + NetInfo *back_cursor = crit_net.first; + while (back_cursor != nullptr) { + float max_crit = 0; + std::pair<NetInfo *, size_t> crit_sink{nullptr, 0}; + CellInfo *cell = back_cursor->driver.cell; + if (cell == nullptr) + break; + for (auto port : cell->ports) { + if (port.second.type != PORT_IN) + continue; + NetInfo *pn = port.second.net; + if (pn == nullptr) + continue; + if (!net_crit.count(pn->name) || net_crit.at(pn->name).criticality.empty()) + continue; + int ccount; + DelayInfo combDelay; + TimingPortClass tpclass = ctx->getPortTimingClass(cell, port.first, ccount); + if (tpclass != TMG_COMB_INPUT) + continue; + bool is_path = ctx->getCellDelay(cell, port.first, back_cursor->driver.port, combDelay); + if (!is_path) + continue; + size_t user_idx = port_user_index(cell, port.second); + float usr_crit = net_crit.at(pn->name).criticality.at(user_idx); + if (used_ports.count(&(pn->users.at(user_idx)))) + continue; + if (usr_crit >= max_crit) { + max_crit = usr_crit; + crit_sink = std::make_pair(pn, user_idx); + } + } + + if (crit_sink.first != nullptr) { + crit_path.push_front(&(crit_sink.first->users.at(crit_sink.second))); + used_ports.insert(&(crit_sink.first->users.at(crit_sink.second))); + } + back_cursor = crit_sink.first; + } + // Iterate forwards following greatest criticiality + PortRef *fwd_cursor = &(crit_net.first->users.at(crit_net.second)); + while (fwd_cursor != nullptr) { + crit_path.push_back(fwd_cursor); + float max_crit = 0; + std::pair<NetInfo *, size_t> crit_sink{nullptr, 0}; + CellInfo *cell = fwd_cursor->cell; + for (auto port : cell->ports) { + if (port.second.type != PORT_OUT) + continue; + NetInfo *pn = port.second.net; + if (pn == nullptr) + continue; + if (!net_crit.count(pn->name) || net_crit.at(pn->name).criticality.empty()) + continue; + int ccount; + DelayInfo combDelay; + TimingPortClass tpclass = ctx->getPortTimingClass(cell, port.first, ccount); + if (tpclass != TMG_COMB_OUTPUT && tpclass != TMG_REGISTER_OUTPUT) + continue; + bool is_path = ctx->getCellDelay(cell, fwd_cursor->port, port.first, combDelay); + if (!is_path) + continue; + auto &crits = net_crit.at(pn->name).criticality; + for (size_t i = 0; i < crits.size(); i++) { + if (used_ports.count(&(pn->users.at(i)))) + continue; + if (crits.at(i) >= max_crit) { + max_crit = crits.at(i); + crit_sink = std::make_pair(pn, i); + } + } + } + if (crit_sink.first != nullptr) { + fwd_cursor = &(crit_sink.first->users.at(crit_sink.second)); + used_ports.insert(&(crit_sink.first->users.at(crit_sink.second))); + } else { + fwd_cursor = nullptr; + } + } + + std::vector<PortRef *> crit_path_vec; + std::copy(crit_path.begin(), crit_path.end(), std::back_inserter(crit_path_vec)); + crit_paths.push_back(crit_path_vec); + } + + return crit_paths; + } + + void optimise_path(std::vector<PortRef *> &path) + { + path_cells.clear(); + cell_neighbour_bels.clear(); + bel_candidate_cells.clear(); + if (ctx->debug) + log_info("Optimising the following path: \n"); + + auto front_port = path.front(); + NetInfo *front_net = front_port->cell->ports.at(front_port->port).net; + if (front_net != nullptr && front_net->driver.cell != nullptr) { + auto front_cell = front_net->driver.cell; + if (front_cell->belStrength <= STRENGTH_WEAK && cfg.cellTypes.count(front_cell->type) && + front_cell->constr_parent == nullptr && front_cell->constr_children.empty()) { + path_cells.push_back(front_cell->name); + } + } + + for (auto port : path) { + if (ctx->debug) { + float crit = 0; + NetInfo *pn = port->cell->ports.at(port->port).net; + if (net_crit.count(pn->name) && !net_crit.at(pn->name).criticality.empty()) + for (size_t i = 0; i < pn->users.size(); i++) + if (pn->users.at(i).cell == port->cell && pn->users.at(i).port == port->port) + crit = net_crit.at(pn->name).criticality.at(i); + log_info(" %s.%s at %s crit %0.02f\n", port->cell->name.c_str(ctx), port->port.c_str(ctx), + ctx->getBelName(port->cell->bel).c_str(ctx), crit); + } + if (std::find(path_cells.begin(), path_cells.end(), port->cell->name) != path_cells.end()) + continue; + if (port->cell->belStrength > STRENGTH_WEAK || !cfg.cellTypes.count(port->cell->type) || + port->cell->constr_parent != nullptr || !port->cell->constr_children.empty()) + continue; + if (ctx->debug) + log_info(" can move\n"); + path_cells.push_back(port->cell->name); + } + + if (path_cells.size() < 2) { + if (ctx->debug) { + log_info("Too few moveable cells; skipping path\n"); + log_break(); + } + + return; + } + + // Calculate original delay before touching anything + delay_t original_delay = 0; + + for (size_t i = 0; i < path.size(); i++) { + NetInfo *pn = path.at(i)->cell->ports.at(path.at(i)->port).net; + for (size_t j = 0; j < pn->users.size(); j++) { + auto &usr = pn->users.at(j); + if (usr.cell == path.at(i)->cell && usr.port == path.at(i)->port) { + original_delay += ctx->predictDelay(pn, usr); + break; + } + } + } + + IdString last_cell; + const int d = 2; // FIXME: how to best determine d + for (auto cell : path_cells) { + // FIXME: when should we allow swapping due to a lack of candidates + find_neighbours(ctx->cells[cell].get(), last_cell, d, false); + last_cell = cell; + } + + if (ctx->debug) { + for (auto cell : path_cells) { + log_info("Candidate neighbours for %s (%s):\n", cell.c_str(ctx), + ctx->getBelName(ctx->cells[cell]->bel).c_str(ctx)); + for (auto neigh : cell_neighbour_bels.at(cell)) { + log_info(" %s\n", ctx->getBelName(neigh).c_str(ctx)); + } + } + } + + // Actual BFS path optimisation algorithm + std::unordered_map<IdString, std::unordered_map<BelId, delay_t>> cumul_costs; + std::unordered_map<std::pair<IdString, BelId>, std::pair<IdString, BelId>> backtrace; + std::queue<std::pair<int, BelId>> visit; + std::unordered_set<std::pair<int, BelId>> to_visit; + + for (auto startbel : cell_neighbour_bels[path_cells.front()]) { + // Swap for legality check + CellInfo *cell = ctx->cells.at(path_cells.front()).get(); + BelId origBel = cell_swap_bel(cell, startbel); + std::vector<std::pair<CellInfo *, BelId>> move{std::make_pair(cell, origBel)}; + if (acceptable_move(move)) { + auto entry = std::make_pair(0, startbel); + visit.push(entry); + cumul_costs[path_cells.front()][startbel] = 0; + } + // Swap back + cell_swap_bel(cell, origBel); + } + + while (!visit.empty()) { + auto entry = visit.front(); + visit.pop(); + auto cellname = path_cells.at(entry.first); + if (entry.first == int(path_cells.size()) - 1) + continue; + std::vector<std::pair<CellInfo *, BelId>> move; + // Apply the entire backtrace for accurate legality and delay checks + // This is probably pretty expensive (but also probably pales in comparison to the number of swaps + // SA will make...) + std::vector<std::pair<IdString, BelId>> route_to_entry; + auto cursor = std::make_pair(cellname, entry.second); + route_to_entry.push_back(cursor); + while (backtrace.count(cursor)) { + cursor = backtrace.at(cursor); + route_to_entry.push_back(cursor); + } + for (auto rt_entry : boost::adaptors::reverse(route_to_entry)) { + CellInfo *cell = ctx->cells.at(rt_entry.first).get(); + BelId origBel = cell_swap_bel(cell, rt_entry.second); + move.push_back(std::make_pair(cell, origBel)); + } + + // Have a look at where we can travel from here + for (auto neighbour : cell_neighbour_bels.at(path_cells.at(entry.first + 1))) { + // Edges between overlapping bels are deleted + if (neighbour == entry.second) + continue; + // Experimentally swap the next path cell onto the neighbour bel we are trying + IdString ncname = path_cells.at(entry.first + 1); + CellInfo *next_cell = ctx->cells.at(ncname).get(); + BelId origBel = cell_swap_bel(next_cell, neighbour); + move.push_back(std::make_pair(next_cell, origBel)); + + delay_t total_delay = 0; + + for (size_t i = 0; i < path.size(); i++) { + NetInfo *pn = path.at(i)->cell->ports.at(path.at(i)->port).net; + for (size_t j = 0; j < pn->users.size(); j++) { + auto &usr = pn->users.at(j); + if (usr.cell == path.at(i)->cell && usr.port == path.at(i)->port) { + total_delay += ctx->predictDelay(pn, usr); + break; + } + } + if (path.at(i)->cell == next_cell) + break; + } + + // First, check if the move is actually worthwhile from a delay point of view before the expensive + // legality check + if (!cumul_costs.count(ncname) || !cumul_costs.at(ncname).count(neighbour) || + cumul_costs.at(ncname).at(neighbour) > total_delay) { + // Now check that the swaps we have made to get here are legal and meet max delay requirements + if (acceptable_move(move)) { + cumul_costs[ncname][neighbour] = total_delay; + backtrace[std::make_pair(ncname, neighbour)] = std::make_pair(cellname, entry.second); + if (!to_visit.count(std::make_pair(entry.first + 1, neighbour))) + visit.push(std::make_pair(entry.first + 1, neighbour)); + } + } + // Revert the experimental swap + cell_swap_bel(move.back().first, move.back().second); + move.pop_back(); + } + + // Revert move by swapping cells back to their original order + // Execute swaps in reverse order to how we made them originally + for (auto move_entry : boost::adaptors::reverse(move)) { + cell_swap_bel(move_entry.first, move_entry.second); + } + } + + // Did we find a solution?? + if (cumul_costs.count(path_cells.back())) { + // Find the end position with the lowest total delay + auto &end_options = cumul_costs.at(path_cells.back()); + auto lowest = std::min_element(end_options.begin(), end_options.end(), + [](const std::pair<BelId, delay_t> &a, const std::pair<BelId, delay_t> &b) { + return a.second < b.second; + }); + NPNR_ASSERT(lowest != end_options.end()); + + std::vector<std::pair<IdString, BelId>> route_to_solution; + auto cursor = std::make_pair(path_cells.back(), lowest->first); + route_to_solution.push_back(cursor); + while (backtrace.count(cursor)) { + cursor = backtrace.at(cursor); + route_to_solution.push_back(cursor); + } + if (ctx->debug) + log_info("Found a solution with cost %.02f ns (existing path %.02f ns)\n", + ctx->getDelayNS(lowest->second), ctx->getDelayNS(original_delay)); + for (auto rt_entry : boost::adaptors::reverse(route_to_solution)) { + CellInfo *cell = ctx->cells.at(rt_entry.first).get(); + cell_swap_bel(cell, rt_entry.second); + if (ctx->debug) + log_info(" %s at %s\n", rt_entry.first.c_str(ctx), ctx->getBelName(rt_entry.second).c_str(ctx)); + } + + } else { + if (ctx->debug) + log_info("Solution was not found\n"); + } + if (ctx->debug) + log_break(); + } + + // Current candidate Bels for cells (linked in both direction> + std::vector<IdString> path_cells; + std::unordered_map<IdString, std::unordered_set<BelId>> cell_neighbour_bels; + std::unordered_map<BelId, std::unordered_set<IdString>> bel_candidate_cells; + // Map cell ports to net delay limit + std::unordered_map<std::pair<IdString, IdString>, delay_t> max_net_delay; + // Criticality data from timing analysis + NetCriticalityMap net_crit; + Context *ctx; + TimingOptCfg cfg; +}; + +bool timing_opt(Context *ctx, TimingOptCfg cfg) { return TimingOptimiser(ctx, cfg).optimise(); } + +NEXTPNR_NAMESPACE_END diff --git a/tests/generic/main.cc b/common/timing_opt.h index a2634711..ceb35c71 100644 --- a/tests/generic/main.cc +++ b/common/timing_opt.h @@ -1,7 +1,7 @@ /* * nextpnr -- Next Generation Place and Route * - * Copyright (C) 2018 Miodrag Milanovic <miodrag@symbioticeda.com> + * Copyright (C) 2018 David Shah <david@symbioticeda.com> * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above @@ -17,12 +17,21 @@ * */ -#include "gtest/gtest.h" +#include "nextpnr.h" +#include "settings.h" -#include <vector> +NEXTPNR_NAMESPACE_BEGIN -int main(int argc, char **argv) +struct TimingOptCfg : public Settings { - ::testing::InitGoogleTest(&argc, argv); - return RUN_ALL_TESTS(); -} + TimingOptCfg(Context *ctx) : Settings(ctx) {} + + // The timing optimiser will *only* optimise cells of these types + // Normally these would only be logic cells (or tiles if applicable), the algorithm makes little sense + // for other cell types + std::unordered_set<IdString> cellTypes; +}; + +extern bool timing_opt(Context *ctx, TimingOptCfg cfg); + +NEXTPNR_NAMESPACE_END diff --git a/docs/archapi.md b/docs/archapi.md index 3c938865..6e59ecdb 100644 --- a/docs/archapi.md +++ b/docs/archapi.md @@ -490,3 +490,14 @@ a certain number of different clock signals allowed for a group of bels. Returns true if a bell in the current configuration is valid, i.e. if `isValidBelForCell()` would return true for the current mapping. + + +### static const std::string defaultPlacer + +Name of the default placement algorithm for the architecture, if +`--placer` isn't specified on the command line. + +### static const std::vector\<std::string\> availablePlacers + +Name of available placer algorithms for the architecture, used +to provide help for and validate `--placer`.
\ No newline at end of file diff --git a/docs/generic.md b/docs/generic.md new file mode 100644 index 00000000..d6ddbfb6 --- /dev/null +++ b/docs/generic.md @@ -0,0 +1,119 @@ +# nextpnr Generic Architecture + +Instead of implementing the [C++ API](archapi.md), you can programmatically +build up a description of an FPGA using the generic architecture and the +Python API. + +A basic packer is provided that supports LUTs, flipflops and IO buffer insertion. +Packing could also be implemented using the Python API. + +At present there is no support for cell timing in the generic architecture. This +will be worked on in the future. + +## Python API + +All identifiers (`IdString`) are automatically converted to +and from a Python string, so no manual conversion is required. + +Argument names are included in the Python bindings, +so named arguments may be used. + +### void addWire(IdString name, IdString type, int x, int y); + +Adds a wire with a name, type (for user purposes only, ignored by all nextpnr code other than the UI) to the FPGA description. x and y give a nominal location of the wire for delay estimation purposes. Delay estimates are important for router performance (as the router uses an A* type algorithm), even if timing is not of importance. + +### addPip(IdString name, IdString type, IdString srcWire, IdString dstWire, DelayInfo delay, Loc loc); + +Adds a pip (programmable connection between two named wires). Pip delays that correspond to delay estimates are important for router performance (as the router uses an A* type algorithm), even if timing is otherwise not of importance. + +Loc is constructed using `Loc(x, y, z)`. 'z' for pips is only important if region constraints (e.g. for partial reconfiguration regions) are used. + +### void addAlias(IdString name, IdString type, IdString srcWire, IdString dstWire, DelayInfo delay); + +Adds a wire alias (fixed connection between two named wires). Alias delays that correspond to delay estimates are important for router performance (as the router uses an A* type algorithm), even if timing is otherwise not of importance. + +### void addBel(IdString name, IdString type, Loc loc, bool gb); + +Adds a bel to the FPGA description. Bel type should match the type of cells in the netlist that are placed at this bel (see below for information on special bel types supported by the packer). Loc is constructed using `Loc(x, y, z)` and must be unique. + +### void addBelInput(IdString bel, IdString name, IdString wire); +### void addBelOutput(IdString bel, IdString name, IdString wire); +### void addBelInout(IdString bel, IdString name, IdString wire); + +Adds an input, output or inout pin to a bel, with an associated wire. Note that both `bel` and `wire` must have been created before calling this function. + +### void addGroupBel(IdString group, IdString bel); +### void addGroupWire(IdString group, IdString wire); +### void addGroupPip(IdString group, IdString pip); +### void addGroupGroup(IdString group, IdString grp); + +Add a bel, wire, pip or subgroup to a group, which will be created if it doesn't already exist. Groups are purely for visual presentation purposes in the user interface and are not used by any place-and-route algorithms. + +### void addDecalGraphic(DecalId decal, const GraphicElement &graphic); + +Add a graphic element to a _decal_, a reusable drawing that may be used to represent multiple wires, pips, bels or groups in the UI (with different offsets). The decal will be created if it doesn't already exist + +### void setWireDecal(WireId wire, DecalXY decalxy); +### void setPipDecal(PipId pip, DecalXY decalxy); +### void setBelDecal(BelId bel, DecalXY decalxy); +### void setGroupDecal(GroupId group, DecalXY decalxy); + +Sets the decal ID and offset for a wire, bel, pip or group in the UI. + +### void setWireAttr(IdString wire, IdString key, const std::string &value); +### void setPipAttr(IdString pip, IdString key, const std::string &value); +### void setBelAttr(IdString bel, IdString key, const std::string &value); + +Sets an attribute on a wire, pip or bel. Attributes are displayed in the tree view in the UI, but have no bearing on place-and-route itself. + +### void setLutK(int K); + +Sets the number of input pins a LUT in the architecture has. Only affects the generic packer, if a custom packer or no packer is used this value has no effect - there is no need for the architecture to have LUTs at all in this case. + +### void setDelayScaling(double scale, double offset); + +Set the linear scaling vs distance and fixed offset (both values in nanoseconds) for routing delay estimates. + +### void addCellTimingClock(IdString cell, IdString port); + +Set the timing class of a port on a particular cell to a clock input. + +_NOTE: All cell timing functions apply to an individual named cell and not a cell type. This is because +cell-specific configuration might affect timing, e.g. whether or not the register is used for a slice._ + +### void addCellTimingDelay(IdString cell, IdString fromPort, IdString toPort, DelayInfo delay); + +Specify the combinational delay between two ports of a cell, and set the timing class of + those ports as combinational input/output. + +### void addCellTimingSetupHold(IdString cell, IdString port, IdString clock, DelayInfo setup, DelayInfo hold); + +Specify setup and hold timings for a port of a cell, and set the timing class of that port as register input. + +### void addCellTimingClockToOut(IdString cell, IdString port, IdString clock, DelayInfo clktoq); + +Specify clock-to-out time for a port of a cell, and set the timing class of that port as register output. + +## Generic Packer + +The generic packer combines K-input LUTs (`LUT` cells) and simple D-type flip flops (`DFF` cells) (posedge clock only, no set/reset or enable) into a `GENERIC_SLICE` cell. It also inserts `GENERIC_IOB`s onto any top level IO pins without an IO buffer. + +Thus, the architecture should provide bels with the following ports in order to use the generic packer: + + - `GENERIC_SLICE` bels with `CLK` input, `I[0]` .. `I[K-1]` LUT inputs and `Q` LUT/FF output (N.B. both LUT and FF outputs are not available at the same time) + - `GENERIC_IOB` bels with `I` output buffer input, `EN` output enable input, and `O` input buffer output. + +See [prims.v](../generic/synth/prims.v) for Verilog simulation models for all these cells. + +[synth_generic.tcl](../generic/synth/synth_generic.tcl) can be used with Yosys to perform synthesis to the generic `LUT` and `DFF` cells which the generic packer supports. Invoke it using `tcl synth_generic.tcl K out.json` where _K_ is the number of LUT inputs and _out.json_ the name of the JSON file to write. + +## Validity Checks + +The following constraints are enforced by the generic architecture during placement. + + - `GENERIC_SLICE` bels may only have one clock signal per tile (xy location) + - If the `PACK_GROUP` attribute is set to a non-zero value on cells, then only cells with the same `PACK_GROUP` attribute (or `PACK_GROUP` negative or unset) may share a tile. This could be set by the Python API or during synthesis. + +## Implementation Example + +An artificial, procedural architecture is included in the [generic/examples](../generic/examples) folder. [simple.py](../generic/examples/simple.py) sets up the architecture, and [report.py](../generic/examples/report.py) saves post-place-and-route design to a text file (in place of bitstream generation). [simple.sh](../generic/examples/simple.sh) can be used to synthesise and place-and-route a simple blinky for this architecture. diff --git a/ecp5/arch.cc b/ecp5/arch.cc index 719426ab..9da8abdf 100644 --- a/ecp5/arch.cc +++ b/ecp5/arch.cc @@ -19,6 +19,7 @@ */ #include <algorithm> +#include <boost/iostreams/device/mapped_file.hpp> #include <boost/range/adaptor/reversed.hpp> #include <cmath> #include <cstring> @@ -27,6 +28,7 @@ #include "log.h" #include "nextpnr.h" #include "placer1.h" +#include "placer_heap.h" #include "router1.h" #include "timing.h" #include "util.h" @@ -63,11 +65,37 @@ static const ChipInfoPOD *get_chip_info(const RelPtr<ChipInfoPOD> *ptr) { return void load_chipdb(); #endif +#if defined(EXTERNAL_CHIPDB_ROOT) +const char *chipdb_blob_25k = nullptr; +const char *chipdb_blob_45k = nullptr; +const char *chipdb_blob_85k = nullptr; + +boost::iostreams::mapped_file_source blob_files[3]; + +const char *mmap_file(int index, const char *filename) +{ + try { + blob_files[index].open(filename); + if (!blob_files[index].is_open()) + log_error("Unable to read chipdb %s\n", filename); + return (const char *)blob_files[index].data(); + } catch (...) { + log_error("Unable to read chipdb %s\n", filename); + } +} + +void load_chipdb() +{ + chipdb_blob_25k = mmap_file(0, EXTERNAL_CHIPDB_ROOT "/ecp5/chipdb-25k.bin"); + chipdb_blob_45k = mmap_file(1, EXTERNAL_CHIPDB_ROOT "/ecp5/chipdb-45k.bin"); + chipdb_blob_85k = mmap_file(2, EXTERNAL_CHIPDB_ROOT "/ecp5/chipdb-85k.bin"); +} +#endif //#define LFE5U_45F_ONLY Arch::Arch(ArchArgs args) : args(args) { -#if defined(_MSC_VER) +#if defined(_MSC_VER) || defined(EXTERNAL_CHIPDB_ROOT) load_chipdb(); #endif #ifdef LFE5U_45F_ONLY @@ -400,23 +428,104 @@ BelId Arch::getBelByLocation(Loc loc) const delay_t Arch::estimateDelay(WireId src, WireId dst) const { - return (240 - 20 * args.speed) * (abs(src.location.x - dst.location.x) + abs(src.location.y - dst.location.y)); + WireId cursor = dst; + + int num_uh = locInfo(dst)->wire_data[dst.index].num_uphill; + if (num_uh < 6) { + for (auto uh : getPipsUphill(dst)) { + if (getPipSrcWire(uh) == src) + return getPipDelay(uh).maxDelay(); + } + } + + auto est_location = [&](WireId w) -> std::pair<int, int> { + const auto &wire = locInfo(w)->wire_data[w.index]; + if (wire.num_bel_pins > 0) { + return std::make_pair(w.location.x + wire.bel_pins[0].rel_bel_loc.x, + w.location.y + wire.bel_pins[0].rel_bel_loc.y); + } else if (wire.num_downhill > 0) { + return std::make_pair(w.location.x + wire.pips_downhill[0].rel_loc.x, + w.location.y + wire.pips_downhill[0].rel_loc.y); + } else if (wire.num_uphill > 0) { + return std::make_pair(w.location.x + wire.pips_uphill[0].rel_loc.x, + w.location.y + wire.pips_uphill[0].rel_loc.y); + } else { + return std::make_pair(int(w.location.x), int(w.location.y)); + } + }; + + auto src_loc = est_location(src), dst_loc = est_location(dst); + + int dx = abs(src_loc.first - dst_loc.first), dy = abs(src_loc.second - dst_loc.second); + + return (130 - 25 * args.speed) * + (6 + std::max(dx - 5, 0) + std::max(dy - 5, 0) + 2 * (std::min(dx, 5) + std::min(dy, 5))); } delay_t Arch::predictDelay(const NetInfo *net_info, const PortRef &sink) const { const auto &driver = net_info->driver; + if ((driver.port == id_FCO && sink.port == id_FCI) || sink.port == id_FXA || sink.port == id_FXB) + return 0; auto driver_loc = getBelLocation(driver.cell->bel); auto sink_loc = getBelLocation(sink.cell->bel); + // Encourage use of direct interconnect + if (driver_loc.x == sink_loc.x && driver_loc.y == sink_loc.y) { + if ((sink.port == id_A0 || sink.port == id_A1) && (driver.port == id_F1) && + (driver_loc.z == 2 || driver_loc.z == 3)) + return 0; + if ((sink.port == id_B0 || sink.port == id_B1) && (driver.port == id_F1) && + (driver_loc.z == 0 || driver_loc.z == 1)) + return 0; + if ((sink.port == id_C0 || sink.port == id_C1) && (driver.port == id_F0) && + (driver_loc.z == 2 || driver_loc.z == 3)) + return 0; + if ((sink.port == id_D0 || sink.port == id_D1) && (driver.port == id_F0) && + (driver_loc.z == 0 || driver_loc.z == 1)) + return 0; + } + + int dx = abs(driver_loc.x - sink_loc.x), dy = abs(driver_loc.y - sink_loc.y); - return (240 - 20 * args.speed) * (abs(driver_loc.x - sink_loc.x) + abs(driver_loc.y - sink_loc.y)); + return (130 - 25 * args.speed) * + (6 + std::max(dx - 5, 0) + std::max(dy - 5, 0) + 2 * (std::min(dx, 5) + std::min(dy, 5))); } -bool Arch::getBudgetOverride(const NetInfo *net_info, const PortRef &sink, delay_t &budget) const { return false; } +bool Arch::getBudgetOverride(const NetInfo *net_info, const PortRef &sink, delay_t &budget) const +{ + if (net_info->driver.port == id_FCO && sink.port == id_FCI) { + budget = 0; + return true; + } else if (sink.port == id_FXA || sink.port == id_FXB) { + budget = 0; + return true; + } else { + return false; + } +} // ----------------------------------------------------------------------- -bool Arch::place() { return placer1(getCtx(), Placer1Cfg(getCtx())); } +bool Arch::place() +{ + std::string placer = str_or_default(settings, id("placer"), defaultPlacer); + + if (placer == "heap") { + PlacerHeapCfg cfg(getCtx()); + cfg.criticalityExponent = 7; + cfg.ioBufTypes.insert(id_TRELLIS_IO); + if (!placer_heap(getCtx(), cfg)) + return false; + } else if (placer == "sa") { + if (!placer1(getCtx(), Placer1Cfg(getCtx()))) + return false; + } else { + log_error("ECP5 architecture does not support placer '%s'\n", placer.c_str()); + } + + permute_luts(); + return true; +} bool Arch::route() { @@ -511,6 +620,11 @@ DecalXY Arch::getGroupDecal(GroupId pip) const { return {}; }; bool Arch::getDelayFromTimingDatabase(IdString tctype, IdString from, IdString to, DelayInfo &delay) const { + auto fnd_dk = celldelay_cache.find({tctype, from, to}); + if (fnd_dk != celldelay_cache.end()) { + delay = fnd_dk->second.second; + return fnd_dk->second.first; + } for (int i = 0; i < speed_grade->num_cell_timings; i++) { const auto &tc = speed_grade->cell_timings[i]; if (tc.cell_type == tctype.index) { @@ -519,9 +633,11 @@ bool Arch::getDelayFromTimingDatabase(IdString tctype, IdString from, IdString t if (dly.from_port == from.index && dly.to_port == to.index) { delay.max_delay = dly.max_delay; delay.min_delay = dly.min_delay; + celldelay_cache[{tctype, from, to}] = std::make_pair(true, delay); return true; } } + celldelay_cache[{tctype, from, to}] = std::make_pair(false, DelayInfo()); return false; } } @@ -551,10 +667,9 @@ void Arch::getSetupHoldFromTimingDatabase(IdString tctype, IdString clock, IdStr bool Arch::getCellDelay(const CellInfo *cell, IdString fromPort, IdString toPort, DelayInfo &delay) const { - // Data for -8 grade if (cell->type == id_TRELLIS_SLICE) { - bool has_carry = str_or_default(cell->params, id("MODE"), "LOGIC") == "CCU2"; + bool has_carry = cell->sliceInfo.is_carry; if (fromPort == id_A0 || fromPort == id_B0 || fromPort == id_C0 || fromPort == id_D0 || fromPort == id_A1 || fromPort == id_B1 || fromPort == id_C1 || fromPort == id_D1 || fromPort == id_M0 || fromPort == id_M1 || fromPort == id_FXA || fromPort == id_FXB || fromPort == id_FCI) { @@ -579,6 +694,8 @@ bool Arch::getCellDelay(const CellInfo *cell, IdString fromPort, IdString toPort return false; } else if (cell->type == id_DP16KD) { return false; + } else if (cell->type == id_IOLOGIC || cell->type == id_SIOLOGIC) { + return false; } else { return false; } @@ -589,7 +706,7 @@ TimingPortClass Arch::getPortTimingClass(const CellInfo *cell, IdString port, in auto disconnected = [cell](IdString p) { return !cell->ports.count(p) || cell->ports.at(p).net == nullptr; }; clockInfoCount = 0; if (cell->type == id_TRELLIS_SLICE) { - int sd0 = int_or_default(cell->params, id("REG0_SD"), 0), sd1 = int_or_default(cell->params, id("REG1_SD"), 0); + int sd0 = cell->sliceInfo.sd0, sd1 = cell->sliceInfo.sd1; if (port == id_CLK || port == id_WCK) return TMG_CLOCK_INPUT; if (port == id_A0 || port == id_A1 || port == id_B0 || port == id_B1 || port == id_C0 || port == id_C1 || @@ -669,6 +786,56 @@ TimingPortClass Arch::getPortTimingClass(const CellInfo *cell, IdString port, in return (cell->ports.at(port).type == PORT_OUT) ? TMG_REGISTER_OUTPUT : TMG_REGISTER_INPUT; } return TMG_IGNORE; + } else if (cell->type == id_IOLOGIC || cell->type == id_SIOLOGIC) { + if (port == id_CLK || port == id_ECLK) { + return TMG_CLOCK_INPUT; + } else if (port == id_IOLDO || port == id_IOLDOI || port == id_IOLDOD || port == id_IOLTO || port == id_PADDI || + port == id_DQSR90 || port == id_DQSW || port == id_DQSW270) { + return TMG_IGNORE; + } else { + clockInfoCount = 1; + return (cell->ports.at(port).type == PORT_OUT) ? TMG_REGISTER_OUTPUT : TMG_REGISTER_INPUT; + } + } else if (cell->type == id_DTR || cell->type == id_USRMCLK || cell->type == id_SEDGA || cell->type == id_GSR || + cell->type == id_JTAGG) { + return (cell->ports.at(port).type == PORT_OUT) ? TMG_STARTPOINT : TMG_ENDPOINT; + } else if (cell->type == id_OSCG) { + if (port == id_OSC) + return TMG_GEN_CLOCK; + else + return TMG_IGNORE; + } else if (cell->type == id_CLKDIVF) { + if (port == id_CLKI) + return TMG_CLOCK_INPUT; + else if (port == id_RST || port == id_ALIGNWD) + return TMG_ENDPOINT; + else if (port == id_CDIVX) + return TMG_GEN_CLOCK; + else + NPNR_ASSERT_FALSE("bad clkdiv port"); + } else if (cell->type == id_DQSBUFM) { + if (port == id_READ0 || port == id_READ1) { + clockInfoCount = 1; + return TMG_REGISTER_INPUT; + } else if (port == id_DATAVALID) { + clockInfoCount = 1; + return TMG_REGISTER_OUTPUT; + } else if (port == id_SCLK || port == id_ECLK || port == id_DQSI) { + return TMG_CLOCK_INPUT; + } else if (port == id_DQSR90 || port == id_DQSW || port == id_DQSW270) { + return TMG_GEN_CLOCK; + } + return (cell->ports.at(port).type == PORT_OUT) ? TMG_STARTPOINT : TMG_ENDPOINT; + } else if (cell->type == id_DDRDLL) { + if (port == id_CLK) + return TMG_CLOCK_INPUT; + return (cell->ports.at(port).type == PORT_OUT) ? TMG_STARTPOINT : TMG_ENDPOINT; + } else if (cell->type == id_TRELLIS_ECLKBUF) { + return (cell->ports.at(port).type == PORT_OUT) ? TMG_COMB_OUTPUT : TMG_COMB_INPUT; + } else if (cell->type == id_ECLKSYNCB) { + if (cell->ports.at(port).name == id_STOP) + return TMG_ENDPOINT; + return (cell->ports.at(port).type == PORT_OUT) ? TMG_COMB_OUTPUT : TMG_COMB_INPUT; } else { log_error("cell type '%s' is unsupported (instantiated as '%s')\n", cell->type.c_str(this), cell->name.c_str(this)); @@ -682,8 +849,7 @@ TimingClockingInfo Arch::getPortClockingInfo(const CellInfo *cell, IdString port info.hold = getDelayFromNS(0); info.clockToQ = getDelayFromNS(0); if (cell->type == id_TRELLIS_SLICE) { - int sd0 = int_or_default(cell->params, id("REG0_SD"), 0), sd1 = int_or_default(cell->params, id("REG1_SD"), 0); - + int sd0 = cell->sliceInfo.sd0, sd1 = cell->sliceInfo.sd1; if (port == id_WD0 || port == id_WD1 || port == id_WAD0 || port == id_WAD1 || port == id_WAD2 || port == id_WAD3 || port == id_WRE) { info.edge = RISING_EDGE; @@ -744,6 +910,24 @@ TimingClockingInfo Arch::getPortClockingInfo(const CellInfo *cell, IdString port info.setup = getDelayFromNS(1); info.hold = getDelayFromNS(0); } + } else if (cell->type == id_IOLOGIC || cell->type == id_SIOLOGIC) { + info.clock_port = id_CLK; + if (cell->ports.at(port).type == PORT_OUT) { + info.clockToQ = getDelayFromNS(0.5); + } else { + info.setup = getDelayFromNS(0.1); + info.hold = getDelayFromNS(0); + } + } else if (cell->type == id_DQSBUFM) { + info.clock_port = id_SCLK; + if (port == id_DATAVALID) { + info.clockToQ = getDelayFromNS(0.2); + } else if (port == id_READ0 || port == id_READ1) { + info.setup = getDelayFromNS(0.5); + info.hold = getDelayFromNS(-0.4); + } else { + NPNR_ASSERT_FALSE("unknown DQSBUFM register port"); + } } return info; } @@ -765,4 +949,53 @@ GlobalInfoPOD Arch::globalInfoAtLoc(Location loc) return chip_info->location_glbinfo[locidx]; } +bool Arch::getPIODQSGroup(BelId pio, bool &dqsright, int &dqsrow) +{ + for (int i = 0; i < chip_info->num_pios; i++) { + if (Location(chip_info->pio_info[i].abs_loc) == pio.location && chip_info->pio_info[i].bel_index == pio.index) { + int dqs = chip_info->pio_info[i].dqsgroup; + if (dqs == -1) + return false; + else { + dqsright = (dqs & 2048) != 0; + dqsrow = dqs & 0x1FF; + return true; + } + } + } + NPNR_ASSERT_FALSE("failed to find PIO"); +} + +BelId Arch::getDQSBUF(bool dqsright, int dqsrow) +{ + BelId bel; + bel.location.y = dqsrow; + bel.location.x = (dqsright ? (chip_info->width - 1) : 0); + for (int i = 0; i < locInfo(bel)->num_bels; i++) { + auto &bd = locInfo(bel)->bel_data[i]; + if (bd.type == id_DQSBUFM.index) { + bel.index = i; + return bel; + } + } + NPNR_ASSERT_FALSE("failed to find DQSBUF"); +} + +WireId Arch::getBankECLK(int bank, int eclk) +{ + return getWireByLocAndBasename(Location(0, 0), "G_BANK" + std::to_string(bank) + "ECLK" + std::to_string(eclk)); +} + +#ifdef WITH_HEAP +const std::string Arch::defaultPlacer = "heap"; +#else +const std::string Arch::defaultPlacer = "sa"; +#endif + +const std::vector<std::string> Arch::availablePlacers = {"sa", +#ifdef WITH_HEAP + "heap" +#endif +}; + NEXTPNR_NAMESPACE_END diff --git a/ecp5/arch.h b/ecp5/arch.h index a68673f4..3de06a42 100644 --- a/ecp5/arch.h +++ b/ecp5/arch.h @@ -103,7 +103,7 @@ NPNR_PACKED_STRUCT(struct PIOInfoPOD { int32_t bel_index; RelPtr<char> function_name; int16_t bank; - int16_t padding; + int16_t dqsgroup; }); NPNR_PACKED_STRUCT(struct PackagePinPOD { @@ -204,7 +204,7 @@ NPNR_PACKED_STRUCT(struct ChipInfoPOD { RelPtr<SpeedGradePOD> speed_grades; }); -#if defined(_MSC_VER) +#if defined(_MSC_VER) || defined(EXTERNAL_CHIPDB_ROOT) extern const char *chipdb_blob_25k; extern const char *chipdb_blob_45k; extern const char *chipdb_blob_85k; @@ -448,6 +448,30 @@ struct ArchArgs } speed = SPEED_6; }; +struct DelayKey +{ + IdString celltype, from, to; + inline bool operator==(const DelayKey &other) const + { + return celltype == other.celltype && from == other.from && to == other.to; + } +}; + +NEXTPNR_NAMESPACE_END +namespace std { +template <> struct hash<NEXTPNR_NAMESPACE_PREFIX DelayKey> +{ + std::size_t operator()(const NEXTPNR_NAMESPACE_PREFIX DelayKey &dk) const noexcept + { + std::size_t seed = std::hash<NEXTPNR_NAMESPACE_PREFIX IdString>()(dk.celltype); + seed ^= std::hash<NEXTPNR_NAMESPACE_PREFIX IdString>()(dk.from) + 0x9e3779b9 + (seed << 6) + (seed >> 2); + seed ^= std::hash<NEXTPNR_NAMESPACE_PREFIX IdString>()(dk.to) + 0x9e3779b9 + (seed << 6) + (seed >> 2); + return seed; + } +}; +} // namespace std +NEXTPNR_NAMESPACE_BEGIN + struct Arch : BaseCtx { const ChipInfoPOD *chip_info; @@ -918,7 +942,7 @@ struct Arch : BaseCtx delay_t estimateDelay(WireId src, WireId dst) const; delay_t predictDelay(const NetInfo *net_info, const PortRef &sink) const; delay_t getDelayEpsilon() const { return 20; } - delay_t getRipupDelayPenalty() const { return 200; } + delay_t getRipupDelayPenalty() const { return 400; } float getDelayNS(delay_t v) const { return v * 0.001; } DelayInfo getDelayFromNS(float ns) const { @@ -971,6 +995,8 @@ struct Arch : BaseCtx void assignArchInfo(); + void permute_luts(); + std::vector<std::pair<std::string, std::string>> getTilesAtLocation(int row, int col); std::string getTileByTypeAndLocation(int row, int col, std::string type) const { @@ -993,8 +1019,23 @@ struct Arch : BaseCtx NPNR_ASSERT_FALSE_STR("no tile at (" + std::to_string(col) + ", " + std::to_string(row) + ") with type in set"); } + std::string getTileByType(std::string type) const + { + for (int i = 0; i < chip_info->height * chip_info->width; i++) { + auto &tileloc = chip_info->tile_info[i]; + for (int j = 0; j < tileloc.num_tiles; j++) + if (chip_info->tiletype_names[tileloc.tile_names[j].type_idx].get() == type) + return tileloc.tile_names[j].name.get(); + } + NPNR_ASSERT_FALSE_STR("no with type " + type); + } + GlobalInfoPOD globalInfoAtLoc(Location loc); + bool getPIODQSGroup(BelId pio, bool &dqsright, int &dqsrow); + BelId getDQSBUF(bool dqsright, int dqsrow); + WireId getBankECLK(int bank, int eclk); + // Apply LPF constraints to the context bool applyLPF(std::string filename, std::istream &in); @@ -1002,6 +1043,11 @@ struct Arch : BaseCtx IdString id_clk, id_lsr; IdString id_clkmux, id_lsrmux; IdString id_srmode, id_mode; + + mutable std::unordered_map<DelayKey, std::pair<bool, DelayInfo>> celldelay_cache; + + static const std::string defaultPlacer; + static const std::vector<std::string> availablePlacers; }; NEXTPNR_NAMESPACE_END diff --git a/ecp5/arch_place.cc b/ecp5/arch_place.cc index ff70bb5a..e5c9b31f 100644 --- a/ecp5/arch_place.cc +++ b/ecp5/arch_place.cc @@ -18,8 +18,10 @@ */ #include "cells.h" +#include "design_utils.h" #include "log.h" #include "nextpnr.h" +#include "timing.h" #include "util.h" NEXTPNR_NAMESPACE_BEGIN @@ -115,4 +117,76 @@ bool Arch::isValidBelForCell(CellInfo *cell, BelId bel) const } } +void Arch::permute_luts() +{ + NetCriticalityMap nc; + get_criticalities(getCtx(), &nc); + + std::unordered_map<PortInfo *, size_t> port_to_user; + for (auto net : sorted(nets)) { + NetInfo *ni = net.second; + for (size_t i = 0; i < ni->users.size(); i++) { + auto &usr = ni->users.at(i); + port_to_user[&(usr.cell->ports.at(usr.port))] = i; + } + } + + auto proc_lut = [&](CellInfo *ci, int lut) { + std::vector<IdString> port_names; + for (int i = 0; i < 4; i++) + port_names.push_back(id(std::string("ABCD").substr(i, 1) + std::to_string(lut))); + + std::vector<std::pair<float, int>> inputs; + std::vector<NetInfo *> orig_nets; + + for (int i = 0; i < 4; i++) { + auto &port = ci->ports.at(port_names.at(i)); + float crit = 0; + if (port.net != nullptr && nc.count(port.net->name)) { + auto &n = nc.at(port.net->name); + size_t usr = port_to_user.at(&port); + if (usr < n.criticality.size()) + crit = n.criticality.at(usr); + } + orig_nets.push_back(port.net); + inputs.emplace_back(crit, i); + } + // Least critical first (A input is slowest) + std::sort(inputs.begin(), inputs.end()); + for (int i = 0; i < 4; i++) { + IdString p = port_names.at(i); + // log_info("%s %s %f\n", p.c_str(ctx), port_names.at(inputs.at(i).second).c_str(ctx), inputs.at(i).first); + disconnect_port(getCtx(), ci, p); + ci->ports.at(p).net = nullptr; + if (orig_nets.at(inputs.at(i).second) != nullptr) { + connect_port(getCtx(), orig_nets.at(inputs.at(i).second), ci, p); + ci->params[id(p.str(this) + "MUX")] = p.str(this); + } else { + ci->params[id(p.str(this) + "MUX")] = "1"; + } + } + // Rewrite function + int old_init = int_or_default(ci->params, id("LUT" + std::to_string(lut) + "_INITVAL"), 0); + int new_init = 0; + for (int i = 0; i < 16; i++) { + int old_index = 0; + for (int k = 0; k < 4; k++) { + if (i & (1 << k)) + old_index |= (1 << inputs.at(k).second); + } + if (old_init & (1 << old_index)) + new_init |= (1 << i); + } + ci->params[id("LUT" + std::to_string(lut) + "_INITVAL")] = std::to_string(new_init); + }; + + for (auto cell : sorted(cells)) { + CellInfo *ci = cell.second; + if (ci->type == id_TRELLIS_SLICE && str_or_default(ci->params, id("MODE"), "LOGIC") == "LOGIC") { + proc_lut(ci, 0); + proc_lut(ci, 1); + } + } +} + NEXTPNR_NAMESPACE_END diff --git a/ecp5/arch_pybindings.cc b/ecp5/arch_pybindings.cc index 5e73a673..18d21112 100644 --- a/ecp5/arch_pybindings.cc +++ b/ecp5/arch_pybindings.cc @@ -133,6 +133,13 @@ void arch_wrap_python() fn_wrapper_2a_v<Context, decltype(&Context::addClock), &Context::addClock, conv_from_str<IdString>, pass_through<float>>::def_wrap(ctx_cls, "addClock"); + fn_wrapper_5a_v<Context, decltype(&Context::createRectangularRegion), &Context::createRectangularRegion, + conv_from_str<IdString>, pass_through<int>, pass_through<int>, pass_through<int>, + pass_through<int>>::def_wrap(ctx_cls, "createRectangularRegion"); + fn_wrapper_2a_v<Context, decltype(&Context::addBelToRegion), &Context::addBelToRegion, conv_from_str<IdString>, + conv_from_str<BelId>>::def_wrap(ctx_cls, "addBelToRegion"); + fn_wrapper_2a_v<Context, decltype(&Context::constrainCellToRegion), &Context::constrainCellToRegion, + conv_from_str<IdString>, conv_from_str<IdString>>::def_wrap(ctx_cls, "constrainCellToRegion"); WRAP_RANGE(Bel, conv_to_str<BelId>); WRAP_RANGE(Wire, conv_to_str<WireId>); diff --git a/ecp5/archdefs.h b/ecp5/archdefs.h index bfc5769b..d7ea0a8e 100644 --- a/ecp5/archdefs.h +++ b/ecp5/archdefs.h @@ -159,7 +159,9 @@ struct ArchCellInfo { bool using_dff; bool has_l6mux; + bool is_carry; IdString clk_sig, lsr_sig, clkmux, lsrmux, srmode; + int sd0, sd1; } sliceInfo; }; diff --git a/ecp5/baseconfigs.cc b/ecp5/baseconfigs.cc new file mode 100644 index 00000000..3dc07b22 --- /dev/null +++ b/ecp5/baseconfigs.cc @@ -0,0 +1,2630 @@ +#include "config.h" +#include "nextpnr.h" + +NEXTPNR_NAMESPACE_BEGIN +namespace BaseConfigs { +void config_empty_lfe5u_25f(ChipConfig &cc) +{ + cc.chip_name = "LFE5U-25F"; + cc.tiles["CIB_R49C3:CIB_PLL3"].add_enum("CIB.JA3MUX", "0"); + cc.tiles["CIB_R49C3:CIB_PLL3"].add_enum("CIB.JB3MUX", "0"); + cc.tiles["CIB_R49C42:VCIB_DCU0"].add_enum("CIB.JA1MUX", "0"); + cc.tiles["CIB_R49C42:VCIB_DCU0"].add_enum("CIB.JA3MUX", "0"); + cc.tiles["CIB_R49C42:VCIB_DCU0"].add_enum("CIB.JA5MUX", "0"); + cc.tiles["CIB_R49C42:VCIB_DCU0"].add_enum("CIB.JA7MUX", "0"); + cc.tiles["CIB_R49C42:VCIB_DCU0"].add_enum("CIB.JB1MUX", "0"); + cc.tiles["CIB_R49C42:VCIB_DCU0"].add_enum("CIB.JB3MUX", "0"); + cc.tiles["CIB_R49C42:VCIB_DCU0"].add_enum("CIB.JB5MUX", "0"); + cc.tiles["CIB_R49C42:VCIB_DCU0"].add_enum("CIB.JB7MUX", "0"); + cc.tiles["CIB_R49C42:VCIB_DCU0"].add_enum("CIB.JC0MUX", "0"); + cc.tiles["CIB_R49C42:VCIB_DCU0"].add_enum("CIB.JC2MUX", "0"); + cc.tiles["CIB_R49C42:VCIB_DCU0"].add_enum("CIB.JC4MUX", "0"); + cc.tiles["CIB_R49C42:VCIB_DCU0"].add_enum("CIB.JC6MUX", "0"); + cc.tiles["CIB_R49C42:VCIB_DCU0"].add_enum("CIB.JD0MUX", "0"); + cc.tiles["CIB_R49C42:VCIB_DCU0"].add_enum("CIB.JD2MUX", "0"); + cc.tiles["CIB_R49C42:VCIB_DCU0"].add_enum("CIB.JD4MUX", "0"); + cc.tiles["CIB_R49C42:VCIB_DCU0"].add_enum("CIB.JD6MUX", "0"); + cc.tiles["CIB_R49C43:VCIB_DCUA"].add_enum("CIB.JA1MUX", "0"); + cc.tiles["CIB_R49C43:VCIB_DCUA"].add_enum("CIB.JA3MUX", "0"); + cc.tiles["CIB_R49C43:VCIB_DCUA"].add_enum("CIB.JA5MUX", "0"); + cc.tiles["CIB_R49C43:VCIB_DCUA"].add_enum("CIB.JA7MUX", "0"); + cc.tiles["CIB_R49C43:VCIB_DCUA"].add_enum("CIB.JB1MUX", "0"); + cc.tiles["CIB_R49C43:VCIB_DCUA"].add_enum("CIB.JB3MUX", "0"); + cc.tiles["CIB_R49C43:VCIB_DCUA"].add_enum("CIB.JB5MUX", "0"); + cc.tiles["CIB_R49C43:VCIB_DCUA"].add_enum("CIB.JB7MUX", "0"); + cc.tiles["CIB_R49C43:VCIB_DCUA"].add_enum("CIB.JC0MUX", "0"); + cc.tiles["CIB_R49C43:VCIB_DCUA"].add_enum("CIB.JC2MUX", "0"); + cc.tiles["CIB_R49C43:VCIB_DCUA"].add_enum("CIB.JC4MUX", "0"); + cc.tiles["CIB_R49C43:VCIB_DCUA"].add_enum("CIB.JC6MUX", "0"); + cc.tiles["CIB_R49C43:VCIB_DCUA"].add_enum("CIB.JD0MUX", "0"); + cc.tiles["CIB_R49C43:VCIB_DCUA"].add_enum("CIB.JD2MUX", "0"); + cc.tiles["CIB_R49C43:VCIB_DCUA"].add_enum("CIB.JD4MUX", "0"); + cc.tiles["CIB_R49C43:VCIB_DCUA"].add_enum("CIB.JD6MUX", "0"); + cc.tiles["CIB_R49C44:VCIB_DCUB"].add_enum("CIB.JA1MUX", "0"); + cc.tiles["CIB_R49C44:VCIB_DCUB"].add_enum("CIB.JA3MUX", "0"); + cc.tiles["CIB_R49C44:VCIB_DCUB"].add_enum("CIB.JA5MUX", "0"); + cc.tiles["CIB_R49C44:VCIB_DCUB"].add_enum("CIB.JA7MUX", "0"); + cc.tiles["CIB_R49C44:VCIB_DCUB"].add_enum("CIB.JB1MUX", "0"); + cc.tiles["CIB_R49C44:VCIB_DCUB"].add_enum("CIB.JB3MUX", "0"); + cc.tiles["CIB_R49C44:VCIB_DCUB"].add_enum("CIB.JB5MUX", "0"); + cc.tiles["CIB_R49C44:VCIB_DCUB"].add_enum("CIB.JB7MUX", "0"); + cc.tiles["CIB_R49C44:VCIB_DCUB"].add_enum("CIB.JC0MUX", "0"); + cc.tiles["CIB_R49C44:VCIB_DCUB"].add_enum("CIB.JC2MUX", "0"); + cc.tiles["CIB_R49C44:VCIB_DCUB"].add_enum("CIB.JC4MUX", "0"); + cc.tiles["CIB_R49C44:VCIB_DCUB"].add_enum("CIB.JC6MUX", "0"); + cc.tiles["CIB_R49C44:VCIB_DCUB"].add_enum("CIB.JD0MUX", "0"); + cc.tiles["CIB_R49C44:VCIB_DCUB"].add_enum("CIB.JD2MUX", "0"); + cc.tiles["CIB_R49C44:VCIB_DCUB"].add_enum("CIB.JD4MUX", "0"); + cc.tiles["CIB_R49C44:VCIB_DCUB"].add_enum("CIB.JD6MUX", "0"); + cc.tiles["CIB_R49C45:VCIB_DCUC"].add_enum("CIB.JA1MUX", "0"); + cc.tiles["CIB_R49C45:VCIB_DCUC"].add_enum("CIB.JA3MUX", "0"); + cc.tiles["CIB_R49C45:VCIB_DCUC"].add_enum("CIB.JA5MUX", "0"); + cc.tiles["CIB_R49C45:VCIB_DCUC"].add_enum("CIB.JA7MUX", "0"); + cc.tiles["CIB_R49C45:VCIB_DCUC"].add_enum("CIB.JB1MUX", "0"); + cc.tiles["CIB_R49C45:VCIB_DCUC"].add_enum("CIB.JB3MUX", "0"); + cc.tiles["CIB_R49C45:VCIB_DCUC"].add_enum("CIB.JB5MUX", "0"); + cc.tiles["CIB_R49C45:VCIB_DCUC"].add_enum("CIB.JB7MUX", "0"); + cc.tiles["CIB_R49C45:VCIB_DCUC"].add_enum("CIB.JC0MUX", "0"); + cc.tiles["CIB_R49C45:VCIB_DCUC"].add_enum("CIB.JC2MUX", "0"); + cc.tiles["CIB_R49C45:VCIB_DCUC"].add_enum("CIB.JC4MUX", "0"); + cc.tiles["CIB_R49C45:VCIB_DCUC"].add_enum("CIB.JC6MUX", "0"); + cc.tiles["CIB_R49C45:VCIB_DCUC"].add_enum("CIB.JD0MUX", "0"); + cc.tiles["CIB_R49C45:VCIB_DCUC"].add_enum("CIB.JD2MUX", "0"); + cc.tiles["CIB_R49C45:VCIB_DCUC"].add_enum("CIB.JD4MUX", "0"); + cc.tiles["CIB_R49C45:VCIB_DCUC"].add_enum("CIB.JD6MUX", "0"); + cc.tiles["CIB_R49C46:VCIB_DCUD"].add_enum("CIB.JA1MUX", "0"); + cc.tiles["CIB_R49C46:VCIB_DCUD"].add_enum("CIB.JA5MUX", "0"); + cc.tiles["CIB_R49C46:VCIB_DCUD"].add_enum("CIB.JA7MUX", "0"); + cc.tiles["CIB_R49C46:VCIB_DCUD"].add_enum("CIB.JB1MUX", "0"); + cc.tiles["CIB_R49C46:VCIB_DCUD"].add_enum("CIB.JB3MUX", "0"); + cc.tiles["CIB_R49C46:VCIB_DCUD"].add_enum("CIB.JB5MUX", "0"); + cc.tiles["CIB_R49C46:VCIB_DCUD"].add_enum("CIB.JB7MUX", "0"); + cc.tiles["CIB_R49C46:VCIB_DCUD"].add_enum("CIB.JC0MUX", "0"); + cc.tiles["CIB_R49C46:VCIB_DCUD"].add_enum("CIB.JC2MUX", "0"); + cc.tiles["CIB_R49C46:VCIB_DCUD"].add_enum("CIB.JC4MUX", "0"); + cc.tiles["CIB_R49C46:VCIB_DCUD"].add_enum("CIB.JC6MUX", "0"); + cc.tiles["CIB_R49C46:VCIB_DCUD"].add_enum("CIB.JD0MUX", "0"); + cc.tiles["CIB_R49C46:VCIB_DCUD"].add_enum("CIB.JD2MUX", "0"); + cc.tiles["CIB_R49C46:VCIB_DCUD"].add_enum("CIB.JD4MUX", "0"); + cc.tiles["CIB_R49C46:VCIB_DCUD"].add_enum("CIB.JD6MUX", "0"); + cc.tiles["CIB_R49C47:VCIB_DCUF"].add_enum("CIB.JA1MUX", "0"); + cc.tiles["CIB_R49C47:VCIB_DCUF"].add_enum("CIB.JA3MUX", "0"); + cc.tiles["CIB_R49C47:VCIB_DCUF"].add_enum("CIB.JA5MUX", "0"); + cc.tiles["CIB_R49C47:VCIB_DCUF"].add_enum("CIB.JA7MUX", "0"); + cc.tiles["CIB_R49C47:VCIB_DCUF"].add_enum("CIB.JB1MUX", "0"); + cc.tiles["CIB_R49C47:VCIB_DCUF"].add_enum("CIB.JB3MUX", "0"); + cc.tiles["CIB_R49C47:VCIB_DCUF"].add_enum("CIB.JB5MUX", "0"); + cc.tiles["CIB_R49C47:VCIB_DCUF"].add_enum("CIB.JB7MUX", "0"); + cc.tiles["CIB_R49C47:VCIB_DCUF"].add_enum("CIB.JC0MUX", "0"); + cc.tiles["CIB_R49C47:VCIB_DCUF"].add_enum("CIB.JC2MUX", "0"); + cc.tiles["CIB_R49C47:VCIB_DCUF"].add_enum("CIB.JC4MUX", "0"); + cc.tiles["CIB_R49C47:VCIB_DCUF"].add_enum("CIB.JC6MUX", "0"); + cc.tiles["CIB_R49C47:VCIB_DCUF"].add_enum("CIB.JD0MUX", "0"); + cc.tiles["CIB_R49C47:VCIB_DCUF"].add_enum("CIB.JD2MUX", "0"); + cc.tiles["CIB_R49C47:VCIB_DCUF"].add_enum("CIB.JD4MUX", "0"); + cc.tiles["CIB_R49C47:VCIB_DCUF"].add_enum("CIB.JD6MUX", "0"); + cc.tiles["CIB_R49C48:VCIB_DCU3"].add_enum("CIB.JA5MUX", "0"); + cc.tiles["CIB_R49C48:VCIB_DCU3"].add_enum("CIB.JA7MUX", "0"); + cc.tiles["CIB_R49C48:VCIB_DCU3"].add_enum("CIB.JB1MUX", "0"); + cc.tiles["CIB_R49C48:VCIB_DCU3"].add_enum("CIB.JB3MUX", "0"); + cc.tiles["CIB_R49C48:VCIB_DCU3"].add_enum("CIB.JB5MUX", "0"); + cc.tiles["CIB_R49C48:VCIB_DCU3"].add_enum("CIB.JB7MUX", "0"); + cc.tiles["CIB_R49C48:VCIB_DCU3"].add_enum("CIB.JC0MUX", "0"); + cc.tiles["CIB_R49C48:VCIB_DCU3"].add_enum("CIB.JC4MUX", "0"); + cc.tiles["CIB_R49C48:VCIB_DCU3"].add_enum("CIB.JC6MUX", "0"); + cc.tiles["CIB_R49C48:VCIB_DCU3"].add_enum("CIB.JD0MUX", "0"); + cc.tiles["CIB_R49C48:VCIB_DCU3"].add_enum("CIB.JD2MUX", "0"); + cc.tiles["CIB_R49C48:VCIB_DCU3"].add_enum("CIB.JD4MUX", "0"); + cc.tiles["CIB_R49C48:VCIB_DCU3"].add_enum("CIB.JD6MUX", "0"); + cc.tiles["CIB_R49C49:VCIB_DCU2"].add_enum("CIB.JB1MUX", "0"); + cc.tiles["CIB_R49C49:VCIB_DCU2"].add_enum("CIB.JB3MUX", "0"); + cc.tiles["CIB_R49C49:VCIB_DCU2"].add_enum("CIB.JB5MUX", "0"); + cc.tiles["CIB_R49C49:VCIB_DCU2"].add_enum("CIB.JB7MUX", "0"); + cc.tiles["CIB_R49C49:VCIB_DCU2"].add_enum("CIB.JD0MUX", "0"); + cc.tiles["CIB_R49C49:VCIB_DCU2"].add_enum("CIB.JD2MUX", "0"); + cc.tiles["CIB_R49C49:VCIB_DCU2"].add_enum("CIB.JD4MUX", "0"); + cc.tiles["CIB_R49C49:VCIB_DCU2"].add_enum("CIB.JD6MUX", "0"); + cc.tiles["CIB_R49C50:VCIB_DCUG"].add_enum("CIB.JB1MUX", "0"); + cc.tiles["CIB_R49C50:VCIB_DCUG"].add_enum("CIB.JB3MUX", "0"); + cc.tiles["CIB_R49C50:VCIB_DCUG"].add_enum("CIB.JB5MUX", "0"); + cc.tiles["CIB_R49C50:VCIB_DCUG"].add_enum("CIB.JB7MUX", "0"); + cc.tiles["CIB_R49C50:VCIB_DCUG"].add_enum("CIB.JD0MUX", "0"); + cc.tiles["CIB_R49C50:VCIB_DCUG"].add_enum("CIB.JD2MUX", "0"); + cc.tiles["CIB_R49C50:VCIB_DCUG"].add_enum("CIB.JD4MUX", "0"); + cc.tiles["CIB_R49C50:VCIB_DCUG"].add_enum("CIB.JD6MUX", "0"); + cc.tiles["CIB_R49C51:VCIB_DCUH"].add_enum("CIB.JB1MUX", "0"); + cc.tiles["CIB_R49C51:VCIB_DCUH"].add_enum("CIB.JB3MUX", "0"); + cc.tiles["CIB_R49C51:VCIB_DCUH"].add_enum("CIB.JB5MUX", "0"); + cc.tiles["CIB_R49C51:VCIB_DCUH"].add_enum("CIB.JB7MUX", "0"); + cc.tiles["CIB_R49C51:VCIB_DCUH"].add_enum("CIB.JD0MUX", "0"); + cc.tiles["CIB_R49C51:VCIB_DCUH"].add_enum("CIB.JD2MUX", "0"); + cc.tiles["CIB_R49C51:VCIB_DCUH"].add_enum("CIB.JD4MUX", "0"); + cc.tiles["CIB_R49C51:VCIB_DCUH"].add_enum("CIB.JD6MUX", "0"); + cc.tiles["CIB_R49C52:VCIB_DCUI"].add_enum("CIB.JB1MUX", "0"); + cc.tiles["CIB_R49C52:VCIB_DCUI"].add_enum("CIB.JB3MUX", "0"); + cc.tiles["CIB_R49C52:VCIB_DCUI"].add_enum("CIB.JB5MUX", "0"); + cc.tiles["CIB_R49C52:VCIB_DCUI"].add_enum("CIB.JB7MUX", "0"); + cc.tiles["CIB_R49C52:VCIB_DCUI"].add_enum("CIB.JD0MUX", "0"); + cc.tiles["CIB_R49C52:VCIB_DCUI"].add_enum("CIB.JD2MUX", "0"); + cc.tiles["CIB_R49C52:VCIB_DCUI"].add_enum("CIB.JD4MUX", "0"); + cc.tiles["CIB_R49C52:VCIB_DCUI"].add_enum("CIB.JD6MUX", "0"); + cc.tiles["CIB_R49C53:VCIB_DCU1"].add_enum("CIB.JB1MUX", "0"); + cc.tiles["CIB_R49C53:VCIB_DCU1"].add_enum("CIB.JB3MUX", "0"); + cc.tiles["CIB_R49C53:VCIB_DCU1"].add_enum("CIB.JB5MUX", "0"); + cc.tiles["CIB_R49C53:VCIB_DCU1"].add_enum("CIB.JD0MUX", "0"); + cc.tiles["CIB_R49C53:VCIB_DCU1"].add_enum("CIB.JD2MUX", "0"); + cc.tiles["CIB_R49C69:CIB_PLL3"].add_enum("CIB.JA3MUX", "0"); + cc.tiles["CIB_R49C69:CIB_PLL3"].add_enum("CIB.JB3MUX", "0"); + cc.tiles["CIB_R49C6:CIB_EFB0"].add_enum("CIB.JB3MUX", "0"); + cc.tiles["CIB_R49C6:CIB_EFB0"].add_enum("CIB.JC6MUX", "0"); + cc.tiles["CIB_R49C6:CIB_EFB0"].add_enum("CIB.JD6MUX", "0"); + cc.tiles["CIB_R49C7:CIB_EFB1"].add_enum("CIB.JA3MUX", "0"); + cc.tiles["CIB_R49C7:CIB_EFB1"].add_enum("CIB.JA4MUX", "0"); + cc.tiles["CIB_R49C7:CIB_EFB1"].add_enum("CIB.JA5MUX", "0"); + cc.tiles["CIB_R49C7:CIB_EFB1"].add_enum("CIB.JA6MUX", "0"); + cc.tiles["CIB_R49C7:CIB_EFB1"].add_enum("CIB.JB3MUX", "0"); + cc.tiles["CIB_R49C7:CIB_EFB1"].add_enum("CIB.JB4MUX", "0"); + cc.tiles["CIB_R49C7:CIB_EFB1"].add_enum("CIB.JB5MUX", "0"); + cc.tiles["CIB_R49C7:CIB_EFB1"].add_enum("CIB.JB6MUX", "0"); + cc.tiles["CIB_R49C7:CIB_EFB1"].add_enum("CIB.JC3MUX", "0"); + cc.tiles["CIB_R49C7:CIB_EFB1"].add_enum("CIB.JC4MUX", "0"); + cc.tiles["CIB_R49C7:CIB_EFB1"].add_enum("CIB.JC5MUX", "0"); + cc.tiles["CIB_R49C7:CIB_EFB1"].add_enum("CIB.JD3MUX", "0"); + cc.tiles["CIB_R49C7:CIB_EFB1"].add_enum("CIB.JD4MUX", "0"); + cc.tiles["CIB_R49C7:CIB_EFB1"].add_enum("CIB.JD5MUX", "0"); + cc.tiles["MIB_R13C31:CMUX_UL_0"].add_arc("G_DCS0CLK0", "G_VPFN0000"); + cc.tiles["MIB_R13C32:CMUX_UR_0"].add_arc("G_DCS0CLK1", "G_VPFN0000"); + cc.tiles["MIB_R13C3:DSP_SPINE_UL1"].add_unknown(2, 0); + cc.tiles["MIB_R13C3:DSP_SPINE_UL1"].add_unknown(3, 0); + cc.tiles["MIB_R13C3:DSP_SPINE_UL1"].add_unknown(5, 0); + cc.tiles["MIB_R13C3:DSP_SPINE_UL1"].add_unknown(11, 0); + cc.tiles["MIB_R13C3:DSP_SPINE_UL1"].add_unknown(13, 0); + cc.tiles["MIB_R37C31:CMUX_LL_0"].add_arc("G_DCS1CLK0", "G_VPFN0000"); + cc.tiles["MIB_R37C32:CMUX_LR_0"].add_arc("G_DCS1CLK1", "G_VPFN0000"); + cc.tiles["MIB_R50C4:EFB0_PICB0"].add_unknown(54, 1); + cc.tiles["MIB_R50C4:EFB0_PICB0"].add_unknown(56, 1); + cc.tiles["MIB_R50C4:EFB0_PICB0"].add_unknown(82, 1); + cc.tiles["MIB_R50C4:EFB0_PICB0"].add_unknown(94, 1); +} + +void config_empty_lfe5u_45f(ChipConfig &cc) +{ + cc.chip_name = "LFE5U-45F"; + cc.tiles["CIB_R10C3:PVT_COUNT2"].add_unknown(2, 0); + cc.tiles["CIB_R10C3:PVT_COUNT2"].add_unknown(3, 0); + cc.tiles["CIB_R10C3:PVT_COUNT2"].add_unknown(5, 0); + cc.tiles["CIB_R10C3:PVT_COUNT2"].add_unknown(11, 0); + cc.tiles["CIB_R10C3:PVT_COUNT2"].add_unknown(13, 0); + cc.tiles["CIB_R5C1:CIB_PLL1"].add_enum("CIB.JA3MUX", "0"); + cc.tiles["CIB_R5C1:CIB_PLL1"].add_enum("CIB.JB3MUX", "0"); + cc.tiles["CIB_R5C89:CIB_PLL1"].add_enum("CIB.JA3MUX", "0"); + cc.tiles["CIB_R5C89:CIB_PLL1"].add_enum("CIB.JB3MUX", "0"); + cc.tiles["CIB_R70C3:CIB_PLL3"].add_enum("CIB.JA3MUX", "0"); + cc.tiles["CIB_R70C3:CIB_PLL3"].add_enum("CIB.JB3MUX", "0"); + cc.tiles["CIB_R70C42:VCIB_DCU0"].add_enum("CIB.JA1MUX", "0"); + cc.tiles["CIB_R70C42:VCIB_DCU0"].add_enum("CIB.JA3MUX", "0"); + cc.tiles["CIB_R70C42:VCIB_DCU0"].add_enum("CIB.JA5MUX", "0"); + cc.tiles["CIB_R70C42:VCIB_DCU0"].add_enum("CIB.JA7MUX", "0"); + cc.tiles["CIB_R70C42:VCIB_DCU0"].add_enum("CIB.JB1MUX", "0"); + cc.tiles["CIB_R70C42:VCIB_DCU0"].add_enum("CIB.JB3MUX", "0"); + cc.tiles["CIB_R70C42:VCIB_DCU0"].add_enum("CIB.JB5MUX", "0"); + cc.tiles["CIB_R70C42:VCIB_DCU0"].add_enum("CIB.JB7MUX", "0"); + cc.tiles["CIB_R70C42:VCIB_DCU0"].add_enum("CIB.JC0MUX", "0"); + cc.tiles["CIB_R70C42:VCIB_DCU0"].add_enum("CIB.JC2MUX", "0"); + cc.tiles["CIB_R70C42:VCIB_DCU0"].add_enum("CIB.JC4MUX", "0"); + cc.tiles["CIB_R70C42:VCIB_DCU0"].add_enum("CIB.JC6MUX", "0"); + cc.tiles["CIB_R70C42:VCIB_DCU0"].add_enum("CIB.JD0MUX", "0"); + cc.tiles["CIB_R70C42:VCIB_DCU0"].add_enum("CIB.JD2MUX", "0"); + cc.tiles["CIB_R70C42:VCIB_DCU0"].add_enum("CIB.JD4MUX", "0"); + cc.tiles["CIB_R70C42:VCIB_DCU0"].add_enum("CIB.JD6MUX", "0"); + cc.tiles["CIB_R70C43:VCIB_DCUA"].add_enum("CIB.JA1MUX", "0"); + cc.tiles["CIB_R70C43:VCIB_DCUA"].add_enum("CIB.JA3MUX", "0"); + cc.tiles["CIB_R70C43:VCIB_DCUA"].add_enum("CIB.JA5MUX", "0"); + cc.tiles["CIB_R70C43:VCIB_DCUA"].add_enum("CIB.JA7MUX", "0"); + cc.tiles["CIB_R70C43:VCIB_DCUA"].add_enum("CIB.JB1MUX", "0"); + cc.tiles["CIB_R70C43:VCIB_DCUA"].add_enum("CIB.JB3MUX", "0"); + cc.tiles["CIB_R70C43:VCIB_DCUA"].add_enum("CIB.JB5MUX", "0"); + cc.tiles["CIB_R70C43:VCIB_DCUA"].add_enum("CIB.JB7MUX", "0"); + cc.tiles["CIB_R70C43:VCIB_DCUA"].add_enum("CIB.JC0MUX", "0"); + cc.tiles["CIB_R70C43:VCIB_DCUA"].add_enum("CIB.JC2MUX", "0"); + cc.tiles["CIB_R70C43:VCIB_DCUA"].add_enum("CIB.JC4MUX", "0"); + cc.tiles["CIB_R70C43:VCIB_DCUA"].add_enum("CIB.JC6MUX", "0"); + cc.tiles["CIB_R70C43:VCIB_DCUA"].add_enum("CIB.JD0MUX", "0"); + cc.tiles["CIB_R70C43:VCIB_DCUA"].add_enum("CIB.JD2MUX", "0"); + cc.tiles["CIB_R70C43:VCIB_DCUA"].add_enum("CIB.JD4MUX", "0"); + cc.tiles["CIB_R70C43:VCIB_DCUA"].add_enum("CIB.JD6MUX", "0"); + cc.tiles["CIB_R70C44:VCIB_DCUB"].add_enum("CIB.JA1MUX", "0"); + cc.tiles["CIB_R70C44:VCIB_DCUB"].add_enum("CIB.JA3MUX", "0"); + cc.tiles["CIB_R70C44:VCIB_DCUB"].add_enum("CIB.JA5MUX", "0"); + cc.tiles["CIB_R70C44:VCIB_DCUB"].add_enum("CIB.JA7MUX", "0"); + cc.tiles["CIB_R70C44:VCIB_DCUB"].add_enum("CIB.JB1MUX", "0"); + cc.tiles["CIB_R70C44:VCIB_DCUB"].add_enum("CIB.JB3MUX", "0"); + cc.tiles["CIB_R70C44:VCIB_DCUB"].add_enum("CIB.JB5MUX", "0"); + cc.tiles["CIB_R70C44:VCIB_DCUB"].add_enum("CIB.JB7MUX", "0"); + cc.tiles["CIB_R70C44:VCIB_DCUB"].add_enum("CIB.JC0MUX", "0"); + cc.tiles["CIB_R70C44:VCIB_DCUB"].add_enum("CIB.JC2MUX", "0"); + cc.tiles["CIB_R70C44:VCIB_DCUB"].add_enum("CIB.JC4MUX", "0"); + cc.tiles["CIB_R70C44:VCIB_DCUB"].add_enum("CIB.JC6MUX", "0"); + cc.tiles["CIB_R70C44:VCIB_DCUB"].add_enum("CIB.JD0MUX", "0"); + cc.tiles["CIB_R70C44:VCIB_DCUB"].add_enum("CIB.JD2MUX", "0"); + cc.tiles["CIB_R70C44:VCIB_DCUB"].add_enum("CIB.JD4MUX", "0"); + cc.tiles["CIB_R70C44:VCIB_DCUB"].add_enum("CIB.JD6MUX", "0"); + cc.tiles["CIB_R70C45:VCIB_DCUC"].add_enum("CIB.JA1MUX", "0"); + cc.tiles["CIB_R70C45:VCIB_DCUC"].add_enum("CIB.JA3MUX", "0"); + cc.tiles["CIB_R70C45:VCIB_DCUC"].add_enum("CIB.JA5MUX", "0"); + cc.tiles["CIB_R70C45:VCIB_DCUC"].add_enum("CIB.JA7MUX", "0"); + cc.tiles["CIB_R70C45:VCIB_DCUC"].add_enum("CIB.JB1MUX", "0"); + cc.tiles["CIB_R70C45:VCIB_DCUC"].add_enum("CIB.JB3MUX", "0"); + cc.tiles["CIB_R70C45:VCIB_DCUC"].add_enum("CIB.JB5MUX", "0"); + cc.tiles["CIB_R70C45:VCIB_DCUC"].add_enum("CIB.JB7MUX", "0"); + cc.tiles["CIB_R70C45:VCIB_DCUC"].add_enum("CIB.JC0MUX", "0"); + cc.tiles["CIB_R70C45:VCIB_DCUC"].add_enum("CIB.JC2MUX", "0"); + cc.tiles["CIB_R70C45:VCIB_DCUC"].add_enum("CIB.JC4MUX", "0"); + cc.tiles["CIB_R70C45:VCIB_DCUC"].add_enum("CIB.JC6MUX", "0"); + cc.tiles["CIB_R70C45:VCIB_DCUC"].add_enum("CIB.JD0MUX", "0"); + cc.tiles["CIB_R70C45:VCIB_DCUC"].add_enum("CIB.JD2MUX", "0"); + cc.tiles["CIB_R70C45:VCIB_DCUC"].add_enum("CIB.JD4MUX", "0"); + cc.tiles["CIB_R70C45:VCIB_DCUC"].add_enum("CIB.JD6MUX", "0"); + cc.tiles["CIB_R70C46:VCIB_DCUD"].add_enum("CIB.JA1MUX", "0"); + cc.tiles["CIB_R70C46:VCIB_DCUD"].add_enum("CIB.JA5MUX", "0"); + cc.tiles["CIB_R70C46:VCIB_DCUD"].add_enum("CIB.JA7MUX", "0"); + cc.tiles["CIB_R70C46:VCIB_DCUD"].add_enum("CIB.JB1MUX", "0"); + cc.tiles["CIB_R70C46:VCIB_DCUD"].add_enum("CIB.JB3MUX", "0"); + cc.tiles["CIB_R70C46:VCIB_DCUD"].add_enum("CIB.JB5MUX", "0"); + cc.tiles["CIB_R70C46:VCIB_DCUD"].add_enum("CIB.JB7MUX", "0"); + cc.tiles["CIB_R70C46:VCIB_DCUD"].add_enum("CIB.JC0MUX", "0"); + cc.tiles["CIB_R70C46:VCIB_DCUD"].add_enum("CIB.JC2MUX", "0"); + cc.tiles["CIB_R70C46:VCIB_DCUD"].add_enum("CIB.JC4MUX", "0"); + cc.tiles["CIB_R70C46:VCIB_DCUD"].add_enum("CIB.JC6MUX", "0"); + cc.tiles["CIB_R70C46:VCIB_DCUD"].add_enum("CIB.JD0MUX", "0"); + cc.tiles["CIB_R70C46:VCIB_DCUD"].add_enum("CIB.JD2MUX", "0"); + cc.tiles["CIB_R70C46:VCIB_DCUD"].add_enum("CIB.JD4MUX", "0"); + cc.tiles["CIB_R70C46:VCIB_DCUD"].add_enum("CIB.JD6MUX", "0"); + cc.tiles["CIB_R70C47:VCIB_DCUF"].add_enum("CIB.JA1MUX", "0"); + cc.tiles["CIB_R70C47:VCIB_DCUF"].add_enum("CIB.JA3MUX", "0"); + cc.tiles["CIB_R70C47:VCIB_DCUF"].add_enum("CIB.JA5MUX", "0"); + cc.tiles["CIB_R70C47:VCIB_DCUF"].add_enum("CIB.JA7MUX", "0"); + cc.tiles["CIB_R70C47:VCIB_DCUF"].add_enum("CIB.JB1MUX", "0"); + cc.tiles["CIB_R70C47:VCIB_DCUF"].add_enum("CIB.JB3MUX", "0"); + cc.tiles["CIB_R70C47:VCIB_DCUF"].add_enum("CIB.JB5MUX", "0"); + cc.tiles["CIB_R70C47:VCIB_DCUF"].add_enum("CIB.JB7MUX", "0"); + cc.tiles["CIB_R70C47:VCIB_DCUF"].add_enum("CIB.JC0MUX", "0"); + cc.tiles["CIB_R70C47:VCIB_DCUF"].add_enum("CIB.JC2MUX", "0"); + cc.tiles["CIB_R70C47:VCIB_DCUF"].add_enum("CIB.JC4MUX", "0"); + cc.tiles["CIB_R70C47:VCIB_DCUF"].add_enum("CIB.JC6MUX", "0"); + cc.tiles["CIB_R70C47:VCIB_DCUF"].add_enum("CIB.JD0MUX", "0"); + cc.tiles["CIB_R70C47:VCIB_DCUF"].add_enum("CIB.JD2MUX", "0"); + cc.tiles["CIB_R70C47:VCIB_DCUF"].add_enum("CIB.JD4MUX", "0"); + cc.tiles["CIB_R70C47:VCIB_DCUF"].add_enum("CIB.JD6MUX", "0"); + cc.tiles["CIB_R70C48:VCIB_DCU3"].add_enum("CIB.JA5MUX", "0"); + cc.tiles["CIB_R70C48:VCIB_DCU3"].add_enum("CIB.JA7MUX", "0"); + cc.tiles["CIB_R70C48:VCIB_DCU3"].add_enum("CIB.JB1MUX", "0"); + cc.tiles["CIB_R70C48:VCIB_DCU3"].add_enum("CIB.JB3MUX", "0"); + cc.tiles["CIB_R70C48:VCIB_DCU3"].add_enum("CIB.JB5MUX", "0"); + cc.tiles["CIB_R70C48:VCIB_DCU3"].add_enum("CIB.JB7MUX", "0"); + cc.tiles["CIB_R70C48:VCIB_DCU3"].add_enum("CIB.JC0MUX", "0"); + cc.tiles["CIB_R70C48:VCIB_DCU3"].add_enum("CIB.JC4MUX", "0"); + cc.tiles["CIB_R70C48:VCIB_DCU3"].add_enum("CIB.JC6MUX", "0"); + cc.tiles["CIB_R70C48:VCIB_DCU3"].add_enum("CIB.JD0MUX", "0"); + cc.tiles["CIB_R70C48:VCIB_DCU3"].add_enum("CIB.JD2MUX", "0"); + cc.tiles["CIB_R70C48:VCIB_DCU3"].add_enum("CIB.JD4MUX", "0"); + cc.tiles["CIB_R70C48:VCIB_DCU3"].add_enum("CIB.JD6MUX", "0"); + cc.tiles["CIB_R70C49:VCIB_DCU2"].add_enum("CIB.JB1MUX", "0"); + cc.tiles["CIB_R70C49:VCIB_DCU2"].add_enum("CIB.JB3MUX", "0"); + cc.tiles["CIB_R70C49:VCIB_DCU2"].add_enum("CIB.JB5MUX", "0"); + cc.tiles["CIB_R70C49:VCIB_DCU2"].add_enum("CIB.JB7MUX", "0"); + cc.tiles["CIB_R70C49:VCIB_DCU2"].add_enum("CIB.JD0MUX", "0"); + cc.tiles["CIB_R70C49:VCIB_DCU2"].add_enum("CIB.JD2MUX", "0"); + cc.tiles["CIB_R70C49:VCIB_DCU2"].add_enum("CIB.JD4MUX", "0"); + cc.tiles["CIB_R70C49:VCIB_DCU2"].add_enum("CIB.JD6MUX", "0"); + cc.tiles["CIB_R70C50:VCIB_DCUG"].add_enum("CIB.JB1MUX", "0"); + cc.tiles["CIB_R70C50:VCIB_DCUG"].add_enum("CIB.JB3MUX", "0"); + cc.tiles["CIB_R70C50:VCIB_DCUG"].add_enum("CIB.JB5MUX", "0"); + cc.tiles["CIB_R70C50:VCIB_DCUG"].add_enum("CIB.JB7MUX", "0"); + cc.tiles["CIB_R70C50:VCIB_DCUG"].add_enum("CIB.JD0MUX", "0"); + cc.tiles["CIB_R70C50:VCIB_DCUG"].add_enum("CIB.JD2MUX", "0"); + cc.tiles["CIB_R70C50:VCIB_DCUG"].add_enum("CIB.JD4MUX", "0"); + cc.tiles["CIB_R70C50:VCIB_DCUG"].add_enum("CIB.JD6MUX", "0"); + cc.tiles["CIB_R70C51:VCIB_DCUH"].add_enum("CIB.JB1MUX", "0"); + cc.tiles["CIB_R70C51:VCIB_DCUH"].add_enum("CIB.JB3MUX", "0"); + cc.tiles["CIB_R70C51:VCIB_DCUH"].add_enum("CIB.JB5MUX", "0"); + cc.tiles["CIB_R70C51:VCIB_DCUH"].add_enum("CIB.JB7MUX", "0"); + cc.tiles["CIB_R70C51:VCIB_DCUH"].add_enum("CIB.JD0MUX", "0"); + cc.tiles["CIB_R70C51:VCIB_DCUH"].add_enum("CIB.JD2MUX", "0"); + cc.tiles["CIB_R70C51:VCIB_DCUH"].add_enum("CIB.JD4MUX", "0"); + cc.tiles["CIB_R70C51:VCIB_DCUH"].add_enum("CIB.JD6MUX", "0"); + cc.tiles["CIB_R70C52:VCIB_DCUI"].add_enum("CIB.JB1MUX", "0"); + cc.tiles["CIB_R70C52:VCIB_DCUI"].add_enum("CIB.JB3MUX", "0"); + cc.tiles["CIB_R70C52:VCIB_DCUI"].add_enum("CIB.JB5MUX", "0"); + cc.tiles["CIB_R70C52:VCIB_DCUI"].add_enum("CIB.JB7MUX", "0"); + cc.tiles["CIB_R70C52:VCIB_DCUI"].add_enum("CIB.JD0MUX", "0"); + cc.tiles["CIB_R70C52:VCIB_DCUI"].add_enum("CIB.JD2MUX", "0"); + cc.tiles["CIB_R70C52:VCIB_DCUI"].add_enum("CIB.JD4MUX", "0"); + cc.tiles["CIB_R70C52:VCIB_DCUI"].add_enum("CIB.JD6MUX", "0"); + cc.tiles["CIB_R70C53:VCIB_DCU1"].add_enum("CIB.JB1MUX", "0"); + cc.tiles["CIB_R70C53:VCIB_DCU1"].add_enum("CIB.JB3MUX", "0"); + cc.tiles["CIB_R70C53:VCIB_DCU1"].add_enum("CIB.JB5MUX", "0"); + cc.tiles["CIB_R70C53:VCIB_DCU1"].add_enum("CIB.JD0MUX", "0"); + cc.tiles["CIB_R70C53:VCIB_DCU1"].add_enum("CIB.JD2MUX", "0"); + cc.tiles["CIB_R70C69:VCIB_DCU0"].add_enum("CIB.JA1MUX", "0"); + cc.tiles["CIB_R70C69:VCIB_DCU0"].add_enum("CIB.JA3MUX", "0"); + cc.tiles["CIB_R70C69:VCIB_DCU0"].add_enum("CIB.JA5MUX", "0"); + cc.tiles["CIB_R70C69:VCIB_DCU0"].add_enum("CIB.JA7MUX", "0"); + cc.tiles["CIB_R70C69:VCIB_DCU0"].add_enum("CIB.JB1MUX", "0"); + cc.tiles["CIB_R70C69:VCIB_DCU0"].add_enum("CIB.JB3MUX", "0"); + cc.tiles["CIB_R70C69:VCIB_DCU0"].add_enum("CIB.JB5MUX", "0"); + cc.tiles["CIB_R70C69:VCIB_DCU0"].add_enum("CIB.JB7MUX", "0"); + cc.tiles["CIB_R70C69:VCIB_DCU0"].add_enum("CIB.JC0MUX", "0"); + cc.tiles["CIB_R70C69:VCIB_DCU0"].add_enum("CIB.JC2MUX", "0"); + cc.tiles["CIB_R70C69:VCIB_DCU0"].add_enum("CIB.JC4MUX", "0"); + cc.tiles["CIB_R70C69:VCIB_DCU0"].add_enum("CIB.JC6MUX", "0"); + cc.tiles["CIB_R70C69:VCIB_DCU0"].add_enum("CIB.JD0MUX", "0"); + cc.tiles["CIB_R70C69:VCIB_DCU0"].add_enum("CIB.JD2MUX", "0"); + cc.tiles["CIB_R70C69:VCIB_DCU0"].add_enum("CIB.JD4MUX", "0"); + cc.tiles["CIB_R70C69:VCIB_DCU0"].add_enum("CIB.JD6MUX", "0"); + cc.tiles["CIB_R70C6:CIB_EFB0"].add_enum("CIB.JB3MUX", "0"); + cc.tiles["CIB_R70C6:CIB_EFB0"].add_enum("CIB.JC6MUX", "0"); + cc.tiles["CIB_R70C6:CIB_EFB0"].add_enum("CIB.JD6MUX", "0"); + cc.tiles["CIB_R70C70:VCIB_DCUA"].add_enum("CIB.JA1MUX", "0"); + cc.tiles["CIB_R70C70:VCIB_DCUA"].add_enum("CIB.JA3MUX", "0"); + cc.tiles["CIB_R70C70:VCIB_DCUA"].add_enum("CIB.JA5MUX", "0"); + cc.tiles["CIB_R70C70:VCIB_DCUA"].add_enum("CIB.JA7MUX", "0"); + cc.tiles["CIB_R70C70:VCIB_DCUA"].add_enum("CIB.JB1MUX", "0"); + cc.tiles["CIB_R70C70:VCIB_DCUA"].add_enum("CIB.JB3MUX", "0"); + cc.tiles["CIB_R70C70:VCIB_DCUA"].add_enum("CIB.JB5MUX", "0"); + cc.tiles["CIB_R70C70:VCIB_DCUA"].add_enum("CIB.JB7MUX", "0"); + cc.tiles["CIB_R70C70:VCIB_DCUA"].add_enum("CIB.JC0MUX", "0"); + cc.tiles["CIB_R70C70:VCIB_DCUA"].add_enum("CIB.JC2MUX", "0"); + cc.tiles["CIB_R70C70:VCIB_DCUA"].add_enum("CIB.JC4MUX", "0"); + cc.tiles["CIB_R70C70:VCIB_DCUA"].add_enum("CIB.JC6MUX", "0"); + cc.tiles["CIB_R70C70:VCIB_DCUA"].add_enum("CIB.JD0MUX", "0"); + cc.tiles["CIB_R70C70:VCIB_DCUA"].add_enum("CIB.JD2MUX", "0"); + cc.tiles["CIB_R70C70:VCIB_DCUA"].add_enum("CIB.JD4MUX", "0"); + cc.tiles["CIB_R70C70:VCIB_DCUA"].add_enum("CIB.JD6MUX", "0"); + cc.tiles["CIB_R70C71:VCIB_DCUB"].add_enum("CIB.JA1MUX", "0"); + cc.tiles["CIB_R70C71:VCIB_DCUB"].add_enum("CIB.JA3MUX", "0"); + cc.tiles["CIB_R70C71:VCIB_DCUB"].add_enum("CIB.JA5MUX", "0"); + cc.tiles["CIB_R70C71:VCIB_DCUB"].add_enum("CIB.JA7MUX", "0"); + cc.tiles["CIB_R70C71:VCIB_DCUB"].add_enum("CIB.JB1MUX", "0"); + cc.tiles["CIB_R70C71:VCIB_DCUB"].add_enum("CIB.JB3MUX", "0"); + cc.tiles["CIB_R70C71:VCIB_DCUB"].add_enum("CIB.JB5MUX", "0"); + cc.tiles["CIB_R70C71:VCIB_DCUB"].add_enum("CIB.JB7MUX", "0"); + cc.tiles["CIB_R70C71:VCIB_DCUB"].add_enum("CIB.JC0MUX", "0"); + cc.tiles["CIB_R70C71:VCIB_DCUB"].add_enum("CIB.JC2MUX", "0"); + cc.tiles["CIB_R70C71:VCIB_DCUB"].add_enum("CIB.JC4MUX", "0"); + cc.tiles["CIB_R70C71:VCIB_DCUB"].add_enum("CIB.JC6MUX", "0"); + cc.tiles["CIB_R70C71:VCIB_DCUB"].add_enum("CIB.JD0MUX", "0"); + cc.tiles["CIB_R70C71:VCIB_DCUB"].add_enum("CIB.JD2MUX", "0"); + cc.tiles["CIB_R70C71:VCIB_DCUB"].add_enum("CIB.JD4MUX", "0"); + cc.tiles["CIB_R70C71:VCIB_DCUB"].add_enum("CIB.JD6MUX", "0"); + cc.tiles["CIB_R70C72:VCIB_DCUC"].add_enum("CIB.JA1MUX", "0"); + cc.tiles["CIB_R70C72:VCIB_DCUC"].add_enum("CIB.JA3MUX", "0"); + cc.tiles["CIB_R70C72:VCIB_DCUC"].add_enum("CIB.JA5MUX", "0"); + cc.tiles["CIB_R70C72:VCIB_DCUC"].add_enum("CIB.JA7MUX", "0"); + cc.tiles["CIB_R70C72:VCIB_DCUC"].add_enum("CIB.JB1MUX", "0"); + cc.tiles["CIB_R70C72:VCIB_DCUC"].add_enum("CIB.JB3MUX", "0"); + cc.tiles["CIB_R70C72:VCIB_DCUC"].add_enum("CIB.JB5MUX", "0"); + cc.tiles["CIB_R70C72:VCIB_DCUC"].add_enum("CIB.JB7MUX", "0"); + cc.tiles["CIB_R70C72:VCIB_DCUC"].add_enum("CIB.JC0MUX", "0"); + cc.tiles["CIB_R70C72:VCIB_DCUC"].add_enum("CIB.JC2MUX", "0"); + cc.tiles["CIB_R70C72:VCIB_DCUC"].add_enum("CIB.JC4MUX", "0"); + cc.tiles["CIB_R70C72:VCIB_DCUC"].add_enum("CIB.JC6MUX", "0"); + cc.tiles["CIB_R70C72:VCIB_DCUC"].add_enum("CIB.JD0MUX", "0"); + cc.tiles["CIB_R70C72:VCIB_DCUC"].add_enum("CIB.JD2MUX", "0"); + cc.tiles["CIB_R70C72:VCIB_DCUC"].add_enum("CIB.JD4MUX", "0"); + cc.tiles["CIB_R70C72:VCIB_DCUC"].add_enum("CIB.JD6MUX", "0"); + cc.tiles["CIB_R70C73:VCIB_DCUD"].add_enum("CIB.JA1MUX", "0"); + cc.tiles["CIB_R70C73:VCIB_DCUD"].add_enum("CIB.JA5MUX", "0"); + cc.tiles["CIB_R70C73:VCIB_DCUD"].add_enum("CIB.JA7MUX", "0"); + cc.tiles["CIB_R70C73:VCIB_DCUD"].add_enum("CIB.JB1MUX", "0"); + cc.tiles["CIB_R70C73:VCIB_DCUD"].add_enum("CIB.JB3MUX", "0"); + cc.tiles["CIB_R70C73:VCIB_DCUD"].add_enum("CIB.JB5MUX", "0"); + cc.tiles["CIB_R70C73:VCIB_DCUD"].add_enum("CIB.JB7MUX", "0"); + cc.tiles["CIB_R70C73:VCIB_DCUD"].add_enum("CIB.JC0MUX", "0"); + cc.tiles["CIB_R70C73:VCIB_DCUD"].add_enum("CIB.JC2MUX", "0"); + cc.tiles["CIB_R70C73:VCIB_DCUD"].add_enum("CIB.JC4MUX", "0"); + cc.tiles["CIB_R70C73:VCIB_DCUD"].add_enum("CIB.JC6MUX", "0"); + cc.tiles["CIB_R70C73:VCIB_DCUD"].add_enum("CIB.JD0MUX", "0"); + cc.tiles["CIB_R70C73:VCIB_DCUD"].add_enum("CIB.JD2MUX", "0"); + cc.tiles["CIB_R70C73:VCIB_DCUD"].add_enum("CIB.JD4MUX", "0"); + cc.tiles["CIB_R70C73:VCIB_DCUD"].add_enum("CIB.JD6MUX", "0"); + cc.tiles["CIB_R70C74:VCIB_DCUF"].add_enum("CIB.JA1MUX", "0"); + cc.tiles["CIB_R70C74:VCIB_DCUF"].add_enum("CIB.JA3MUX", "0"); + cc.tiles["CIB_R70C74:VCIB_DCUF"].add_enum("CIB.JA5MUX", "0"); + cc.tiles["CIB_R70C74:VCIB_DCUF"].add_enum("CIB.JA7MUX", "0"); + cc.tiles["CIB_R70C74:VCIB_DCUF"].add_enum("CIB.JB1MUX", "0"); + cc.tiles["CIB_R70C74:VCIB_DCUF"].add_enum("CIB.JB3MUX", "0"); + cc.tiles["CIB_R70C74:VCIB_DCUF"].add_enum("CIB.JB5MUX", "0"); + cc.tiles["CIB_R70C74:VCIB_DCUF"].add_enum("CIB.JB7MUX", "0"); + cc.tiles["CIB_R70C74:VCIB_DCUF"].add_enum("CIB.JC0MUX", "0"); + cc.tiles["CIB_R70C74:VCIB_DCUF"].add_enum("CIB.JC2MUX", "0"); + cc.tiles["CIB_R70C74:VCIB_DCUF"].add_enum("CIB.JC4MUX", "0"); + cc.tiles["CIB_R70C74:VCIB_DCUF"].add_enum("CIB.JC6MUX", "0"); + cc.tiles["CIB_R70C74:VCIB_DCUF"].add_enum("CIB.JD0MUX", "0"); + cc.tiles["CIB_R70C74:VCIB_DCUF"].add_enum("CIB.JD2MUX", "0"); + cc.tiles["CIB_R70C74:VCIB_DCUF"].add_enum("CIB.JD4MUX", "0"); + cc.tiles["CIB_R70C74:VCIB_DCUF"].add_enum("CIB.JD6MUX", "0"); + cc.tiles["CIB_R70C75:VCIB_DCU3"].add_enum("CIB.JA5MUX", "0"); + cc.tiles["CIB_R70C75:VCIB_DCU3"].add_enum("CIB.JA7MUX", "0"); + cc.tiles["CIB_R70C75:VCIB_DCU3"].add_enum("CIB.JB1MUX", "0"); + cc.tiles["CIB_R70C75:VCIB_DCU3"].add_enum("CIB.JB3MUX", "0"); + cc.tiles["CIB_R70C75:VCIB_DCU3"].add_enum("CIB.JB5MUX", "0"); + cc.tiles["CIB_R70C75:VCIB_DCU3"].add_enum("CIB.JB7MUX", "0"); + cc.tiles["CIB_R70C75:VCIB_DCU3"].add_enum("CIB.JC0MUX", "0"); + cc.tiles["CIB_R70C75:VCIB_DCU3"].add_enum("CIB.JC4MUX", "0"); + cc.tiles["CIB_R70C75:VCIB_DCU3"].add_enum("CIB.JC6MUX", "0"); + cc.tiles["CIB_R70C75:VCIB_DCU3"].add_enum("CIB.JD0MUX", "0"); + cc.tiles["CIB_R70C75:VCIB_DCU3"].add_enum("CIB.JD2MUX", "0"); + cc.tiles["CIB_R70C75:VCIB_DCU3"].add_enum("CIB.JD4MUX", "0"); + cc.tiles["CIB_R70C75:VCIB_DCU3"].add_enum("CIB.JD6MUX", "0"); + cc.tiles["CIB_R70C76:VCIB_DCU2"].add_enum("CIB.JB1MUX", "0"); + cc.tiles["CIB_R70C76:VCIB_DCU2"].add_enum("CIB.JB3MUX", "0"); + cc.tiles["CIB_R70C76:VCIB_DCU2"].add_enum("CIB.JB5MUX", "0"); + cc.tiles["CIB_R70C76:VCIB_DCU2"].add_enum("CIB.JB7MUX", "0"); + cc.tiles["CIB_R70C76:VCIB_DCU2"].add_enum("CIB.JD0MUX", "0"); + cc.tiles["CIB_R70C76:VCIB_DCU2"].add_enum("CIB.JD2MUX", "0"); + cc.tiles["CIB_R70C76:VCIB_DCU2"].add_enum("CIB.JD4MUX", "0"); + cc.tiles["CIB_R70C76:VCIB_DCU2"].add_enum("CIB.JD6MUX", "0"); + cc.tiles["CIB_R70C77:VCIB_DCUG"].add_enum("CIB.JB1MUX", "0"); + cc.tiles["CIB_R70C77:VCIB_DCUG"].add_enum("CIB.JB3MUX", "0"); + cc.tiles["CIB_R70C77:VCIB_DCUG"].add_enum("CIB.JB5MUX", "0"); + cc.tiles["CIB_R70C77:VCIB_DCUG"].add_enum("CIB.JB7MUX", "0"); + cc.tiles["CIB_R70C77:VCIB_DCUG"].add_enum("CIB.JD0MUX", "0"); + cc.tiles["CIB_R70C77:VCIB_DCUG"].add_enum("CIB.JD2MUX", "0"); + cc.tiles["CIB_R70C77:VCIB_DCUG"].add_enum("CIB.JD4MUX", "0"); + cc.tiles["CIB_R70C77:VCIB_DCUG"].add_enum("CIB.JD6MUX", "0"); + cc.tiles["CIB_R70C78:VCIB_DCUH"].add_enum("CIB.JB1MUX", "0"); + cc.tiles["CIB_R70C78:VCIB_DCUH"].add_enum("CIB.JB3MUX", "0"); + cc.tiles["CIB_R70C78:VCIB_DCUH"].add_enum("CIB.JB5MUX", "0"); + cc.tiles["CIB_R70C78:VCIB_DCUH"].add_enum("CIB.JB7MUX", "0"); + cc.tiles["CIB_R70C78:VCIB_DCUH"].add_enum("CIB.JD0MUX", "0"); + cc.tiles["CIB_R70C78:VCIB_DCUH"].add_enum("CIB.JD2MUX", "0"); + cc.tiles["CIB_R70C78:VCIB_DCUH"].add_enum("CIB.JD4MUX", "0"); + cc.tiles["CIB_R70C78:VCIB_DCUH"].add_enum("CIB.JD6MUX", "0"); + cc.tiles["CIB_R70C79:VCIB_DCUI"].add_enum("CIB.JB1MUX", "0"); + cc.tiles["CIB_R70C79:VCIB_DCUI"].add_enum("CIB.JB3MUX", "0"); + cc.tiles["CIB_R70C79:VCIB_DCUI"].add_enum("CIB.JB5MUX", "0"); + cc.tiles["CIB_R70C79:VCIB_DCUI"].add_enum("CIB.JB7MUX", "0"); + cc.tiles["CIB_R70C79:VCIB_DCUI"].add_enum("CIB.JD0MUX", "0"); + cc.tiles["CIB_R70C79:VCIB_DCUI"].add_enum("CIB.JD2MUX", "0"); + cc.tiles["CIB_R70C79:VCIB_DCUI"].add_enum("CIB.JD4MUX", "0"); + cc.tiles["CIB_R70C79:VCIB_DCUI"].add_enum("CIB.JD6MUX", "0"); + cc.tiles["CIB_R70C7:CIB_EFB1"].add_enum("CIB.JA3MUX", "0"); + cc.tiles["CIB_R70C7:CIB_EFB1"].add_enum("CIB.JA4MUX", "0"); + cc.tiles["CIB_R70C7:CIB_EFB1"].add_enum("CIB.JA5MUX", "0"); + cc.tiles["CIB_R70C7:CIB_EFB1"].add_enum("CIB.JA6MUX", "0"); + cc.tiles["CIB_R70C7:CIB_EFB1"].add_enum("CIB.JB3MUX", "0"); + cc.tiles["CIB_R70C7:CIB_EFB1"].add_enum("CIB.JB4MUX", "0"); + cc.tiles["CIB_R70C7:CIB_EFB1"].add_enum("CIB.JB5MUX", "0"); + cc.tiles["CIB_R70C7:CIB_EFB1"].add_enum("CIB.JB6MUX", "0"); + cc.tiles["CIB_R70C7:CIB_EFB1"].add_enum("CIB.JC3MUX", "0"); + cc.tiles["CIB_R70C7:CIB_EFB1"].add_enum("CIB.JC4MUX", "0"); + cc.tiles["CIB_R70C7:CIB_EFB1"].add_enum("CIB.JC5MUX", "0"); + cc.tiles["CIB_R70C7:CIB_EFB1"].add_enum("CIB.JD3MUX", "0"); + cc.tiles["CIB_R70C7:CIB_EFB1"].add_enum("CIB.JD4MUX", "0"); + cc.tiles["CIB_R70C7:CIB_EFB1"].add_enum("CIB.JD5MUX", "0"); + cc.tiles["CIB_R70C80:VCIB_DCU1"].add_enum("CIB.JB1MUX", "0"); + cc.tiles["CIB_R70C80:VCIB_DCU1"].add_enum("CIB.JB3MUX", "0"); + cc.tiles["CIB_R70C80:VCIB_DCU1"].add_enum("CIB.JB5MUX", "0"); + cc.tiles["CIB_R70C80:VCIB_DCU1"].add_enum("CIB.JD0MUX", "0"); + cc.tiles["CIB_R70C80:VCIB_DCU1"].add_enum("CIB.JD2MUX", "0"); + cc.tiles["CIB_R70C87:CIB_PLL3"].add_enum("CIB.JA3MUX", "0"); + cc.tiles["CIB_R70C87:CIB_PLL3"].add_enum("CIB.JB3MUX", "0"); + cc.tiles["MIB_R10C40:CMUX_UL_0"].add_arc("G_DCS0CLK0", "G_VPFN0000"); + cc.tiles["MIB_R10C41:CMUX_UR_0"].add_arc("G_DCS0CLK1", "G_VPFN0000"); + cc.tiles["MIB_R58C40:CMUX_LL_0"].add_arc("G_DCS1CLK0", "G_VPFN0000"); + cc.tiles["MIB_R58C41:CMUX_LR_0"].add_arc("G_DCS1CLK1", "G_VPFN0000"); + cc.tiles["MIB_R71C3:BANKREF8"].add_unknown(18, 0); + cc.tiles["MIB_R71C4:EFB0_PICB0"].add_unknown(54, 1); + cc.tiles["MIB_R71C4:EFB0_PICB0"].add_unknown(56, 1); + cc.tiles["MIB_R71C4:EFB0_PICB0"].add_unknown(82, 1); + cc.tiles["MIB_R71C4:EFB0_PICB0"].add_unknown(94, 1); +} + +void config_empty_lfe5u_85f(ChipConfig &cc) +{ + cc.chip_name = "LFE5U-85F"; + cc.tiles["CIB_R10C3:PVT_COUNT2"].add_unknown(2, 0); + cc.tiles["CIB_R10C3:PVT_COUNT2"].add_unknown(3, 0); + cc.tiles["CIB_R10C3:PVT_COUNT2"].add_unknown(5, 0); + cc.tiles["CIB_R10C3:PVT_COUNT2"].add_unknown(11, 0); + cc.tiles["CIB_R10C3:PVT_COUNT2"].add_unknown(13, 0); + cc.tiles["CIB_R5C125:CIB_PLL1"].add_enum("CIB.JA3MUX", "0"); + cc.tiles["CIB_R5C125:CIB_PLL1"].add_enum("CIB.JB3MUX", "0"); + cc.tiles["CIB_R5C1:CIB_PLL1"].add_enum("CIB.JA3MUX", "0"); + cc.tiles["CIB_R5C1:CIB_PLL1"].add_enum("CIB.JB3MUX", "0"); + cc.tiles["CIB_R94C123:CIB_PLL3"].add_enum("CIB.JA3MUX", "0"); + cc.tiles["CIB_R94C123:CIB_PLL3"].add_enum("CIB.JB3MUX", "0"); + cc.tiles["CIB_R94C3:CIB_PLL3"].add_enum("CIB.JA3MUX", "0"); + cc.tiles["CIB_R94C3:CIB_PLL3"].add_enum("CIB.JB3MUX", "0"); + cc.tiles["CIB_R94C46:VCIB_DCU0"].add_enum("CIB.JA1MUX", "0"); + cc.tiles["CIB_R94C46:VCIB_DCU0"].add_enum("CIB.JA3MUX", "0"); + cc.tiles["CIB_R94C46:VCIB_DCU0"].add_enum("CIB.JA5MUX", "0"); + cc.tiles["CIB_R94C46:VCIB_DCU0"].add_enum("CIB.JA7MUX", "0"); + cc.tiles["CIB_R94C46:VCIB_DCU0"].add_enum("CIB.JB1MUX", "0"); + cc.tiles["CIB_R94C46:VCIB_DCU0"].add_enum("CIB.JB3MUX", "0"); + cc.tiles["CIB_R94C46:VCIB_DCU0"].add_enum("CIB.JB5MUX", "0"); + cc.tiles["CIB_R94C46:VCIB_DCU0"].add_enum("CIB.JB7MUX", "0"); + cc.tiles["CIB_R94C46:VCIB_DCU0"].add_enum("CIB.JC0MUX", "0"); + cc.tiles["CIB_R94C46:VCIB_DCU0"].add_enum("CIB.JC2MUX", "0"); + cc.tiles["CIB_R94C46:VCIB_DCU0"].add_enum("CIB.JC4MUX", "0"); + cc.tiles["CIB_R94C46:VCIB_DCU0"].add_enum("CIB.JC6MUX", "0"); + cc.tiles["CIB_R94C46:VCIB_DCU0"].add_enum("CIB.JD0MUX", "0"); + cc.tiles["CIB_R94C46:VCIB_DCU0"].add_enum("CIB.JD2MUX", "0"); + cc.tiles["CIB_R94C46:VCIB_DCU0"].add_enum("CIB.JD4MUX", "0"); + cc.tiles["CIB_R94C46:VCIB_DCU0"].add_enum("CIB.JD6MUX", "0"); + cc.tiles["CIB_R94C47:VCIB_DCUA"].add_enum("CIB.JA1MUX", "0"); + cc.tiles["CIB_R94C47:VCIB_DCUA"].add_enum("CIB.JA3MUX", "0"); + cc.tiles["CIB_R94C47:VCIB_DCUA"].add_enum("CIB.JA5MUX", "0"); + cc.tiles["CIB_R94C47:VCIB_DCUA"].add_enum("CIB.JA7MUX", "0"); + cc.tiles["CIB_R94C47:VCIB_DCUA"].add_enum("CIB.JB1MUX", "0"); + cc.tiles["CIB_R94C47:VCIB_DCUA"].add_enum("CIB.JB3MUX", "0"); + cc.tiles["CIB_R94C47:VCIB_DCUA"].add_enum("CIB.JB5MUX", "0"); + cc.tiles["CIB_R94C47:VCIB_DCUA"].add_enum("CIB.JB7MUX", "0"); + cc.tiles["CIB_R94C47:VCIB_DCUA"].add_enum("CIB.JC0MUX", "0"); + cc.tiles["CIB_R94C47:VCIB_DCUA"].add_enum("CIB.JC2MUX", "0"); + cc.tiles["CIB_R94C47:VCIB_DCUA"].add_enum("CIB.JC4MUX", "0"); + cc.tiles["CIB_R94C47:VCIB_DCUA"].add_enum("CIB.JC6MUX", "0"); + cc.tiles["CIB_R94C47:VCIB_DCUA"].add_enum("CIB.JD0MUX", "0"); + cc.tiles["CIB_R94C47:VCIB_DCUA"].add_enum("CIB.JD2MUX", "0"); + cc.tiles["CIB_R94C47:VCIB_DCUA"].add_enum("CIB.JD4MUX", "0"); + cc.tiles["CIB_R94C47:VCIB_DCUA"].add_enum("CIB.JD6MUX", "0"); + cc.tiles["CIB_R94C48:VCIB_DCUB"].add_enum("CIB.JA1MUX", "0"); + cc.tiles["CIB_R94C48:VCIB_DCUB"].add_enum("CIB.JA3MUX", "0"); + cc.tiles["CIB_R94C48:VCIB_DCUB"].add_enum("CIB.JA5MUX", "0"); + cc.tiles["CIB_R94C48:VCIB_DCUB"].add_enum("CIB.JA7MUX", "0"); + cc.tiles["CIB_R94C48:VCIB_DCUB"].add_enum("CIB.JB1MUX", "0"); + cc.tiles["CIB_R94C48:VCIB_DCUB"].add_enum("CIB.JB3MUX", "0"); + cc.tiles["CIB_R94C48:VCIB_DCUB"].add_enum("CIB.JB5MUX", "0"); + cc.tiles["CIB_R94C48:VCIB_DCUB"].add_enum("CIB.JB7MUX", "0"); + cc.tiles["CIB_R94C48:VCIB_DCUB"].add_enum("CIB.JC0MUX", "0"); + cc.tiles["CIB_R94C48:VCIB_DCUB"].add_enum("CIB.JC2MUX", "0"); + cc.tiles["CIB_R94C48:VCIB_DCUB"].add_enum("CIB.JC4MUX", "0"); + cc.tiles["CIB_R94C48:VCIB_DCUB"].add_enum("CIB.JC6MUX", "0"); + cc.tiles["CIB_R94C48:VCIB_DCUB"].add_enum("CIB.JD0MUX", "0"); + cc.tiles["CIB_R94C48:VCIB_DCUB"].add_enum("CIB.JD2MUX", "0"); + cc.tiles["CIB_R94C48:VCIB_DCUB"].add_enum("CIB.JD4MUX", "0"); + cc.tiles["CIB_R94C48:VCIB_DCUB"].add_enum("CIB.JD6MUX", "0"); + cc.tiles["CIB_R94C49:VCIB_DCUC"].add_enum("CIB.JA1MUX", "0"); + cc.tiles["CIB_R94C49:VCIB_DCUC"].add_enum("CIB.JA3MUX", "0"); + cc.tiles["CIB_R94C49:VCIB_DCUC"].add_enum("CIB.JA5MUX", "0"); + cc.tiles["CIB_R94C49:VCIB_DCUC"].add_enum("CIB.JA7MUX", "0"); + cc.tiles["CIB_R94C49:VCIB_DCUC"].add_enum("CIB.JB1MUX", "0"); + cc.tiles["CIB_R94C49:VCIB_DCUC"].add_enum("CIB.JB3MUX", "0"); + cc.tiles["CIB_R94C49:VCIB_DCUC"].add_enum("CIB.JB5MUX", "0"); + cc.tiles["CIB_R94C49:VCIB_DCUC"].add_enum("CIB.JB7MUX", "0"); + cc.tiles["CIB_R94C49:VCIB_DCUC"].add_enum("CIB.JC0MUX", "0"); + cc.tiles["CIB_R94C49:VCIB_DCUC"].add_enum("CIB.JC2MUX", "0"); + cc.tiles["CIB_R94C49:VCIB_DCUC"].add_enum("CIB.JC4MUX", "0"); + cc.tiles["CIB_R94C49:VCIB_DCUC"].add_enum("CIB.JC6MUX", "0"); + cc.tiles["CIB_R94C49:VCIB_DCUC"].add_enum("CIB.JD0MUX", "0"); + cc.tiles["CIB_R94C49:VCIB_DCUC"].add_enum("CIB.JD2MUX", "0"); + cc.tiles["CIB_R94C49:VCIB_DCUC"].add_enum("CIB.JD4MUX", "0"); + cc.tiles["CIB_R94C49:VCIB_DCUC"].add_enum("CIB.JD6MUX", "0"); + cc.tiles["CIB_R94C50:VCIB_DCUD"].add_enum("CIB.JA1MUX", "0"); + cc.tiles["CIB_R94C50:VCIB_DCUD"].add_enum("CIB.JA5MUX", "0"); + cc.tiles["CIB_R94C50:VCIB_DCUD"].add_enum("CIB.JA7MUX", "0"); + cc.tiles["CIB_R94C50:VCIB_DCUD"].add_enum("CIB.JB1MUX", "0"); + cc.tiles["CIB_R94C50:VCIB_DCUD"].add_enum("CIB.JB3MUX", "0"); + cc.tiles["CIB_R94C50:VCIB_DCUD"].add_enum("CIB.JB5MUX", "0"); + cc.tiles["CIB_R94C50:VCIB_DCUD"].add_enum("CIB.JB7MUX", "0"); + cc.tiles["CIB_R94C50:VCIB_DCUD"].add_enum("CIB.JC0MUX", "0"); + cc.tiles["CIB_R94C50:VCIB_DCUD"].add_enum("CIB.JC2MUX", "0"); + cc.tiles["CIB_R94C50:VCIB_DCUD"].add_enum("CIB.JC4MUX", "0"); + cc.tiles["CIB_R94C50:VCIB_DCUD"].add_enum("CIB.JC6MUX", "0"); + cc.tiles["CIB_R94C50:VCIB_DCUD"].add_enum("CIB.JD0MUX", "0"); + cc.tiles["CIB_R94C50:VCIB_DCUD"].add_enum("CIB.JD2MUX", "0"); + cc.tiles["CIB_R94C50:VCIB_DCUD"].add_enum("CIB.JD4MUX", "0"); + cc.tiles["CIB_R94C50:VCIB_DCUD"].add_enum("CIB.JD6MUX", "0"); + cc.tiles["CIB_R94C51:VCIB_DCUF"].add_enum("CIB.JA1MUX", "0"); + cc.tiles["CIB_R94C51:VCIB_DCUF"].add_enum("CIB.JA3MUX", "0"); + cc.tiles["CIB_R94C51:VCIB_DCUF"].add_enum("CIB.JA5MUX", "0"); + cc.tiles["CIB_R94C51:VCIB_DCUF"].add_enum("CIB.JA7MUX", "0"); + cc.tiles["CIB_R94C51:VCIB_DCUF"].add_enum("CIB.JB1MUX", "0"); + cc.tiles["CIB_R94C51:VCIB_DCUF"].add_enum("CIB.JB3MUX", "0"); + cc.tiles["CIB_R94C51:VCIB_DCUF"].add_enum("CIB.JB5MUX", "0"); + cc.tiles["CIB_R94C51:VCIB_DCUF"].add_enum("CIB.JB7MUX", "0"); + cc.tiles["CIB_R94C51:VCIB_DCUF"].add_enum("CIB.JC0MUX", "0"); + cc.tiles["CIB_R94C51:VCIB_DCUF"].add_enum("CIB.JC2MUX", "0"); + cc.tiles["CIB_R94C51:VCIB_DCUF"].add_enum("CIB.JC4MUX", "0"); + cc.tiles["CIB_R94C51:VCIB_DCUF"].add_enum("CIB.JC6MUX", "0"); + cc.tiles["CIB_R94C51:VCIB_DCUF"].add_enum("CIB.JD0MUX", "0"); + cc.tiles["CIB_R94C51:VCIB_DCUF"].add_enum("CIB.JD2MUX", "0"); + cc.tiles["CIB_R94C51:VCIB_DCUF"].add_enum("CIB.JD4MUX", "0"); + cc.tiles["CIB_R94C51:VCIB_DCUF"].add_enum("CIB.JD6MUX", "0"); + cc.tiles["CIB_R94C52:VCIB_DCU3"].add_enum("CIB.JA5MUX", "0"); + cc.tiles["CIB_R94C52:VCIB_DCU3"].add_enum("CIB.JA7MUX", "0"); + cc.tiles["CIB_R94C52:VCIB_DCU3"].add_enum("CIB.JB1MUX", "0"); + cc.tiles["CIB_R94C52:VCIB_DCU3"].add_enum("CIB.JB3MUX", "0"); + cc.tiles["CIB_R94C52:VCIB_DCU3"].add_enum("CIB.JB5MUX", "0"); + cc.tiles["CIB_R94C52:VCIB_DCU3"].add_enum("CIB.JB7MUX", "0"); + cc.tiles["CIB_R94C52:VCIB_DCU3"].add_enum("CIB.JC0MUX", "0"); + cc.tiles["CIB_R94C52:VCIB_DCU3"].add_enum("CIB.JC4MUX", "0"); + cc.tiles["CIB_R94C52:VCIB_DCU3"].add_enum("CIB.JC6MUX", "0"); + cc.tiles["CIB_R94C52:VCIB_DCU3"].add_enum("CIB.JD0MUX", "0"); + cc.tiles["CIB_R94C52:VCIB_DCU3"].add_enum("CIB.JD2MUX", "0"); + cc.tiles["CIB_R94C52:VCIB_DCU3"].add_enum("CIB.JD4MUX", "0"); + cc.tiles["CIB_R94C52:VCIB_DCU3"].add_enum("CIB.JD6MUX", "0"); + cc.tiles["CIB_R94C53:VCIB_DCU2"].add_enum("CIB.JB1MUX", "0"); + cc.tiles["CIB_R94C53:VCIB_DCU2"].add_enum("CIB.JB3MUX", "0"); + cc.tiles["CIB_R94C53:VCIB_DCU2"].add_enum("CIB.JB5MUX", "0"); + cc.tiles["CIB_R94C53:VCIB_DCU2"].add_enum("CIB.JB7MUX", "0"); + cc.tiles["CIB_R94C53:VCIB_DCU2"].add_enum("CIB.JD0MUX", "0"); + cc.tiles["CIB_R94C53:VCIB_DCU2"].add_enum("CIB.JD2MUX", "0"); + cc.tiles["CIB_R94C53:VCIB_DCU2"].add_enum("CIB.JD4MUX", "0"); + cc.tiles["CIB_R94C53:VCIB_DCU2"].add_enum("CIB.JD6MUX", "0"); + cc.tiles["CIB_R94C54:VCIB_DCUG"].add_enum("CIB.JB1MUX", "0"); + cc.tiles["CIB_R94C54:VCIB_DCUG"].add_enum("CIB.JB3MUX", "0"); + cc.tiles["CIB_R94C54:VCIB_DCUG"].add_enum("CIB.JB5MUX", "0"); + cc.tiles["CIB_R94C54:VCIB_DCUG"].add_enum("CIB.JB7MUX", "0"); + cc.tiles["CIB_R94C54:VCIB_DCUG"].add_enum("CIB.JD0MUX", "0"); + cc.tiles["CIB_R94C54:VCIB_DCUG"].add_enum("CIB.JD2MUX", "0"); + cc.tiles["CIB_R94C54:VCIB_DCUG"].add_enum("CIB.JD4MUX", "0"); + cc.tiles["CIB_R94C54:VCIB_DCUG"].add_enum("CIB.JD6MUX", "0"); + cc.tiles["CIB_R94C55:VCIB_DCUH"].add_enum("CIB.JB1MUX", "0"); + cc.tiles["CIB_R94C55:VCIB_DCUH"].add_enum("CIB.JB3MUX", "0"); + cc.tiles["CIB_R94C55:VCIB_DCUH"].add_enum("CIB.JB5MUX", "0"); + cc.tiles["CIB_R94C55:VCIB_DCUH"].add_enum("CIB.JB7MUX", "0"); + cc.tiles["CIB_R94C55:VCIB_DCUH"].add_enum("CIB.JD0MUX", "0"); + cc.tiles["CIB_R94C55:VCIB_DCUH"].add_enum("CIB.JD2MUX", "0"); + cc.tiles["CIB_R94C55:VCIB_DCUH"].add_enum("CIB.JD4MUX", "0"); + cc.tiles["CIB_R94C55:VCIB_DCUH"].add_enum("CIB.JD6MUX", "0"); + cc.tiles["CIB_R94C56:VCIB_DCUI"].add_enum("CIB.JB1MUX", "0"); + cc.tiles["CIB_R94C56:VCIB_DCUI"].add_enum("CIB.JB3MUX", "0"); + cc.tiles["CIB_R94C56:VCIB_DCUI"].add_enum("CIB.JB5MUX", "0"); + cc.tiles["CIB_R94C56:VCIB_DCUI"].add_enum("CIB.JB7MUX", "0"); + cc.tiles["CIB_R94C56:VCIB_DCUI"].add_enum("CIB.JD0MUX", "0"); + cc.tiles["CIB_R94C56:VCIB_DCUI"].add_enum("CIB.JD2MUX", "0"); + cc.tiles["CIB_R94C56:VCIB_DCUI"].add_enum("CIB.JD4MUX", "0"); + cc.tiles["CIB_R94C56:VCIB_DCUI"].add_enum("CIB.JD6MUX", "0"); + cc.tiles["CIB_R94C57:VCIB_DCU1"].add_enum("CIB.JB1MUX", "0"); + cc.tiles["CIB_R94C57:VCIB_DCU1"].add_enum("CIB.JB3MUX", "0"); + cc.tiles["CIB_R94C57:VCIB_DCU1"].add_enum("CIB.JB5MUX", "0"); + cc.tiles["CIB_R94C57:VCIB_DCU1"].add_enum("CIB.JD0MUX", "0"); + cc.tiles["CIB_R94C57:VCIB_DCU1"].add_enum("CIB.JD2MUX", "0"); + cc.tiles["CIB_R94C6:CIB_EFB0"].add_enum("CIB.JB3MUX", "0"); + cc.tiles["CIB_R94C6:CIB_EFB0"].add_enum("CIB.JC6MUX", "0"); + cc.tiles["CIB_R94C6:CIB_EFB0"].add_enum("CIB.JD6MUX", "0"); + cc.tiles["CIB_R94C71:VCIB_DCU0"].add_enum("CIB.JA1MUX", "0"); + cc.tiles["CIB_R94C71:VCIB_DCU0"].add_enum("CIB.JA3MUX", "0"); + cc.tiles["CIB_R94C71:VCIB_DCU0"].add_enum("CIB.JA5MUX", "0"); + cc.tiles["CIB_R94C71:VCIB_DCU0"].add_enum("CIB.JA7MUX", "0"); + cc.tiles["CIB_R94C71:VCIB_DCU0"].add_enum("CIB.JB1MUX", "0"); + cc.tiles["CIB_R94C71:VCIB_DCU0"].add_enum("CIB.JB3MUX", "0"); + cc.tiles["CIB_R94C71:VCIB_DCU0"].add_enum("CIB.JB5MUX", "0"); + cc.tiles["CIB_R94C71:VCIB_DCU0"].add_enum("CIB.JB7MUX", "0"); + cc.tiles["CIB_R94C71:VCIB_DCU0"].add_enum("CIB.JC0MUX", "0"); + cc.tiles["CIB_R94C71:VCIB_DCU0"].add_enum("CIB.JC2MUX", "0"); + cc.tiles["CIB_R94C71:VCIB_DCU0"].add_enum("CIB.JC4MUX", "0"); + cc.tiles["CIB_R94C71:VCIB_DCU0"].add_enum("CIB.JC6MUX", "0"); + cc.tiles["CIB_R94C71:VCIB_DCU0"].add_enum("CIB.JD0MUX", "0"); + cc.tiles["CIB_R94C71:VCIB_DCU0"].add_enum("CIB.JD2MUX", "0"); + cc.tiles["CIB_R94C71:VCIB_DCU0"].add_enum("CIB.JD4MUX", "0"); + cc.tiles["CIB_R94C71:VCIB_DCU0"].add_enum("CIB.JD6MUX", "0"); + cc.tiles["CIB_R94C72:VCIB_DCUA"].add_enum("CIB.JA1MUX", "0"); + cc.tiles["CIB_R94C72:VCIB_DCUA"].add_enum("CIB.JA3MUX", "0"); + cc.tiles["CIB_R94C72:VCIB_DCUA"].add_enum("CIB.JA5MUX", "0"); + cc.tiles["CIB_R94C72:VCIB_DCUA"].add_enum("CIB.JA7MUX", "0"); + cc.tiles["CIB_R94C72:VCIB_DCUA"].add_enum("CIB.JB1MUX", "0"); + cc.tiles["CIB_R94C72:VCIB_DCUA"].add_enum("CIB.JB3MUX", "0"); + cc.tiles["CIB_R94C72:VCIB_DCUA"].add_enum("CIB.JB5MUX", "0"); + cc.tiles["CIB_R94C72:VCIB_DCUA"].add_enum("CIB.JB7MUX", "0"); + cc.tiles["CIB_R94C72:VCIB_DCUA"].add_enum("CIB.JC0MUX", "0"); + cc.tiles["CIB_R94C72:VCIB_DCUA"].add_enum("CIB.JC2MUX", "0"); + cc.tiles["CIB_R94C72:VCIB_DCUA"].add_enum("CIB.JC4MUX", "0"); + cc.tiles["CIB_R94C72:VCIB_DCUA"].add_enum("CIB.JC6MUX", "0"); + cc.tiles["CIB_R94C72:VCIB_DCUA"].add_enum("CIB.JD0MUX", "0"); + cc.tiles["CIB_R94C72:VCIB_DCUA"].add_enum("CIB.JD2MUX", "0"); + cc.tiles["CIB_R94C72:VCIB_DCUA"].add_enum("CIB.JD4MUX", "0"); + cc.tiles["CIB_R94C72:VCIB_DCUA"].add_enum("CIB.JD6MUX", "0"); + cc.tiles["CIB_R94C73:VCIB_DCUB"].add_enum("CIB.JA1MUX", "0"); + cc.tiles["CIB_R94C73:VCIB_DCUB"].add_enum("CIB.JA3MUX", "0"); + cc.tiles["CIB_R94C73:VCIB_DCUB"].add_enum("CIB.JA5MUX", "0"); + cc.tiles["CIB_R94C73:VCIB_DCUB"].add_enum("CIB.JA7MUX", "0"); + cc.tiles["CIB_R94C73:VCIB_DCUB"].add_enum("CIB.JB1MUX", "0"); + cc.tiles["CIB_R94C73:VCIB_DCUB"].add_enum("CIB.JB3MUX", "0"); + cc.tiles["CIB_R94C73:VCIB_DCUB"].add_enum("CIB.JB5MUX", "0"); + cc.tiles["CIB_R94C73:VCIB_DCUB"].add_enum("CIB.JB7MUX", "0"); + cc.tiles["CIB_R94C73:VCIB_DCUB"].add_enum("CIB.JC0MUX", "0"); + cc.tiles["CIB_R94C73:VCIB_DCUB"].add_enum("CIB.JC2MUX", "0"); + cc.tiles["CIB_R94C73:VCIB_DCUB"].add_enum("CIB.JC4MUX", "0"); + cc.tiles["CIB_R94C73:VCIB_DCUB"].add_enum("CIB.JC6MUX", "0"); + cc.tiles["CIB_R94C73:VCIB_DCUB"].add_enum("CIB.JD0MUX", "0"); + cc.tiles["CIB_R94C73:VCIB_DCUB"].add_enum("CIB.JD2MUX", "0"); + cc.tiles["CIB_R94C73:VCIB_DCUB"].add_enum("CIB.JD4MUX", "0"); + cc.tiles["CIB_R94C73:VCIB_DCUB"].add_enum("CIB.JD6MUX", "0"); + cc.tiles["CIB_R94C74:VCIB_DCUC"].add_enum("CIB.JA1MUX", "0"); + cc.tiles["CIB_R94C74:VCIB_DCUC"].add_enum("CIB.JA3MUX", "0"); + cc.tiles["CIB_R94C74:VCIB_DCUC"].add_enum("CIB.JA5MUX", "0"); + cc.tiles["CIB_R94C74:VCIB_DCUC"].add_enum("CIB.JA7MUX", "0"); + cc.tiles["CIB_R94C74:VCIB_DCUC"].add_enum("CIB.JB1MUX", "0"); + cc.tiles["CIB_R94C74:VCIB_DCUC"].add_enum("CIB.JB3MUX", "0"); + cc.tiles["CIB_R94C74:VCIB_DCUC"].add_enum("CIB.JB5MUX", "0"); + cc.tiles["CIB_R94C74:VCIB_DCUC"].add_enum("CIB.JB7MUX", "0"); + cc.tiles["CIB_R94C74:VCIB_DCUC"].add_enum("CIB.JC0MUX", "0"); + cc.tiles["CIB_R94C74:VCIB_DCUC"].add_enum("CIB.JC2MUX", "0"); + cc.tiles["CIB_R94C74:VCIB_DCUC"].add_enum("CIB.JC4MUX", "0"); + cc.tiles["CIB_R94C74:VCIB_DCUC"].add_enum("CIB.JC6MUX", "0"); + cc.tiles["CIB_R94C74:VCIB_DCUC"].add_enum("CIB.JD0MUX", "0"); + cc.tiles["CIB_R94C74:VCIB_DCUC"].add_enum("CIB.JD2MUX", "0"); + cc.tiles["CIB_R94C74:VCIB_DCUC"].add_enum("CIB.JD4MUX", "0"); + cc.tiles["CIB_R94C74:VCIB_DCUC"].add_enum("CIB.JD6MUX", "0"); + cc.tiles["CIB_R94C75:VCIB_DCUD"].add_enum("CIB.JA1MUX", "0"); + cc.tiles["CIB_R94C75:VCIB_DCUD"].add_enum("CIB.JA5MUX", "0"); + cc.tiles["CIB_R94C75:VCIB_DCUD"].add_enum("CIB.JA7MUX", "0"); + cc.tiles["CIB_R94C75:VCIB_DCUD"].add_enum("CIB.JB1MUX", "0"); + cc.tiles["CIB_R94C75:VCIB_DCUD"].add_enum("CIB.JB3MUX", "0"); + cc.tiles["CIB_R94C75:VCIB_DCUD"].add_enum("CIB.JB5MUX", "0"); + cc.tiles["CIB_R94C75:VCIB_DCUD"].add_enum("CIB.JB7MUX", "0"); + cc.tiles["CIB_R94C75:VCIB_DCUD"].add_enum("CIB.JC0MUX", "0"); + cc.tiles["CIB_R94C75:VCIB_DCUD"].add_enum("CIB.JC2MUX", "0"); + cc.tiles["CIB_R94C75:VCIB_DCUD"].add_enum("CIB.JC4MUX", "0"); + cc.tiles["CIB_R94C75:VCIB_DCUD"].add_enum("CIB.JC6MUX", "0"); + cc.tiles["CIB_R94C75:VCIB_DCUD"].add_enum("CIB.JD0MUX", "0"); + cc.tiles["CIB_R94C75:VCIB_DCUD"].add_enum("CIB.JD2MUX", "0"); + cc.tiles["CIB_R94C75:VCIB_DCUD"].add_enum("CIB.JD4MUX", "0"); + cc.tiles["CIB_R94C75:VCIB_DCUD"].add_enum("CIB.JD6MUX", "0"); + cc.tiles["CIB_R94C76:VCIB_DCUF"].add_enum("CIB.JA1MUX", "0"); + cc.tiles["CIB_R94C76:VCIB_DCUF"].add_enum("CIB.JA3MUX", "0"); + cc.tiles["CIB_R94C76:VCIB_DCUF"].add_enum("CIB.JA5MUX", "0"); + cc.tiles["CIB_R94C76:VCIB_DCUF"].add_enum("CIB.JA7MUX", "0"); + cc.tiles["CIB_R94C76:VCIB_DCUF"].add_enum("CIB.JB1MUX", "0"); + cc.tiles["CIB_R94C76:VCIB_DCUF"].add_enum("CIB.JB3MUX", "0"); + cc.tiles["CIB_R94C76:VCIB_DCUF"].add_enum("CIB.JB5MUX", "0"); + cc.tiles["CIB_R94C76:VCIB_DCUF"].add_enum("CIB.JB7MUX", "0"); + cc.tiles["CIB_R94C76:VCIB_DCUF"].add_enum("CIB.JC0MUX", "0"); + cc.tiles["CIB_R94C76:VCIB_DCUF"].add_enum("CIB.JC2MUX", "0"); + cc.tiles["CIB_R94C76:VCIB_DCUF"].add_enum("CIB.JC4MUX", "0"); + cc.tiles["CIB_R94C76:VCIB_DCUF"].add_enum("CIB.JC6MUX", "0"); + cc.tiles["CIB_R94C76:VCIB_DCUF"].add_enum("CIB.JD0MUX", "0"); + cc.tiles["CIB_R94C76:VCIB_DCUF"].add_enum("CIB.JD2MUX", "0"); + cc.tiles["CIB_R94C76:VCIB_DCUF"].add_enum("CIB.JD4MUX", "0"); + cc.tiles["CIB_R94C76:VCIB_DCUF"].add_enum("CIB.JD6MUX", "0"); + cc.tiles["CIB_R94C77:VCIB_DCU3"].add_enum("CIB.JA5MUX", "0"); + cc.tiles["CIB_R94C77:VCIB_DCU3"].add_enum("CIB.JA7MUX", "0"); + cc.tiles["CIB_R94C77:VCIB_DCU3"].add_enum("CIB.JB1MUX", "0"); + cc.tiles["CIB_R94C77:VCIB_DCU3"].add_enum("CIB.JB3MUX", "0"); + cc.tiles["CIB_R94C77:VCIB_DCU3"].add_enum("CIB.JB5MUX", "0"); + cc.tiles["CIB_R94C77:VCIB_DCU3"].add_enum("CIB.JB7MUX", "0"); + cc.tiles["CIB_R94C77:VCIB_DCU3"].add_enum("CIB.JC0MUX", "0"); + cc.tiles["CIB_R94C77:VCIB_DCU3"].add_enum("CIB.JC4MUX", "0"); + cc.tiles["CIB_R94C77:VCIB_DCU3"].add_enum("CIB.JC6MUX", "0"); + cc.tiles["CIB_R94C77:VCIB_DCU3"].add_enum("CIB.JD0MUX", "0"); + cc.tiles["CIB_R94C77:VCIB_DCU3"].add_enum("CIB.JD2MUX", "0"); + cc.tiles["CIB_R94C77:VCIB_DCU3"].add_enum("CIB.JD4MUX", "0"); + cc.tiles["CIB_R94C77:VCIB_DCU3"].add_enum("CIB.JD6MUX", "0"); + cc.tiles["CIB_R94C78:VCIB_DCU2"].add_enum("CIB.JB1MUX", "0"); + cc.tiles["CIB_R94C78:VCIB_DCU2"].add_enum("CIB.JB3MUX", "0"); + cc.tiles["CIB_R94C78:VCIB_DCU2"].add_enum("CIB.JB5MUX", "0"); + cc.tiles["CIB_R94C78:VCIB_DCU2"].add_enum("CIB.JB7MUX", "0"); + cc.tiles["CIB_R94C78:VCIB_DCU2"].add_enum("CIB.JD0MUX", "0"); + cc.tiles["CIB_R94C78:VCIB_DCU2"].add_enum("CIB.JD2MUX", "0"); + cc.tiles["CIB_R94C78:VCIB_DCU2"].add_enum("CIB.JD4MUX", "0"); + cc.tiles["CIB_R94C78:VCIB_DCU2"].add_enum("CIB.JD6MUX", "0"); + cc.tiles["CIB_R94C79:VCIB_DCUG"].add_enum("CIB.JB1MUX", "0"); + cc.tiles["CIB_R94C79:VCIB_DCUG"].add_enum("CIB.JB3MUX", "0"); + cc.tiles["CIB_R94C79:VCIB_DCUG"].add_enum("CIB.JB5MUX", "0"); + cc.tiles["CIB_R94C79:VCIB_DCUG"].add_enum("CIB.JB7MUX", "0"); + cc.tiles["CIB_R94C79:VCIB_DCUG"].add_enum("CIB.JD0MUX", "0"); + cc.tiles["CIB_R94C79:VCIB_DCUG"].add_enum("CIB.JD2MUX", "0"); + cc.tiles["CIB_R94C79:VCIB_DCUG"].add_enum("CIB.JD4MUX", "0"); + cc.tiles["CIB_R94C79:VCIB_DCUG"].add_enum("CIB.JD6MUX", "0"); + cc.tiles["CIB_R94C7:CIB_EFB1"].add_enum("CIB.JA3MUX", "0"); + cc.tiles["CIB_R94C7:CIB_EFB1"].add_enum("CIB.JA4MUX", "0"); + cc.tiles["CIB_R94C7:CIB_EFB1"].add_enum("CIB.JA5MUX", "0"); + cc.tiles["CIB_R94C7:CIB_EFB1"].add_enum("CIB.JA6MUX", "0"); + cc.tiles["CIB_R94C7:CIB_EFB1"].add_enum("CIB.JB3MUX", "0"); + cc.tiles["CIB_R94C7:CIB_EFB1"].add_enum("CIB.JB4MUX", "0"); + cc.tiles["CIB_R94C7:CIB_EFB1"].add_enum("CIB.JB5MUX", "0"); + cc.tiles["CIB_R94C7:CIB_EFB1"].add_enum("CIB.JB6MUX", "0"); + cc.tiles["CIB_R94C7:CIB_EFB1"].add_enum("CIB.JC3MUX", "0"); + cc.tiles["CIB_R94C7:CIB_EFB1"].add_enum("CIB.JC4MUX", "0"); + cc.tiles["CIB_R94C7:CIB_EFB1"].add_enum("CIB.JC5MUX", "0"); + cc.tiles["CIB_R94C7:CIB_EFB1"].add_enum("CIB.JD3MUX", "0"); + cc.tiles["CIB_R94C7:CIB_EFB1"].add_enum("CIB.JD4MUX", "0"); + cc.tiles["CIB_R94C7:CIB_EFB1"].add_enum("CIB.JD5MUX", "0"); + cc.tiles["CIB_R94C80:VCIB_DCUH"].add_enum("CIB.JB1MUX", "0"); + cc.tiles["CIB_R94C80:VCIB_DCUH"].add_enum("CIB.JB3MUX", "0"); + cc.tiles["CIB_R94C80:VCIB_DCUH"].add_enum("CIB.JB5MUX", "0"); + cc.tiles["CIB_R94C80:VCIB_DCUH"].add_enum("CIB.JB7MUX", "0"); + cc.tiles["CIB_R94C80:VCIB_DCUH"].add_enum("CIB.JD0MUX", "0"); + cc.tiles["CIB_R94C80:VCIB_DCUH"].add_enum("CIB.JD2MUX", "0"); + cc.tiles["CIB_R94C80:VCIB_DCUH"].add_enum("CIB.JD4MUX", "0"); + cc.tiles["CIB_R94C80:VCIB_DCUH"].add_enum("CIB.JD6MUX", "0"); + cc.tiles["CIB_R94C81:VCIB_DCUI"].add_enum("CIB.JB1MUX", "0"); + cc.tiles["CIB_R94C81:VCIB_DCUI"].add_enum("CIB.JB3MUX", "0"); + cc.tiles["CIB_R94C81:VCIB_DCUI"].add_enum("CIB.JB5MUX", "0"); + cc.tiles["CIB_R94C81:VCIB_DCUI"].add_enum("CIB.JB7MUX", "0"); + cc.tiles["CIB_R94C81:VCIB_DCUI"].add_enum("CIB.JD0MUX", "0"); + cc.tiles["CIB_R94C81:VCIB_DCUI"].add_enum("CIB.JD2MUX", "0"); + cc.tiles["CIB_R94C81:VCIB_DCUI"].add_enum("CIB.JD4MUX", "0"); + cc.tiles["CIB_R94C81:VCIB_DCUI"].add_enum("CIB.JD6MUX", "0"); + cc.tiles["CIB_R94C82:VCIB_DCU1"].add_enum("CIB.JB1MUX", "0"); + cc.tiles["CIB_R94C82:VCIB_DCU1"].add_enum("CIB.JB3MUX", "0"); + cc.tiles["CIB_R94C82:VCIB_DCU1"].add_enum("CIB.JB5MUX", "0"); + cc.tiles["CIB_R94C82:VCIB_DCU1"].add_enum("CIB.JD0MUX", "0"); + cc.tiles["CIB_R94C82:VCIB_DCU1"].add_enum("CIB.JD2MUX", "0"); + cc.tiles["MIB_R22C67:CMUX_UL_0"].add_arc("G_DCS0CLK0", "G_VPFN0000"); + cc.tiles["MIB_R22C68:CMUX_UR_0"].add_arc("G_DCS0CLK1", "G_VPFN0000"); + cc.tiles["MIB_R70C67:CMUX_LL_0"].add_arc("G_DCS1CLK0", "G_VPFN0000"); + cc.tiles["MIB_R70C68:CMUX_LR_0"].add_arc("G_DCS1CLK1", "G_VPFN0000"); + cc.tiles["MIB_R95C101:PICB0"].add_unknown(0, 1); + cc.tiles["MIB_R95C102:PICB1"].add_unknown(0, 1); + cc.tiles["MIB_R95C103:PICB0"].add_unknown(0, 1); + cc.tiles["MIB_R95C104:PICB1"].add_unknown(0, 1); + cc.tiles["MIB_R95C105:PICB0"].add_unknown(0, 1); + cc.tiles["MIB_R95C106:PICB1"].add_unknown(0, 1); + cc.tiles["MIB_R95C107:PICB0"].add_unknown(0, 1); + cc.tiles["MIB_R95C108:PICB1"].add_unknown(0, 1); + cc.tiles["MIB_R95C110:PICB0"].add_unknown(0, 1); + cc.tiles["MIB_R95C111:PICB1"].add_unknown(0, 1); + cc.tiles["MIB_R95C112:PICB0"].add_unknown(0, 1); + cc.tiles["MIB_R95C113:PICB1"].add_unknown(0, 1); + cc.tiles["MIB_R95C114:PICB0"].add_unknown(0, 1); + cc.tiles["MIB_R95C115:PICB1"].add_unknown(0, 1); + cc.tiles["MIB_R95C116:PICB0"].add_unknown(0, 1); + cc.tiles["MIB_R95C117:PICB1"].add_unknown(0, 1); + cc.tiles["MIB_R95C119:PICB0"].add_unknown(0, 1); + cc.tiles["MIB_R95C120:PICB1"].add_unknown(0, 1); + cc.tiles["MIB_R95C121:PICB0"].add_unknown(0, 1); + cc.tiles["MIB_R95C122:PICB1"].add_unknown(0, 1); + cc.tiles["MIB_R95C4:EFB0_PICB0"].add_unknown(54, 1); + cc.tiles["MIB_R95C4:EFB0_PICB0"].add_unknown(56, 1); + cc.tiles["MIB_R95C4:EFB0_PICB0"].add_unknown(82, 1); + cc.tiles["MIB_R95C4:EFB0_PICB0"].add_unknown(94, 1); + cc.tiles["MIB_R95C96:PICB0"].add_unknown(0, 1); + cc.tiles["MIB_R95C97:PICB1"].add_unknown(0, 1); + cc.tiles["MIB_R95C98:PICB0"].add_unknown(0, 1); + cc.tiles["MIB_R95C99:PICB1"].add_unknown(0, 1); +} + +void config_empty_lfe5um_25f(ChipConfig &cc) +{ + cc.chip_name = "LFE5UM-25F"; + cc.tiles["CIB_R49C3:CIB_PLL3"].add_enum("CIB.JA3MUX", "0"); + cc.tiles["CIB_R49C3:CIB_PLL3"].add_enum("CIB.JB3MUX", "0"); + cc.tiles["CIB_R49C42:CIB_DCU0"].add_unknown(20, 10); + cc.tiles["CIB_R49C42:CIB_DCU0"].add_unknown(21, 10); + cc.tiles["CIB_R49C42:CIB_DCU0"].add_unknown(22, 10); + cc.tiles["CIB_R49C42:CIB_DCU0"].add_unknown(23, 10); + cc.tiles["CIB_R49C42:CIB_DCU0"].add_unknown(28, 10); + cc.tiles["CIB_R49C42:CIB_DCU0"].add_unknown(29, 10); + cc.tiles["CIB_R49C42:CIB_DCU0"].add_unknown(30, 10); + cc.tiles["CIB_R49C42:CIB_DCU0"].add_unknown(31, 10); + cc.tiles["CIB_R49C42:CIB_DCU0"].add_unknown(74, 10); + cc.tiles["CIB_R49C42:CIB_DCU0"].add_unknown(75, 10); + cc.tiles["CIB_R49C42:CIB_DCU0"].add_unknown(76, 10); + cc.tiles["CIB_R49C42:CIB_DCU0"].add_unknown(77, 10); + cc.tiles["CIB_R49C42:CIB_DCU0"].add_unknown(82, 10); + cc.tiles["CIB_R49C42:CIB_DCU0"].add_unknown(83, 10); + cc.tiles["CIB_R49C42:CIB_DCU0"].add_unknown(84, 10); + cc.tiles["CIB_R49C42:CIB_DCU0"].add_unknown(85, 10); + cc.tiles["CIB_R49C43:CIB_DCUA"].add_unknown(20, 10); + cc.tiles["CIB_R49C43:CIB_DCUA"].add_unknown(21, 10); + cc.tiles["CIB_R49C43:CIB_DCUA"].add_unknown(22, 10); + cc.tiles["CIB_R49C43:CIB_DCUA"].add_unknown(23, 10); + cc.tiles["CIB_R49C43:CIB_DCUA"].add_unknown(28, 10); + cc.tiles["CIB_R49C43:CIB_DCUA"].add_unknown(29, 10); + cc.tiles["CIB_R49C43:CIB_DCUA"].add_unknown(30, 10); + cc.tiles["CIB_R49C43:CIB_DCUA"].add_unknown(31, 10); + cc.tiles["CIB_R49C43:CIB_DCUA"].add_unknown(74, 10); + cc.tiles["CIB_R49C43:CIB_DCUA"].add_unknown(75, 10); + cc.tiles["CIB_R49C43:CIB_DCUA"].add_unknown(76, 10); + cc.tiles["CIB_R49C43:CIB_DCUA"].add_unknown(77, 10); + cc.tiles["CIB_R49C43:CIB_DCUA"].add_unknown(82, 10); + cc.tiles["CIB_R49C43:CIB_DCUA"].add_unknown(83, 10); + cc.tiles["CIB_R49C43:CIB_DCUA"].add_unknown(84, 10); + cc.tiles["CIB_R49C43:CIB_DCUA"].add_unknown(85, 10); + cc.tiles["CIB_R49C44:CIB_DCUB"].add_unknown(20, 10); + cc.tiles["CIB_R49C44:CIB_DCUB"].add_unknown(21, 10); + cc.tiles["CIB_R49C44:CIB_DCUB"].add_unknown(22, 10); + cc.tiles["CIB_R49C44:CIB_DCUB"].add_unknown(23, 10); + cc.tiles["CIB_R49C44:CIB_DCUB"].add_unknown(28, 10); + cc.tiles["CIB_R49C44:CIB_DCUB"].add_unknown(29, 10); + cc.tiles["CIB_R49C44:CIB_DCUB"].add_unknown(30, 10); + cc.tiles["CIB_R49C44:CIB_DCUB"].add_unknown(31, 10); + cc.tiles["CIB_R49C44:CIB_DCUB"].add_unknown(74, 10); + cc.tiles["CIB_R49C44:CIB_DCUB"].add_unknown(75, 10); + cc.tiles["CIB_R49C44:CIB_DCUB"].add_unknown(76, 10); + cc.tiles["CIB_R49C44:CIB_DCUB"].add_unknown(77, 10); + cc.tiles["CIB_R49C44:CIB_DCUB"].add_unknown(82, 10); + cc.tiles["CIB_R49C44:CIB_DCUB"].add_unknown(83, 10); + cc.tiles["CIB_R49C44:CIB_DCUB"].add_unknown(84, 10); + cc.tiles["CIB_R49C44:CIB_DCUB"].add_unknown(85, 10); + cc.tiles["CIB_R49C45:CIB_DCUC"].add_unknown(20, 10); + cc.tiles["CIB_R49C45:CIB_DCUC"].add_unknown(21, 10); + cc.tiles["CIB_R49C45:CIB_DCUC"].add_unknown(22, 10); + cc.tiles["CIB_R49C45:CIB_DCUC"].add_unknown(23, 10); + cc.tiles["CIB_R49C45:CIB_DCUC"].add_unknown(28, 10); + cc.tiles["CIB_R49C45:CIB_DCUC"].add_unknown(29, 10); + cc.tiles["CIB_R49C45:CIB_DCUC"].add_unknown(30, 10); + cc.tiles["CIB_R49C45:CIB_DCUC"].add_unknown(31, 10); + cc.tiles["CIB_R49C45:CIB_DCUC"].add_unknown(74, 10); + cc.tiles["CIB_R49C45:CIB_DCUC"].add_unknown(75, 10); + cc.tiles["CIB_R49C45:CIB_DCUC"].add_unknown(76, 10); + cc.tiles["CIB_R49C45:CIB_DCUC"].add_unknown(77, 10); + cc.tiles["CIB_R49C45:CIB_DCUC"].add_unknown(82, 10); + cc.tiles["CIB_R49C45:CIB_DCUC"].add_unknown(83, 10); + cc.tiles["CIB_R49C45:CIB_DCUC"].add_unknown(84, 10); + cc.tiles["CIB_R49C45:CIB_DCUC"].add_unknown(85, 10); + cc.tiles["CIB_R49C46:CIB_DCUD"].add_unknown(20, 10); + cc.tiles["CIB_R49C46:CIB_DCUD"].add_unknown(21, 10); + cc.tiles["CIB_R49C46:CIB_DCUD"].add_unknown(22, 10); + cc.tiles["CIB_R49C46:CIB_DCUD"].add_unknown(23, 10); + cc.tiles["CIB_R49C46:CIB_DCUD"].add_unknown(28, 10); + cc.tiles["CIB_R49C46:CIB_DCUD"].add_unknown(29, 10); + cc.tiles["CIB_R49C46:CIB_DCUD"].add_unknown(31, 10); + cc.tiles["CIB_R49C46:CIB_DCUD"].add_unknown(74, 10); + cc.tiles["CIB_R49C46:CIB_DCUD"].add_unknown(75, 10); + cc.tiles["CIB_R49C46:CIB_DCUD"].add_unknown(76, 10); + cc.tiles["CIB_R49C46:CIB_DCUD"].add_unknown(77, 10); + cc.tiles["CIB_R49C46:CIB_DCUD"].add_unknown(82, 10); + cc.tiles["CIB_R49C46:CIB_DCUD"].add_unknown(83, 10); + cc.tiles["CIB_R49C46:CIB_DCUD"].add_unknown(84, 10); + cc.tiles["CIB_R49C46:CIB_DCUD"].add_unknown(85, 10); + cc.tiles["CIB_R49C47:CIB_DCUF"].add_unknown(20, 10); + cc.tiles["CIB_R49C47:CIB_DCUF"].add_unknown(21, 10); + cc.tiles["CIB_R49C47:CIB_DCUF"].add_unknown(22, 10); + cc.tiles["CIB_R49C47:CIB_DCUF"].add_unknown(23, 10); + cc.tiles["CIB_R49C47:CIB_DCUF"].add_unknown(28, 10); + cc.tiles["CIB_R49C47:CIB_DCUF"].add_unknown(29, 10); + cc.tiles["CIB_R49C47:CIB_DCUF"].add_unknown(30, 10); + cc.tiles["CIB_R49C47:CIB_DCUF"].add_unknown(31, 10); + cc.tiles["CIB_R49C47:CIB_DCUF"].add_unknown(74, 10); + cc.tiles["CIB_R49C47:CIB_DCUF"].add_unknown(75, 10); + cc.tiles["CIB_R49C47:CIB_DCUF"].add_unknown(76, 10); + cc.tiles["CIB_R49C47:CIB_DCUF"].add_unknown(77, 10); + cc.tiles["CIB_R49C47:CIB_DCUF"].add_unknown(82, 10); + cc.tiles["CIB_R49C47:CIB_DCUF"].add_unknown(83, 10); + cc.tiles["CIB_R49C47:CIB_DCUF"].add_unknown(84, 10); + cc.tiles["CIB_R49C47:CIB_DCUF"].add_unknown(85, 10); + cc.tiles["CIB_R49C48:CIB_DCU3"].add_unknown(20, 10); + cc.tiles["CIB_R49C48:CIB_DCU3"].add_unknown(22, 10); + cc.tiles["CIB_R49C48:CIB_DCU3"].add_unknown(23, 10); + cc.tiles["CIB_R49C48:CIB_DCU3"].add_unknown(29, 10); + cc.tiles["CIB_R49C48:CIB_DCU3"].add_unknown(31, 10); + cc.tiles["CIB_R49C48:CIB_DCU3"].add_unknown(74, 10); + cc.tiles["CIB_R49C48:CIB_DCU3"].add_unknown(75, 10); + cc.tiles["CIB_R49C48:CIB_DCU3"].add_unknown(76, 10); + cc.tiles["CIB_R49C48:CIB_DCU3"].add_unknown(77, 10); + cc.tiles["CIB_R49C48:CIB_DCU3"].add_unknown(82, 10); + cc.tiles["CIB_R49C48:CIB_DCU3"].add_unknown(83, 10); + cc.tiles["CIB_R49C48:CIB_DCU3"].add_unknown(84, 10); + cc.tiles["CIB_R49C48:CIB_DCU3"].add_unknown(85, 10); + cc.tiles["CIB_R49C49:CIB_DCU2"].add_unknown(20, 10); + cc.tiles["CIB_R49C49:CIB_DCU2"].add_unknown(22, 10); + cc.tiles["CIB_R49C49:CIB_DCU2"].add_unknown(29, 10); + cc.tiles["CIB_R49C49:CIB_DCU2"].add_unknown(31, 10); + cc.tiles["CIB_R49C49:CIB_DCU2"].add_unknown(74, 10); + cc.tiles["CIB_R49C49:CIB_DCU2"].add_unknown(76, 10); + cc.tiles["CIB_R49C49:CIB_DCU2"].add_unknown(83, 10); + cc.tiles["CIB_R49C49:CIB_DCU2"].add_unknown(85, 10); + cc.tiles["CIB_R49C50:CIB_DCUG"].add_unknown(20, 10); + cc.tiles["CIB_R49C50:CIB_DCUG"].add_unknown(22, 10); + cc.tiles["CIB_R49C50:CIB_DCUG"].add_unknown(29, 10); + cc.tiles["CIB_R49C50:CIB_DCUG"].add_unknown(31, 10); + cc.tiles["CIB_R49C50:CIB_DCUG"].add_unknown(74, 10); + cc.tiles["CIB_R49C50:CIB_DCUG"].add_unknown(76, 10); + cc.tiles["CIB_R49C50:CIB_DCUG"].add_unknown(83, 10); + cc.tiles["CIB_R49C50:CIB_DCUG"].add_unknown(85, 10); + cc.tiles["CIB_R49C51:CIB_DCUH"].add_unknown(20, 10); + cc.tiles["CIB_R49C51:CIB_DCUH"].add_unknown(22, 10); + cc.tiles["CIB_R49C51:CIB_DCUH"].add_unknown(29, 10); + cc.tiles["CIB_R49C51:CIB_DCUH"].add_unknown(31, 10); + cc.tiles["CIB_R49C51:CIB_DCUH"].add_unknown(74, 10); + cc.tiles["CIB_R49C51:CIB_DCUH"].add_unknown(76, 10); + cc.tiles["CIB_R49C51:CIB_DCUH"].add_unknown(83, 10); + cc.tiles["CIB_R49C51:CIB_DCUH"].add_unknown(85, 10); + cc.tiles["CIB_R49C52:CIB_DCUI"].add_unknown(20, 10); + cc.tiles["CIB_R49C52:CIB_DCUI"].add_unknown(22, 10); + cc.tiles["CIB_R49C52:CIB_DCUI"].add_unknown(29, 10); + cc.tiles["CIB_R49C52:CIB_DCUI"].add_unknown(31, 10); + cc.tiles["CIB_R49C52:CIB_DCUI"].add_unknown(74, 10); + cc.tiles["CIB_R49C52:CIB_DCUI"].add_unknown(76, 10); + cc.tiles["CIB_R49C52:CIB_DCUI"].add_unknown(83, 10); + cc.tiles["CIB_R49C52:CIB_DCUI"].add_unknown(85, 10); + cc.tiles["CIB_R49C53:CIB_DCU1"].add_unknown(20, 10); + cc.tiles["CIB_R49C53:CIB_DCU1"].add_unknown(22, 10); + cc.tiles["CIB_R49C53:CIB_DCU1"].add_unknown(29, 10); + cc.tiles["CIB_R49C53:CIB_DCU1"].add_unknown(31, 10); + cc.tiles["CIB_R49C53:CIB_DCU1"].add_unknown(74, 10); + cc.tiles["CIB_R49C69:CIB_PLL3"].add_enum("CIB.JA3MUX", "0"); + cc.tiles["CIB_R49C69:CIB_PLL3"].add_enum("CIB.JB3MUX", "0"); + cc.tiles["CIB_R49C6:CIB_EFB0"].add_enum("CIB.JB3MUX", "0"); + cc.tiles["CIB_R49C6:CIB_EFB0"].add_enum("CIB.JC6MUX", "0"); + cc.tiles["CIB_R49C6:CIB_EFB0"].add_enum("CIB.JD6MUX", "0"); + cc.tiles["CIB_R49C7:CIB_EFB1"].add_enum("CIB.JA3MUX", "0"); + cc.tiles["CIB_R49C7:CIB_EFB1"].add_enum("CIB.JA4MUX", "0"); + cc.tiles["CIB_R49C7:CIB_EFB1"].add_enum("CIB.JA5MUX", "0"); + cc.tiles["CIB_R49C7:CIB_EFB1"].add_enum("CIB.JA6MUX", "0"); + cc.tiles["CIB_R49C7:CIB_EFB1"].add_enum("CIB.JB3MUX", "0"); + cc.tiles["CIB_R49C7:CIB_EFB1"].add_enum("CIB.JB4MUX", "0"); + cc.tiles["CIB_R49C7:CIB_EFB1"].add_enum("CIB.JB5MUX", "0"); + cc.tiles["CIB_R49C7:CIB_EFB1"].add_enum("CIB.JB6MUX", "0"); + cc.tiles["CIB_R49C7:CIB_EFB1"].add_enum("CIB.JC3MUX", "0"); + cc.tiles["CIB_R49C7:CIB_EFB1"].add_enum("CIB.JC4MUX", "0"); + cc.tiles["CIB_R49C7:CIB_EFB1"].add_enum("CIB.JC5MUX", "0"); + cc.tiles["CIB_R49C7:CIB_EFB1"].add_enum("CIB.JD3MUX", "0"); + cc.tiles["CIB_R49C7:CIB_EFB1"].add_enum("CIB.JD4MUX", "0"); + cc.tiles["CIB_R49C7:CIB_EFB1"].add_enum("CIB.JD5MUX", "0"); + cc.tiles["MIB_R13C31:CMUX_UL_0"].add_arc("G_DCS0CLK0", "G_VPFN0000"); + cc.tiles["MIB_R13C32:CMUX_UR_0"].add_arc("G_DCS0CLK1", "G_VPFN0000"); + cc.tiles["MIB_R13C3:DSP_SPINE_UL1"].add_unknown(2, 0); + cc.tiles["MIB_R13C3:DSP_SPINE_UL1"].add_unknown(3, 0); + cc.tiles["MIB_R13C3:DSP_SPINE_UL1"].add_unknown(5, 0); + cc.tiles["MIB_R13C3:DSP_SPINE_UL1"].add_unknown(11, 0); + cc.tiles["MIB_R13C3:DSP_SPINE_UL1"].add_unknown(13, 0); + cc.tiles["MIB_R37C31:CMUX_LL_0"].add_arc("G_DCS1CLK0", "G_VPFN0000"); + cc.tiles["MIB_R37C32:CMUX_LR_0"].add_arc("G_DCS1CLK1", "G_VPFN0000"); + cc.tiles["MIB_R50C4:EFB0_PICB0"].add_unknown(54, 1); + cc.tiles["MIB_R50C4:EFB0_PICB0"].add_unknown(56, 1); + cc.tiles["MIB_R50C4:EFB0_PICB0"].add_unknown(82, 1); + cc.tiles["MIB_R50C4:EFB0_PICB0"].add_unknown(94, 1); +} + +void config_empty_lfe5um_45f(ChipConfig &cc) +{ + cc.chip_name = "LFE5UM-45F"; + cc.tiles["CIB_R10C3:PVT_COUNT2"].add_unknown(2, 0); + cc.tiles["CIB_R10C3:PVT_COUNT2"].add_unknown(3, 0); + cc.tiles["CIB_R10C3:PVT_COUNT2"].add_unknown(5, 0); + cc.tiles["CIB_R10C3:PVT_COUNT2"].add_unknown(11, 0); + cc.tiles["CIB_R10C3:PVT_COUNT2"].add_unknown(13, 0); + cc.tiles["CIB_R5C1:CIB_PLL1"].add_enum("CIB.JA3MUX", "0"); + cc.tiles["CIB_R5C1:CIB_PLL1"].add_enum("CIB.JB3MUX", "0"); + cc.tiles["CIB_R5C89:CIB_PLL1"].add_enum("CIB.JA3MUX", "0"); + cc.tiles["CIB_R5C89:CIB_PLL1"].add_enum("CIB.JB3MUX", "0"); + cc.tiles["CIB_R70C3:CIB_PLL3"].add_enum("CIB.JA3MUX", "0"); + cc.tiles["CIB_R70C3:CIB_PLL3"].add_enum("CIB.JB3MUX", "0"); + cc.tiles["CIB_R70C42:CIB_DCU0"].add_unknown(20, 10); + cc.tiles["CIB_R70C42:CIB_DCU0"].add_unknown(21, 10); + cc.tiles["CIB_R70C42:CIB_DCU0"].add_unknown(22, 10); + cc.tiles["CIB_R70C42:CIB_DCU0"].add_unknown(23, 10); + cc.tiles["CIB_R70C42:CIB_DCU0"].add_unknown(28, 10); + cc.tiles["CIB_R70C42:CIB_DCU0"].add_unknown(29, 10); + cc.tiles["CIB_R70C42:CIB_DCU0"].add_unknown(30, 10); + cc.tiles["CIB_R70C42:CIB_DCU0"].add_unknown(31, 10); + cc.tiles["CIB_R70C42:CIB_DCU0"].add_unknown(74, 10); + cc.tiles["CIB_R70C42:CIB_DCU0"].add_unknown(75, 10); + cc.tiles["CIB_R70C42:CIB_DCU0"].add_unknown(76, 10); + cc.tiles["CIB_R70C42:CIB_DCU0"].add_unknown(77, 10); + cc.tiles["CIB_R70C42:CIB_DCU0"].add_unknown(82, 10); + cc.tiles["CIB_R70C42:CIB_DCU0"].add_unknown(83, 10); + cc.tiles["CIB_R70C42:CIB_DCU0"].add_unknown(84, 10); + cc.tiles["CIB_R70C42:CIB_DCU0"].add_unknown(85, 10); + cc.tiles["CIB_R70C43:CIB_DCUA"].add_unknown(20, 10); + cc.tiles["CIB_R70C43:CIB_DCUA"].add_unknown(21, 10); + cc.tiles["CIB_R70C43:CIB_DCUA"].add_unknown(22, 10); + cc.tiles["CIB_R70C43:CIB_DCUA"].add_unknown(23, 10); + cc.tiles["CIB_R70C43:CIB_DCUA"].add_unknown(28, 10); + cc.tiles["CIB_R70C43:CIB_DCUA"].add_unknown(29, 10); + cc.tiles["CIB_R70C43:CIB_DCUA"].add_unknown(30, 10); + cc.tiles["CIB_R70C43:CIB_DCUA"].add_unknown(31, 10); + cc.tiles["CIB_R70C43:CIB_DCUA"].add_unknown(74, 10); + cc.tiles["CIB_R70C43:CIB_DCUA"].add_unknown(75, 10); + cc.tiles["CIB_R70C43:CIB_DCUA"].add_unknown(76, 10); + cc.tiles["CIB_R70C43:CIB_DCUA"].add_unknown(77, 10); + cc.tiles["CIB_R70C43:CIB_DCUA"].add_unknown(82, 10); + cc.tiles["CIB_R70C43:CIB_DCUA"].add_unknown(83, 10); + cc.tiles["CIB_R70C43:CIB_DCUA"].add_unknown(84, 10); + cc.tiles["CIB_R70C43:CIB_DCUA"].add_unknown(85, 10); + cc.tiles["CIB_R70C44:CIB_DCUB"].add_unknown(20, 10); + cc.tiles["CIB_R70C44:CIB_DCUB"].add_unknown(21, 10); + cc.tiles["CIB_R70C44:CIB_DCUB"].add_unknown(22, 10); + cc.tiles["CIB_R70C44:CIB_DCUB"].add_unknown(23, 10); + cc.tiles["CIB_R70C44:CIB_DCUB"].add_unknown(28, 10); + cc.tiles["CIB_R70C44:CIB_DCUB"].add_unknown(29, 10); + cc.tiles["CIB_R70C44:CIB_DCUB"].add_unknown(30, 10); + cc.tiles["CIB_R70C44:CIB_DCUB"].add_unknown(31, 10); + cc.tiles["CIB_R70C44:CIB_DCUB"].add_unknown(74, 10); + cc.tiles["CIB_R70C44:CIB_DCUB"].add_unknown(75, 10); + cc.tiles["CIB_R70C44:CIB_DCUB"].add_unknown(76, 10); + cc.tiles["CIB_R70C44:CIB_DCUB"].add_unknown(77, 10); + cc.tiles["CIB_R70C44:CIB_DCUB"].add_unknown(82, 10); + cc.tiles["CIB_R70C44:CIB_DCUB"].add_unknown(83, 10); + cc.tiles["CIB_R70C44:CIB_DCUB"].add_unknown(84, 10); + cc.tiles["CIB_R70C44:CIB_DCUB"].add_unknown(85, 10); + cc.tiles["CIB_R70C45:CIB_DCUC"].add_unknown(20, 10); + cc.tiles["CIB_R70C45:CIB_DCUC"].add_unknown(21, 10); + cc.tiles["CIB_R70C45:CIB_DCUC"].add_unknown(22, 10); + cc.tiles["CIB_R70C45:CIB_DCUC"].add_unknown(23, 10); + cc.tiles["CIB_R70C45:CIB_DCUC"].add_unknown(28, 10); + cc.tiles["CIB_R70C45:CIB_DCUC"].add_unknown(29, 10); + cc.tiles["CIB_R70C45:CIB_DCUC"].add_unknown(30, 10); + cc.tiles["CIB_R70C45:CIB_DCUC"].add_unknown(31, 10); + cc.tiles["CIB_R70C45:CIB_DCUC"].add_unknown(74, 10); + cc.tiles["CIB_R70C45:CIB_DCUC"].add_unknown(75, 10); + cc.tiles["CIB_R70C45:CIB_DCUC"].add_unknown(76, 10); + cc.tiles["CIB_R70C45:CIB_DCUC"].add_unknown(77, 10); + cc.tiles["CIB_R70C45:CIB_DCUC"].add_unknown(82, 10); + cc.tiles["CIB_R70C45:CIB_DCUC"].add_unknown(83, 10); + cc.tiles["CIB_R70C45:CIB_DCUC"].add_unknown(84, 10); + cc.tiles["CIB_R70C45:CIB_DCUC"].add_unknown(85, 10); + cc.tiles["CIB_R70C46:CIB_DCUD"].add_unknown(20, 10); + cc.tiles["CIB_R70C46:CIB_DCUD"].add_unknown(21, 10); + cc.tiles["CIB_R70C46:CIB_DCUD"].add_unknown(22, 10); + cc.tiles["CIB_R70C46:CIB_DCUD"].add_unknown(23, 10); + cc.tiles["CIB_R70C46:CIB_DCUD"].add_unknown(28, 10); + cc.tiles["CIB_R70C46:CIB_DCUD"].add_unknown(29, 10); + cc.tiles["CIB_R70C46:CIB_DCUD"].add_unknown(31, 10); + cc.tiles["CIB_R70C46:CIB_DCUD"].add_unknown(74, 10); + cc.tiles["CIB_R70C46:CIB_DCUD"].add_unknown(75, 10); + cc.tiles["CIB_R70C46:CIB_DCUD"].add_unknown(76, 10); + cc.tiles["CIB_R70C46:CIB_DCUD"].add_unknown(77, 10); + cc.tiles["CIB_R70C46:CIB_DCUD"].add_unknown(82, 10); + cc.tiles["CIB_R70C46:CIB_DCUD"].add_unknown(83, 10); + cc.tiles["CIB_R70C46:CIB_DCUD"].add_unknown(84, 10); + cc.tiles["CIB_R70C46:CIB_DCUD"].add_unknown(85, 10); + cc.tiles["CIB_R70C47:CIB_DCUF"].add_unknown(20, 10); + cc.tiles["CIB_R70C47:CIB_DCUF"].add_unknown(21, 10); + cc.tiles["CIB_R70C47:CIB_DCUF"].add_unknown(22, 10); + cc.tiles["CIB_R70C47:CIB_DCUF"].add_unknown(23, 10); + cc.tiles["CIB_R70C47:CIB_DCUF"].add_unknown(28, 10); + cc.tiles["CIB_R70C47:CIB_DCUF"].add_unknown(29, 10); + cc.tiles["CIB_R70C47:CIB_DCUF"].add_unknown(30, 10); + cc.tiles["CIB_R70C47:CIB_DCUF"].add_unknown(31, 10); + cc.tiles["CIB_R70C47:CIB_DCUF"].add_unknown(74, 10); + cc.tiles["CIB_R70C47:CIB_DCUF"].add_unknown(75, 10); + cc.tiles["CIB_R70C47:CIB_DCUF"].add_unknown(76, 10); + cc.tiles["CIB_R70C47:CIB_DCUF"].add_unknown(77, 10); + cc.tiles["CIB_R70C47:CIB_DCUF"].add_unknown(82, 10); + cc.tiles["CIB_R70C47:CIB_DCUF"].add_unknown(83, 10); + cc.tiles["CIB_R70C47:CIB_DCUF"].add_unknown(84, 10); + cc.tiles["CIB_R70C47:CIB_DCUF"].add_unknown(85, 10); + cc.tiles["CIB_R70C48:CIB_DCU3"].add_unknown(20, 10); + cc.tiles["CIB_R70C48:CIB_DCU3"].add_unknown(22, 10); + cc.tiles["CIB_R70C48:CIB_DCU3"].add_unknown(23, 10); + cc.tiles["CIB_R70C48:CIB_DCU3"].add_unknown(29, 10); + cc.tiles["CIB_R70C48:CIB_DCU3"].add_unknown(31, 10); + cc.tiles["CIB_R70C48:CIB_DCU3"].add_unknown(74, 10); + cc.tiles["CIB_R70C48:CIB_DCU3"].add_unknown(75, 10); + cc.tiles["CIB_R70C48:CIB_DCU3"].add_unknown(76, 10); + cc.tiles["CIB_R70C48:CIB_DCU3"].add_unknown(77, 10); + cc.tiles["CIB_R70C48:CIB_DCU3"].add_unknown(82, 10); + cc.tiles["CIB_R70C48:CIB_DCU3"].add_unknown(83, 10); + cc.tiles["CIB_R70C48:CIB_DCU3"].add_unknown(84, 10); + cc.tiles["CIB_R70C48:CIB_DCU3"].add_unknown(85, 10); + cc.tiles["CIB_R70C49:CIB_DCU2"].add_unknown(20, 10); + cc.tiles["CIB_R70C49:CIB_DCU2"].add_unknown(22, 10); + cc.tiles["CIB_R70C49:CIB_DCU2"].add_unknown(29, 10); + cc.tiles["CIB_R70C49:CIB_DCU2"].add_unknown(31, 10); + cc.tiles["CIB_R70C49:CIB_DCU2"].add_unknown(74, 10); + cc.tiles["CIB_R70C49:CIB_DCU2"].add_unknown(76, 10); + cc.tiles["CIB_R70C49:CIB_DCU2"].add_unknown(83, 10); + cc.tiles["CIB_R70C49:CIB_DCU2"].add_unknown(85, 10); + cc.tiles["CIB_R70C50:CIB_DCUG"].add_unknown(20, 10); + cc.tiles["CIB_R70C50:CIB_DCUG"].add_unknown(22, 10); + cc.tiles["CIB_R70C50:CIB_DCUG"].add_unknown(29, 10); + cc.tiles["CIB_R70C50:CIB_DCUG"].add_unknown(31, 10); + cc.tiles["CIB_R70C50:CIB_DCUG"].add_unknown(74, 10); + cc.tiles["CIB_R70C50:CIB_DCUG"].add_unknown(76, 10); + cc.tiles["CIB_R70C50:CIB_DCUG"].add_unknown(83, 10); + cc.tiles["CIB_R70C50:CIB_DCUG"].add_unknown(85, 10); + cc.tiles["CIB_R70C51:CIB_DCUH"].add_unknown(20, 10); + cc.tiles["CIB_R70C51:CIB_DCUH"].add_unknown(22, 10); + cc.tiles["CIB_R70C51:CIB_DCUH"].add_unknown(29, 10); + cc.tiles["CIB_R70C51:CIB_DCUH"].add_unknown(31, 10); + cc.tiles["CIB_R70C51:CIB_DCUH"].add_unknown(74, 10); + cc.tiles["CIB_R70C51:CIB_DCUH"].add_unknown(76, 10); + cc.tiles["CIB_R70C51:CIB_DCUH"].add_unknown(83, 10); + cc.tiles["CIB_R70C51:CIB_DCUH"].add_unknown(85, 10); + cc.tiles["CIB_R70C52:CIB_DCUI"].add_unknown(20, 10); + cc.tiles["CIB_R70C52:CIB_DCUI"].add_unknown(22, 10); + cc.tiles["CIB_R70C52:CIB_DCUI"].add_unknown(29, 10); + cc.tiles["CIB_R70C52:CIB_DCUI"].add_unknown(31, 10); + cc.tiles["CIB_R70C52:CIB_DCUI"].add_unknown(74, 10); + cc.tiles["CIB_R70C52:CIB_DCUI"].add_unknown(76, 10); + cc.tiles["CIB_R70C52:CIB_DCUI"].add_unknown(83, 10); + cc.tiles["CIB_R70C52:CIB_DCUI"].add_unknown(85, 10); + cc.tiles["CIB_R70C53:CIB_DCU1"].add_unknown(20, 10); + cc.tiles["CIB_R70C53:CIB_DCU1"].add_unknown(22, 10); + cc.tiles["CIB_R70C53:CIB_DCU1"].add_unknown(29, 10); + cc.tiles["CIB_R70C53:CIB_DCU1"].add_unknown(31, 10); + cc.tiles["CIB_R70C53:CIB_DCU1"].add_unknown(74, 10); + cc.tiles["CIB_R70C69:CIB_DCU0"].add_unknown(20, 10); + cc.tiles["CIB_R70C69:CIB_DCU0"].add_unknown(21, 10); + cc.tiles["CIB_R70C69:CIB_DCU0"].add_unknown(22, 10); + cc.tiles["CIB_R70C69:CIB_DCU0"].add_unknown(23, 10); + cc.tiles["CIB_R70C69:CIB_DCU0"].add_unknown(28, 10); + cc.tiles["CIB_R70C69:CIB_DCU0"].add_unknown(29, 10); + cc.tiles["CIB_R70C69:CIB_DCU0"].add_unknown(30, 10); + cc.tiles["CIB_R70C69:CIB_DCU0"].add_unknown(31, 10); + cc.tiles["CIB_R70C69:CIB_DCU0"].add_unknown(74, 10); + cc.tiles["CIB_R70C69:CIB_DCU0"].add_unknown(75, 10); + cc.tiles["CIB_R70C69:CIB_DCU0"].add_unknown(76, 10); + cc.tiles["CIB_R70C69:CIB_DCU0"].add_unknown(77, 10); + cc.tiles["CIB_R70C69:CIB_DCU0"].add_unknown(82, 10); + cc.tiles["CIB_R70C69:CIB_DCU0"].add_unknown(83, 10); + cc.tiles["CIB_R70C69:CIB_DCU0"].add_unknown(84, 10); + cc.tiles["CIB_R70C69:CIB_DCU0"].add_unknown(85, 10); + cc.tiles["CIB_R70C6:CIB_EFB0"].add_enum("CIB.JB3MUX", "0"); + cc.tiles["CIB_R70C6:CIB_EFB0"].add_enum("CIB.JC6MUX", "0"); + cc.tiles["CIB_R70C6:CIB_EFB0"].add_enum("CIB.JD6MUX", "0"); + cc.tiles["CIB_R70C70:CIB_DCUA"].add_unknown(20, 10); + cc.tiles["CIB_R70C70:CIB_DCUA"].add_unknown(21, 10); + cc.tiles["CIB_R70C70:CIB_DCUA"].add_unknown(22, 10); + cc.tiles["CIB_R70C70:CIB_DCUA"].add_unknown(23, 10); + cc.tiles["CIB_R70C70:CIB_DCUA"].add_unknown(28, 10); + cc.tiles["CIB_R70C70:CIB_DCUA"].add_unknown(29, 10); + cc.tiles["CIB_R70C70:CIB_DCUA"].add_unknown(30, 10); + cc.tiles["CIB_R70C70:CIB_DCUA"].add_unknown(31, 10); + cc.tiles["CIB_R70C70:CIB_DCUA"].add_unknown(74, 10); + cc.tiles["CIB_R70C70:CIB_DCUA"].add_unknown(75, 10); + cc.tiles["CIB_R70C70:CIB_DCUA"].add_unknown(76, 10); + cc.tiles["CIB_R70C70:CIB_DCUA"].add_unknown(77, 10); + cc.tiles["CIB_R70C70:CIB_DCUA"].add_unknown(82, 10); + cc.tiles["CIB_R70C70:CIB_DCUA"].add_unknown(83, 10); + cc.tiles["CIB_R70C70:CIB_DCUA"].add_unknown(84, 10); + cc.tiles["CIB_R70C70:CIB_DCUA"].add_unknown(85, 10); + cc.tiles["CIB_R70C71:CIB_DCUB"].add_unknown(20, 10); + cc.tiles["CIB_R70C71:CIB_DCUB"].add_unknown(21, 10); + cc.tiles["CIB_R70C71:CIB_DCUB"].add_unknown(22, 10); + cc.tiles["CIB_R70C71:CIB_DCUB"].add_unknown(23, 10); + cc.tiles["CIB_R70C71:CIB_DCUB"].add_unknown(28, 10); + cc.tiles["CIB_R70C71:CIB_DCUB"].add_unknown(29, 10); + cc.tiles["CIB_R70C71:CIB_DCUB"].add_unknown(30, 10); + cc.tiles["CIB_R70C71:CIB_DCUB"].add_unknown(31, 10); + cc.tiles["CIB_R70C71:CIB_DCUB"].add_unknown(74, 10); + cc.tiles["CIB_R70C71:CIB_DCUB"].add_unknown(75, 10); + cc.tiles["CIB_R70C71:CIB_DCUB"].add_unknown(76, 10); + cc.tiles["CIB_R70C71:CIB_DCUB"].add_unknown(77, 10); + cc.tiles["CIB_R70C71:CIB_DCUB"].add_unknown(82, 10); + cc.tiles["CIB_R70C71:CIB_DCUB"].add_unknown(83, 10); + cc.tiles["CIB_R70C71:CIB_DCUB"].add_unknown(84, 10); + cc.tiles["CIB_R70C71:CIB_DCUB"].add_unknown(85, 10); + cc.tiles["CIB_R70C72:CIB_DCUC"].add_unknown(20, 10); + cc.tiles["CIB_R70C72:CIB_DCUC"].add_unknown(21, 10); + cc.tiles["CIB_R70C72:CIB_DCUC"].add_unknown(22, 10); + cc.tiles["CIB_R70C72:CIB_DCUC"].add_unknown(23, 10); + cc.tiles["CIB_R70C72:CIB_DCUC"].add_unknown(28, 10); + cc.tiles["CIB_R70C72:CIB_DCUC"].add_unknown(29, 10); + cc.tiles["CIB_R70C72:CIB_DCUC"].add_unknown(30, 10); + cc.tiles["CIB_R70C72:CIB_DCUC"].add_unknown(31, 10); + cc.tiles["CIB_R70C72:CIB_DCUC"].add_unknown(74, 10); + cc.tiles["CIB_R70C72:CIB_DCUC"].add_unknown(75, 10); + cc.tiles["CIB_R70C72:CIB_DCUC"].add_unknown(76, 10); + cc.tiles["CIB_R70C72:CIB_DCUC"].add_unknown(77, 10); + cc.tiles["CIB_R70C72:CIB_DCUC"].add_unknown(82, 10); + cc.tiles["CIB_R70C72:CIB_DCUC"].add_unknown(83, 10); + cc.tiles["CIB_R70C72:CIB_DCUC"].add_unknown(84, 10); + cc.tiles["CIB_R70C72:CIB_DCUC"].add_unknown(85, 10); + cc.tiles["CIB_R70C73:CIB_DCUD"].add_unknown(20, 10); + cc.tiles["CIB_R70C73:CIB_DCUD"].add_unknown(21, 10); + cc.tiles["CIB_R70C73:CIB_DCUD"].add_unknown(22, 10); + cc.tiles["CIB_R70C73:CIB_DCUD"].add_unknown(23, 10); + cc.tiles["CIB_R70C73:CIB_DCUD"].add_unknown(28, 10); + cc.tiles["CIB_R70C73:CIB_DCUD"].add_unknown(29, 10); + cc.tiles["CIB_R70C73:CIB_DCUD"].add_unknown(31, 10); + cc.tiles["CIB_R70C73:CIB_DCUD"].add_unknown(74, 10); + cc.tiles["CIB_R70C73:CIB_DCUD"].add_unknown(75, 10); + cc.tiles["CIB_R70C73:CIB_DCUD"].add_unknown(76, 10); + cc.tiles["CIB_R70C73:CIB_DCUD"].add_unknown(77, 10); + cc.tiles["CIB_R70C73:CIB_DCUD"].add_unknown(82, 10); + cc.tiles["CIB_R70C73:CIB_DCUD"].add_unknown(83, 10); + cc.tiles["CIB_R70C73:CIB_DCUD"].add_unknown(84, 10); + cc.tiles["CIB_R70C73:CIB_DCUD"].add_unknown(85, 10); + cc.tiles["CIB_R70C74:CIB_DCUF"].add_unknown(20, 10); + cc.tiles["CIB_R70C74:CIB_DCUF"].add_unknown(21, 10); + cc.tiles["CIB_R70C74:CIB_DCUF"].add_unknown(22, 10); + cc.tiles["CIB_R70C74:CIB_DCUF"].add_unknown(23, 10); + cc.tiles["CIB_R70C74:CIB_DCUF"].add_unknown(28, 10); + cc.tiles["CIB_R70C74:CIB_DCUF"].add_unknown(29, 10); + cc.tiles["CIB_R70C74:CIB_DCUF"].add_unknown(30, 10); + cc.tiles["CIB_R70C74:CIB_DCUF"].add_unknown(31, 10); + cc.tiles["CIB_R70C74:CIB_DCUF"].add_unknown(74, 10); + cc.tiles["CIB_R70C74:CIB_DCUF"].add_unknown(75, 10); + cc.tiles["CIB_R70C74:CIB_DCUF"].add_unknown(76, 10); + cc.tiles["CIB_R70C74:CIB_DCUF"].add_unknown(77, 10); + cc.tiles["CIB_R70C74:CIB_DCUF"].add_unknown(82, 10); + cc.tiles["CIB_R70C74:CIB_DCUF"].add_unknown(83, 10); + cc.tiles["CIB_R70C74:CIB_DCUF"].add_unknown(84, 10); + cc.tiles["CIB_R70C74:CIB_DCUF"].add_unknown(85, 10); + cc.tiles["CIB_R70C75:CIB_DCU3"].add_unknown(20, 10); + cc.tiles["CIB_R70C75:CIB_DCU3"].add_unknown(22, 10); + cc.tiles["CIB_R70C75:CIB_DCU3"].add_unknown(23, 10); + cc.tiles["CIB_R70C75:CIB_DCU3"].add_unknown(29, 10); + cc.tiles["CIB_R70C75:CIB_DCU3"].add_unknown(31, 10); + cc.tiles["CIB_R70C75:CIB_DCU3"].add_unknown(74, 10); + cc.tiles["CIB_R70C75:CIB_DCU3"].add_unknown(75, 10); + cc.tiles["CIB_R70C75:CIB_DCU3"].add_unknown(76, 10); + cc.tiles["CIB_R70C75:CIB_DCU3"].add_unknown(77, 10); + cc.tiles["CIB_R70C75:CIB_DCU3"].add_unknown(82, 10); + cc.tiles["CIB_R70C75:CIB_DCU3"].add_unknown(83, 10); + cc.tiles["CIB_R70C75:CIB_DCU3"].add_unknown(84, 10); + cc.tiles["CIB_R70C75:CIB_DCU3"].add_unknown(85, 10); + cc.tiles["CIB_R70C76:CIB_DCU2"].add_unknown(20, 10); + cc.tiles["CIB_R70C76:CIB_DCU2"].add_unknown(22, 10); + cc.tiles["CIB_R70C76:CIB_DCU2"].add_unknown(29, 10); + cc.tiles["CIB_R70C76:CIB_DCU2"].add_unknown(31, 10); + cc.tiles["CIB_R70C76:CIB_DCU2"].add_unknown(74, 10); + cc.tiles["CIB_R70C76:CIB_DCU2"].add_unknown(76, 10); + cc.tiles["CIB_R70C76:CIB_DCU2"].add_unknown(83, 10); + cc.tiles["CIB_R70C76:CIB_DCU2"].add_unknown(85, 10); + cc.tiles["CIB_R70C77:CIB_DCUG"].add_unknown(20, 10); + cc.tiles["CIB_R70C77:CIB_DCUG"].add_unknown(22, 10); + cc.tiles["CIB_R70C77:CIB_DCUG"].add_unknown(29, 10); + cc.tiles["CIB_R70C77:CIB_DCUG"].add_unknown(31, 10); + cc.tiles["CIB_R70C77:CIB_DCUG"].add_unknown(74, 10); + cc.tiles["CIB_R70C77:CIB_DCUG"].add_unknown(76, 10); + cc.tiles["CIB_R70C77:CIB_DCUG"].add_unknown(83, 10); + cc.tiles["CIB_R70C77:CIB_DCUG"].add_unknown(85, 10); + cc.tiles["CIB_R70C78:CIB_DCUH"].add_unknown(20, 10); + cc.tiles["CIB_R70C78:CIB_DCUH"].add_unknown(22, 10); + cc.tiles["CIB_R70C78:CIB_DCUH"].add_unknown(29, 10); + cc.tiles["CIB_R70C78:CIB_DCUH"].add_unknown(31, 10); + cc.tiles["CIB_R70C78:CIB_DCUH"].add_unknown(74, 10); + cc.tiles["CIB_R70C78:CIB_DCUH"].add_unknown(76, 10); + cc.tiles["CIB_R70C78:CIB_DCUH"].add_unknown(83, 10); + cc.tiles["CIB_R70C78:CIB_DCUH"].add_unknown(85, 10); + cc.tiles["CIB_R70C79:CIB_DCUI"].add_unknown(20, 10); + cc.tiles["CIB_R70C79:CIB_DCUI"].add_unknown(22, 10); + cc.tiles["CIB_R70C79:CIB_DCUI"].add_unknown(29, 10); + cc.tiles["CIB_R70C79:CIB_DCUI"].add_unknown(31, 10); + cc.tiles["CIB_R70C79:CIB_DCUI"].add_unknown(74, 10); + cc.tiles["CIB_R70C79:CIB_DCUI"].add_unknown(76, 10); + cc.tiles["CIB_R70C79:CIB_DCUI"].add_unknown(83, 10); + cc.tiles["CIB_R70C79:CIB_DCUI"].add_unknown(85, 10); + cc.tiles["CIB_R70C7:CIB_EFB1"].add_enum("CIB.JA3MUX", "0"); + cc.tiles["CIB_R70C7:CIB_EFB1"].add_enum("CIB.JA4MUX", "0"); + cc.tiles["CIB_R70C7:CIB_EFB1"].add_enum("CIB.JA5MUX", "0"); + cc.tiles["CIB_R70C7:CIB_EFB1"].add_enum("CIB.JA6MUX", "0"); + cc.tiles["CIB_R70C7:CIB_EFB1"].add_enum("CIB.JB3MUX", "0"); + cc.tiles["CIB_R70C7:CIB_EFB1"].add_enum("CIB.JB4MUX", "0"); + cc.tiles["CIB_R70C7:CIB_EFB1"].add_enum("CIB.JB5MUX", "0"); + cc.tiles["CIB_R70C7:CIB_EFB1"].add_enum("CIB.JB6MUX", "0"); + cc.tiles["CIB_R70C7:CIB_EFB1"].add_enum("CIB.JC3MUX", "0"); + cc.tiles["CIB_R70C7:CIB_EFB1"].add_enum("CIB.JC4MUX", "0"); + cc.tiles["CIB_R70C7:CIB_EFB1"].add_enum("CIB.JC5MUX", "0"); + cc.tiles["CIB_R70C7:CIB_EFB1"].add_enum("CIB.JD3MUX", "0"); + cc.tiles["CIB_R70C7:CIB_EFB1"].add_enum("CIB.JD4MUX", "0"); + cc.tiles["CIB_R70C7:CIB_EFB1"].add_enum("CIB.JD5MUX", "0"); + cc.tiles["CIB_R70C80:CIB_DCU1"].add_unknown(20, 10); + cc.tiles["CIB_R70C80:CIB_DCU1"].add_unknown(22, 10); + cc.tiles["CIB_R70C80:CIB_DCU1"].add_unknown(29, 10); + cc.tiles["CIB_R70C80:CIB_DCU1"].add_unknown(31, 10); + cc.tiles["CIB_R70C80:CIB_DCU1"].add_unknown(74, 10); + cc.tiles["CIB_R70C87:CIB_PLL3"].add_enum("CIB.JA3MUX", "0"); + cc.tiles["CIB_R70C87:CIB_PLL3"].add_enum("CIB.JB3MUX", "0"); + cc.tiles["MIB_R10C40:CMUX_UL_0"].add_arc("G_DCS0CLK0", "G_VPFN0000"); + cc.tiles["MIB_R10C41:CMUX_UR_0"].add_arc("G_DCS0CLK1", "G_VPFN0000"); + cc.tiles["MIB_R58C40:CMUX_LL_0"].add_arc("G_DCS1CLK0", "G_VPFN0000"); + cc.tiles["MIB_R58C41:CMUX_LR_0"].add_arc("G_DCS1CLK1", "G_VPFN0000"); + cc.tiles["MIB_R71C4:EFB0_PICB0"].add_unknown(54, 1); + cc.tiles["MIB_R71C4:EFB0_PICB0"].add_unknown(56, 1); + cc.tiles["MIB_R71C4:EFB0_PICB0"].add_unknown(82, 1); + cc.tiles["MIB_R71C4:EFB0_PICB0"].add_unknown(94, 1); +} + +void config_empty_lfe5um5g_25f(ChipConfig &cc) +{ + cc.chip_name = "LFE5UM5G-25F"; + cc.tiles["CIB_R49C3:CIB_PLL3"].add_enum("CIB.JA3MUX", "0"); + cc.tiles["CIB_R49C3:CIB_PLL3"].add_enum("CIB.JB3MUX", "0"); + cc.tiles["CIB_R49C42:CIB_DCU0"].add_unknown(20, 10); + cc.tiles["CIB_R49C42:CIB_DCU0"].add_unknown(21, 10); + cc.tiles["CIB_R49C42:CIB_DCU0"].add_unknown(22, 10); + cc.tiles["CIB_R49C42:CIB_DCU0"].add_unknown(23, 10); + cc.tiles["CIB_R49C42:CIB_DCU0"].add_unknown(28, 10); + cc.tiles["CIB_R49C42:CIB_DCU0"].add_unknown(29, 10); + cc.tiles["CIB_R49C42:CIB_DCU0"].add_unknown(30, 10); + cc.tiles["CIB_R49C42:CIB_DCU0"].add_unknown(31, 10); + cc.tiles["CIB_R49C42:CIB_DCU0"].add_unknown(74, 10); + cc.tiles["CIB_R49C42:CIB_DCU0"].add_unknown(75, 10); + cc.tiles["CIB_R49C42:CIB_DCU0"].add_unknown(76, 10); + cc.tiles["CIB_R49C42:CIB_DCU0"].add_unknown(77, 10); + cc.tiles["CIB_R49C42:CIB_DCU0"].add_unknown(82, 10); + cc.tiles["CIB_R49C42:CIB_DCU0"].add_unknown(83, 10); + cc.tiles["CIB_R49C42:CIB_DCU0"].add_unknown(84, 10); + cc.tiles["CIB_R49C42:CIB_DCU0"].add_unknown(85, 10); + cc.tiles["CIB_R49C43:CIB_DCUA"].add_unknown(20, 10); + cc.tiles["CIB_R49C43:CIB_DCUA"].add_unknown(21, 10); + cc.tiles["CIB_R49C43:CIB_DCUA"].add_unknown(22, 10); + cc.tiles["CIB_R49C43:CIB_DCUA"].add_unknown(23, 10); + cc.tiles["CIB_R49C43:CIB_DCUA"].add_unknown(28, 10); + cc.tiles["CIB_R49C43:CIB_DCUA"].add_unknown(29, 10); + cc.tiles["CIB_R49C43:CIB_DCUA"].add_unknown(30, 10); + cc.tiles["CIB_R49C43:CIB_DCUA"].add_unknown(31, 10); + cc.tiles["CIB_R49C43:CIB_DCUA"].add_unknown(74, 10); + cc.tiles["CIB_R49C43:CIB_DCUA"].add_unknown(75, 10); + cc.tiles["CIB_R49C43:CIB_DCUA"].add_unknown(76, 10); + cc.tiles["CIB_R49C43:CIB_DCUA"].add_unknown(77, 10); + cc.tiles["CIB_R49C43:CIB_DCUA"].add_unknown(82, 10); + cc.tiles["CIB_R49C43:CIB_DCUA"].add_unknown(83, 10); + cc.tiles["CIB_R49C43:CIB_DCUA"].add_unknown(84, 10); + cc.tiles["CIB_R49C43:CIB_DCUA"].add_unknown(85, 10); + cc.tiles["CIB_R49C44:CIB_DCUB"].add_unknown(20, 10); + cc.tiles["CIB_R49C44:CIB_DCUB"].add_unknown(21, 10); + cc.tiles["CIB_R49C44:CIB_DCUB"].add_unknown(22, 10); + cc.tiles["CIB_R49C44:CIB_DCUB"].add_unknown(23, 10); + cc.tiles["CIB_R49C44:CIB_DCUB"].add_unknown(28, 10); + cc.tiles["CIB_R49C44:CIB_DCUB"].add_unknown(29, 10); + cc.tiles["CIB_R49C44:CIB_DCUB"].add_unknown(30, 10); + cc.tiles["CIB_R49C44:CIB_DCUB"].add_unknown(31, 10); + cc.tiles["CIB_R49C44:CIB_DCUB"].add_unknown(74, 10); + cc.tiles["CIB_R49C44:CIB_DCUB"].add_unknown(75, 10); + cc.tiles["CIB_R49C44:CIB_DCUB"].add_unknown(76, 10); + cc.tiles["CIB_R49C44:CIB_DCUB"].add_unknown(77, 10); + cc.tiles["CIB_R49C44:CIB_DCUB"].add_unknown(82, 10); + cc.tiles["CIB_R49C44:CIB_DCUB"].add_unknown(83, 10); + cc.tiles["CIB_R49C44:CIB_DCUB"].add_unknown(84, 10); + cc.tiles["CIB_R49C44:CIB_DCUB"].add_unknown(85, 10); + cc.tiles["CIB_R49C45:CIB_DCUC"].add_unknown(20, 10); + cc.tiles["CIB_R49C45:CIB_DCUC"].add_unknown(21, 10); + cc.tiles["CIB_R49C45:CIB_DCUC"].add_unknown(22, 10); + cc.tiles["CIB_R49C45:CIB_DCUC"].add_unknown(23, 10); + cc.tiles["CIB_R49C45:CIB_DCUC"].add_unknown(28, 10); + cc.tiles["CIB_R49C45:CIB_DCUC"].add_unknown(29, 10); + cc.tiles["CIB_R49C45:CIB_DCUC"].add_unknown(30, 10); + cc.tiles["CIB_R49C45:CIB_DCUC"].add_unknown(31, 10); + cc.tiles["CIB_R49C45:CIB_DCUC"].add_unknown(74, 10); + cc.tiles["CIB_R49C45:CIB_DCUC"].add_unknown(75, 10); + cc.tiles["CIB_R49C45:CIB_DCUC"].add_unknown(76, 10); + cc.tiles["CIB_R49C45:CIB_DCUC"].add_unknown(77, 10); + cc.tiles["CIB_R49C45:CIB_DCUC"].add_unknown(82, 10); + cc.tiles["CIB_R49C45:CIB_DCUC"].add_unknown(83, 10); + cc.tiles["CIB_R49C45:CIB_DCUC"].add_unknown(84, 10); + cc.tiles["CIB_R49C45:CIB_DCUC"].add_unknown(85, 10); + cc.tiles["CIB_R49C46:CIB_DCUD"].add_unknown(20, 10); + cc.tiles["CIB_R49C46:CIB_DCUD"].add_unknown(21, 10); + cc.tiles["CIB_R49C46:CIB_DCUD"].add_unknown(22, 10); + cc.tiles["CIB_R49C46:CIB_DCUD"].add_unknown(23, 10); + cc.tiles["CIB_R49C46:CIB_DCUD"].add_unknown(28, 10); + cc.tiles["CIB_R49C46:CIB_DCUD"].add_unknown(29, 10); + cc.tiles["CIB_R49C46:CIB_DCUD"].add_unknown(31, 10); + cc.tiles["CIB_R49C46:CIB_DCUD"].add_unknown(74, 10); + cc.tiles["CIB_R49C46:CIB_DCUD"].add_unknown(75, 10); + cc.tiles["CIB_R49C46:CIB_DCUD"].add_unknown(76, 10); + cc.tiles["CIB_R49C46:CIB_DCUD"].add_unknown(77, 10); + cc.tiles["CIB_R49C46:CIB_DCUD"].add_unknown(82, 10); + cc.tiles["CIB_R49C46:CIB_DCUD"].add_unknown(83, 10); + cc.tiles["CIB_R49C46:CIB_DCUD"].add_unknown(84, 10); + cc.tiles["CIB_R49C46:CIB_DCUD"].add_unknown(85, 10); + cc.tiles["CIB_R49C47:CIB_DCUF"].add_unknown(20, 10); + cc.tiles["CIB_R49C47:CIB_DCUF"].add_unknown(21, 10); + cc.tiles["CIB_R49C47:CIB_DCUF"].add_unknown(22, 10); + cc.tiles["CIB_R49C47:CIB_DCUF"].add_unknown(23, 10); + cc.tiles["CIB_R49C47:CIB_DCUF"].add_unknown(28, 10); + cc.tiles["CIB_R49C47:CIB_DCUF"].add_unknown(29, 10); + cc.tiles["CIB_R49C47:CIB_DCUF"].add_unknown(30, 10); + cc.tiles["CIB_R49C47:CIB_DCUF"].add_unknown(31, 10); + cc.tiles["CIB_R49C47:CIB_DCUF"].add_unknown(74, 10); + cc.tiles["CIB_R49C47:CIB_DCUF"].add_unknown(75, 10); + cc.tiles["CIB_R49C47:CIB_DCUF"].add_unknown(76, 10); + cc.tiles["CIB_R49C47:CIB_DCUF"].add_unknown(77, 10); + cc.tiles["CIB_R49C47:CIB_DCUF"].add_unknown(82, 10); + cc.tiles["CIB_R49C47:CIB_DCUF"].add_unknown(83, 10); + cc.tiles["CIB_R49C47:CIB_DCUF"].add_unknown(84, 10); + cc.tiles["CIB_R49C47:CIB_DCUF"].add_unknown(85, 10); + cc.tiles["CIB_R49C48:CIB_DCU3"].add_unknown(20, 10); + cc.tiles["CIB_R49C48:CIB_DCU3"].add_unknown(22, 10); + cc.tiles["CIB_R49C48:CIB_DCU3"].add_unknown(23, 10); + cc.tiles["CIB_R49C48:CIB_DCU3"].add_unknown(29, 10); + cc.tiles["CIB_R49C48:CIB_DCU3"].add_unknown(31, 10); + cc.tiles["CIB_R49C48:CIB_DCU3"].add_unknown(74, 10); + cc.tiles["CIB_R49C48:CIB_DCU3"].add_unknown(75, 10); + cc.tiles["CIB_R49C48:CIB_DCU3"].add_unknown(76, 10); + cc.tiles["CIB_R49C48:CIB_DCU3"].add_unknown(77, 10); + cc.tiles["CIB_R49C48:CIB_DCU3"].add_unknown(82, 10); + cc.tiles["CIB_R49C48:CIB_DCU3"].add_unknown(83, 10); + cc.tiles["CIB_R49C48:CIB_DCU3"].add_unknown(84, 10); + cc.tiles["CIB_R49C48:CIB_DCU3"].add_unknown(85, 10); + cc.tiles["CIB_R49C49:CIB_DCU2"].add_unknown(20, 10); + cc.tiles["CIB_R49C49:CIB_DCU2"].add_unknown(22, 10); + cc.tiles["CIB_R49C49:CIB_DCU2"].add_unknown(29, 10); + cc.tiles["CIB_R49C49:CIB_DCU2"].add_unknown(31, 10); + cc.tiles["CIB_R49C49:CIB_DCU2"].add_unknown(74, 10); + cc.tiles["CIB_R49C49:CIB_DCU2"].add_unknown(76, 10); + cc.tiles["CIB_R49C49:CIB_DCU2"].add_unknown(83, 10); + cc.tiles["CIB_R49C49:CIB_DCU2"].add_unknown(85, 10); + cc.tiles["CIB_R49C50:CIB_DCUG"].add_unknown(20, 10); + cc.tiles["CIB_R49C50:CIB_DCUG"].add_unknown(22, 10); + cc.tiles["CIB_R49C50:CIB_DCUG"].add_unknown(29, 10); + cc.tiles["CIB_R49C50:CIB_DCUG"].add_unknown(31, 10); + cc.tiles["CIB_R49C50:CIB_DCUG"].add_unknown(74, 10); + cc.tiles["CIB_R49C50:CIB_DCUG"].add_unknown(76, 10); + cc.tiles["CIB_R49C50:CIB_DCUG"].add_unknown(83, 10); + cc.tiles["CIB_R49C50:CIB_DCUG"].add_unknown(85, 10); + cc.tiles["CIB_R49C51:CIB_DCUH"].add_unknown(20, 10); + cc.tiles["CIB_R49C51:CIB_DCUH"].add_unknown(22, 10); + cc.tiles["CIB_R49C51:CIB_DCUH"].add_unknown(29, 10); + cc.tiles["CIB_R49C51:CIB_DCUH"].add_unknown(31, 10); + cc.tiles["CIB_R49C51:CIB_DCUH"].add_unknown(74, 10); + cc.tiles["CIB_R49C51:CIB_DCUH"].add_unknown(76, 10); + cc.tiles["CIB_R49C51:CIB_DCUH"].add_unknown(83, 10); + cc.tiles["CIB_R49C51:CIB_DCUH"].add_unknown(85, 10); + cc.tiles["CIB_R49C52:CIB_DCUI"].add_unknown(20, 10); + cc.tiles["CIB_R49C52:CIB_DCUI"].add_unknown(22, 10); + cc.tiles["CIB_R49C52:CIB_DCUI"].add_unknown(29, 10); + cc.tiles["CIB_R49C52:CIB_DCUI"].add_unknown(31, 10); + cc.tiles["CIB_R49C52:CIB_DCUI"].add_unknown(74, 10); + cc.tiles["CIB_R49C52:CIB_DCUI"].add_unknown(76, 10); + cc.tiles["CIB_R49C52:CIB_DCUI"].add_unknown(83, 10); + cc.tiles["CIB_R49C52:CIB_DCUI"].add_unknown(85, 10); + cc.tiles["CIB_R49C53:CIB_DCU1"].add_unknown(20, 10); + cc.tiles["CIB_R49C53:CIB_DCU1"].add_unknown(22, 10); + cc.tiles["CIB_R49C53:CIB_DCU1"].add_unknown(29, 10); + cc.tiles["CIB_R49C53:CIB_DCU1"].add_unknown(31, 10); + cc.tiles["CIB_R49C53:CIB_DCU1"].add_unknown(74, 10); + cc.tiles["CIB_R49C69:CIB_PLL3"].add_enum("CIB.JA3MUX", "0"); + cc.tiles["CIB_R49C69:CIB_PLL3"].add_enum("CIB.JB3MUX", "0"); + cc.tiles["CIB_R49C6:CIB_EFB0"].add_enum("CIB.JB3MUX", "0"); + cc.tiles["CIB_R49C6:CIB_EFB0"].add_enum("CIB.JC6MUX", "0"); + cc.tiles["CIB_R49C6:CIB_EFB0"].add_enum("CIB.JD6MUX", "0"); + cc.tiles["CIB_R49C7:CIB_EFB1"].add_enum("CIB.JA3MUX", "0"); + cc.tiles["CIB_R49C7:CIB_EFB1"].add_enum("CIB.JA4MUX", "0"); + cc.tiles["CIB_R49C7:CIB_EFB1"].add_enum("CIB.JA5MUX", "0"); + cc.tiles["CIB_R49C7:CIB_EFB1"].add_enum("CIB.JA6MUX", "0"); + cc.tiles["CIB_R49C7:CIB_EFB1"].add_enum("CIB.JB3MUX", "0"); + cc.tiles["CIB_R49C7:CIB_EFB1"].add_enum("CIB.JB4MUX", "0"); + cc.tiles["CIB_R49C7:CIB_EFB1"].add_enum("CIB.JB5MUX", "0"); + cc.tiles["CIB_R49C7:CIB_EFB1"].add_enum("CIB.JB6MUX", "0"); + cc.tiles["CIB_R49C7:CIB_EFB1"].add_enum("CIB.JC3MUX", "0"); + cc.tiles["CIB_R49C7:CIB_EFB1"].add_enum("CIB.JC4MUX", "0"); + cc.tiles["CIB_R49C7:CIB_EFB1"].add_enum("CIB.JC5MUX", "0"); + cc.tiles["CIB_R49C7:CIB_EFB1"].add_enum("CIB.JD3MUX", "0"); + cc.tiles["CIB_R49C7:CIB_EFB1"].add_enum("CIB.JD4MUX", "0"); + cc.tiles["CIB_R49C7:CIB_EFB1"].add_enum("CIB.JD5MUX", "0"); + cc.tiles["MIB_R13C31:CMUX_UL_0"].add_arc("G_DCS0CLK0", "G_VPFN0000"); + cc.tiles["MIB_R13C32:CMUX_UR_0"].add_arc("G_DCS0CLK1", "G_VPFN0000"); + cc.tiles["MIB_R13C3:DSP_SPINE_UL1"].add_unknown(2, 0); + cc.tiles["MIB_R13C3:DSP_SPINE_UL1"].add_unknown(3, 0); + cc.tiles["MIB_R13C3:DSP_SPINE_UL1"].add_unknown(5, 0); + cc.tiles["MIB_R13C3:DSP_SPINE_UL1"].add_unknown(11, 0); + cc.tiles["MIB_R13C3:DSP_SPINE_UL1"].add_unknown(13, 0); + cc.tiles["MIB_R37C31:CMUX_LL_0"].add_arc("G_DCS1CLK0", "G_VPFN0000"); + cc.tiles["MIB_R37C32:CMUX_LR_0"].add_arc("G_DCS1CLK1", "G_VPFN0000"); + cc.tiles["MIB_R50C4:EFB0_PICB0"].add_unknown(54, 1); + cc.tiles["MIB_R50C4:EFB0_PICB0"].add_unknown(56, 1); + cc.tiles["MIB_R50C4:EFB0_PICB0"].add_unknown(82, 1); + cc.tiles["MIB_R50C4:EFB0_PICB0"].add_unknown(94, 1); +} + +void config_empty_lfe5um5g_45f(ChipConfig &cc) +{ + cc.chip_name = "LFE5UM5G-45F"; + cc.tiles["CIB_R10C3:PVT_COUNT2"].add_unknown(2, 0); + cc.tiles["CIB_R10C3:PVT_COUNT2"].add_unknown(3, 0); + cc.tiles["CIB_R10C3:PVT_COUNT2"].add_unknown(5, 0); + cc.tiles["CIB_R10C3:PVT_COUNT2"].add_unknown(11, 0); + cc.tiles["CIB_R10C3:PVT_COUNT2"].add_unknown(13, 0); + cc.tiles["CIB_R5C1:CIB_PLL1"].add_enum("CIB.JA3MUX", "0"); + cc.tiles["CIB_R5C1:CIB_PLL1"].add_enum("CIB.JB3MUX", "0"); + cc.tiles["CIB_R5C89:CIB_PLL1"].add_enum("CIB.JA3MUX", "0"); + cc.tiles["CIB_R5C89:CIB_PLL1"].add_enum("CIB.JB3MUX", "0"); + cc.tiles["CIB_R70C3:CIB_PLL3"].add_enum("CIB.JA3MUX", "0"); + cc.tiles["CIB_R70C3:CIB_PLL3"].add_enum("CIB.JB3MUX", "0"); + cc.tiles["CIB_R70C42:CIB_DCU0"].add_unknown(20, 10); + cc.tiles["CIB_R70C42:CIB_DCU0"].add_unknown(21, 10); + cc.tiles["CIB_R70C42:CIB_DCU0"].add_unknown(22, 10); + cc.tiles["CIB_R70C42:CIB_DCU0"].add_unknown(23, 10); + cc.tiles["CIB_R70C42:CIB_DCU0"].add_unknown(28, 10); + cc.tiles["CIB_R70C42:CIB_DCU0"].add_unknown(29, 10); + cc.tiles["CIB_R70C42:CIB_DCU0"].add_unknown(30, 10); + cc.tiles["CIB_R70C42:CIB_DCU0"].add_unknown(31, 10); + cc.tiles["CIB_R70C42:CIB_DCU0"].add_unknown(74, 10); + cc.tiles["CIB_R70C42:CIB_DCU0"].add_unknown(75, 10); + cc.tiles["CIB_R70C42:CIB_DCU0"].add_unknown(76, 10); + cc.tiles["CIB_R70C42:CIB_DCU0"].add_unknown(77, 10); + cc.tiles["CIB_R70C42:CIB_DCU0"].add_unknown(82, 10); + cc.tiles["CIB_R70C42:CIB_DCU0"].add_unknown(83, 10); + cc.tiles["CIB_R70C42:CIB_DCU0"].add_unknown(84, 10); + cc.tiles["CIB_R70C42:CIB_DCU0"].add_unknown(85, 10); + cc.tiles["CIB_R70C43:CIB_DCUA"].add_unknown(20, 10); + cc.tiles["CIB_R70C43:CIB_DCUA"].add_unknown(21, 10); + cc.tiles["CIB_R70C43:CIB_DCUA"].add_unknown(22, 10); + cc.tiles["CIB_R70C43:CIB_DCUA"].add_unknown(23, 10); + cc.tiles["CIB_R70C43:CIB_DCUA"].add_unknown(28, 10); + cc.tiles["CIB_R70C43:CIB_DCUA"].add_unknown(29, 10); + cc.tiles["CIB_R70C43:CIB_DCUA"].add_unknown(30, 10); + cc.tiles["CIB_R70C43:CIB_DCUA"].add_unknown(31, 10); + cc.tiles["CIB_R70C43:CIB_DCUA"].add_unknown(74, 10); + cc.tiles["CIB_R70C43:CIB_DCUA"].add_unknown(75, 10); + cc.tiles["CIB_R70C43:CIB_DCUA"].add_unknown(76, 10); + cc.tiles["CIB_R70C43:CIB_DCUA"].add_unknown(77, 10); + cc.tiles["CIB_R70C43:CIB_DCUA"].add_unknown(82, 10); + cc.tiles["CIB_R70C43:CIB_DCUA"].add_unknown(83, 10); + cc.tiles["CIB_R70C43:CIB_DCUA"].add_unknown(84, 10); + cc.tiles["CIB_R70C43:CIB_DCUA"].add_unknown(85, 10); + cc.tiles["CIB_R70C44:CIB_DCUB"].add_unknown(20, 10); + cc.tiles["CIB_R70C44:CIB_DCUB"].add_unknown(21, 10); + cc.tiles["CIB_R70C44:CIB_DCUB"].add_unknown(22, 10); + cc.tiles["CIB_R70C44:CIB_DCUB"].add_unknown(23, 10); + cc.tiles["CIB_R70C44:CIB_DCUB"].add_unknown(28, 10); + cc.tiles["CIB_R70C44:CIB_DCUB"].add_unknown(29, 10); + cc.tiles["CIB_R70C44:CIB_DCUB"].add_unknown(30, 10); + cc.tiles["CIB_R70C44:CIB_DCUB"].add_unknown(31, 10); + cc.tiles["CIB_R70C44:CIB_DCUB"].add_unknown(74, 10); + cc.tiles["CIB_R70C44:CIB_DCUB"].add_unknown(75, 10); + cc.tiles["CIB_R70C44:CIB_DCUB"].add_unknown(76, 10); + cc.tiles["CIB_R70C44:CIB_DCUB"].add_unknown(77, 10); + cc.tiles["CIB_R70C44:CIB_DCUB"].add_unknown(82, 10); + cc.tiles["CIB_R70C44:CIB_DCUB"].add_unknown(83, 10); + cc.tiles["CIB_R70C44:CIB_DCUB"].add_unknown(84, 10); + cc.tiles["CIB_R70C44:CIB_DCUB"].add_unknown(85, 10); + cc.tiles["CIB_R70C45:CIB_DCUC"].add_unknown(20, 10); + cc.tiles["CIB_R70C45:CIB_DCUC"].add_unknown(21, 10); + cc.tiles["CIB_R70C45:CIB_DCUC"].add_unknown(22, 10); + cc.tiles["CIB_R70C45:CIB_DCUC"].add_unknown(23, 10); + cc.tiles["CIB_R70C45:CIB_DCUC"].add_unknown(28, 10); + cc.tiles["CIB_R70C45:CIB_DCUC"].add_unknown(29, 10); + cc.tiles["CIB_R70C45:CIB_DCUC"].add_unknown(30, 10); + cc.tiles["CIB_R70C45:CIB_DCUC"].add_unknown(31, 10); + cc.tiles["CIB_R70C45:CIB_DCUC"].add_unknown(74, 10); + cc.tiles["CIB_R70C45:CIB_DCUC"].add_unknown(75, 10); + cc.tiles["CIB_R70C45:CIB_DCUC"].add_unknown(76, 10); + cc.tiles["CIB_R70C45:CIB_DCUC"].add_unknown(77, 10); + cc.tiles["CIB_R70C45:CIB_DCUC"].add_unknown(82, 10); + cc.tiles["CIB_R70C45:CIB_DCUC"].add_unknown(83, 10); + cc.tiles["CIB_R70C45:CIB_DCUC"].add_unknown(84, 10); + cc.tiles["CIB_R70C45:CIB_DCUC"].add_unknown(85, 10); + cc.tiles["CIB_R70C46:CIB_DCUD"].add_unknown(20, 10); + cc.tiles["CIB_R70C46:CIB_DCUD"].add_unknown(21, 10); + cc.tiles["CIB_R70C46:CIB_DCUD"].add_unknown(22, 10); + cc.tiles["CIB_R70C46:CIB_DCUD"].add_unknown(23, 10); + cc.tiles["CIB_R70C46:CIB_DCUD"].add_unknown(28, 10); + cc.tiles["CIB_R70C46:CIB_DCUD"].add_unknown(29, 10); + cc.tiles["CIB_R70C46:CIB_DCUD"].add_unknown(31, 10); + cc.tiles["CIB_R70C46:CIB_DCUD"].add_unknown(74, 10); + cc.tiles["CIB_R70C46:CIB_DCUD"].add_unknown(75, 10); + cc.tiles["CIB_R70C46:CIB_DCUD"].add_unknown(76, 10); + cc.tiles["CIB_R70C46:CIB_DCUD"].add_unknown(77, 10); + cc.tiles["CIB_R70C46:CIB_DCUD"].add_unknown(82, 10); + cc.tiles["CIB_R70C46:CIB_DCUD"].add_unknown(83, 10); + cc.tiles["CIB_R70C46:CIB_DCUD"].add_unknown(84, 10); + cc.tiles["CIB_R70C46:CIB_DCUD"].add_unknown(85, 10); + cc.tiles["CIB_R70C47:CIB_DCUF"].add_unknown(20, 10); + cc.tiles["CIB_R70C47:CIB_DCUF"].add_unknown(21, 10); + cc.tiles["CIB_R70C47:CIB_DCUF"].add_unknown(22, 10); + cc.tiles["CIB_R70C47:CIB_DCUF"].add_unknown(23, 10); + cc.tiles["CIB_R70C47:CIB_DCUF"].add_unknown(28, 10); + cc.tiles["CIB_R70C47:CIB_DCUF"].add_unknown(29, 10); + cc.tiles["CIB_R70C47:CIB_DCUF"].add_unknown(30, 10); + cc.tiles["CIB_R70C47:CIB_DCUF"].add_unknown(31, 10); + cc.tiles["CIB_R70C47:CIB_DCUF"].add_unknown(74, 10); + cc.tiles["CIB_R70C47:CIB_DCUF"].add_unknown(75, 10); + cc.tiles["CIB_R70C47:CIB_DCUF"].add_unknown(76, 10); + cc.tiles["CIB_R70C47:CIB_DCUF"].add_unknown(77, 10); + cc.tiles["CIB_R70C47:CIB_DCUF"].add_unknown(82, 10); + cc.tiles["CIB_R70C47:CIB_DCUF"].add_unknown(83, 10); + cc.tiles["CIB_R70C47:CIB_DCUF"].add_unknown(84, 10); + cc.tiles["CIB_R70C47:CIB_DCUF"].add_unknown(85, 10); + cc.tiles["CIB_R70C48:CIB_DCU3"].add_unknown(20, 10); + cc.tiles["CIB_R70C48:CIB_DCU3"].add_unknown(22, 10); + cc.tiles["CIB_R70C48:CIB_DCU3"].add_unknown(23, 10); + cc.tiles["CIB_R70C48:CIB_DCU3"].add_unknown(29, 10); + cc.tiles["CIB_R70C48:CIB_DCU3"].add_unknown(31, 10); + cc.tiles["CIB_R70C48:CIB_DCU3"].add_unknown(74, 10); + cc.tiles["CIB_R70C48:CIB_DCU3"].add_unknown(75, 10); + cc.tiles["CIB_R70C48:CIB_DCU3"].add_unknown(76, 10); + cc.tiles["CIB_R70C48:CIB_DCU3"].add_unknown(77, 10); + cc.tiles["CIB_R70C48:CIB_DCU3"].add_unknown(82, 10); + cc.tiles["CIB_R70C48:CIB_DCU3"].add_unknown(83, 10); + cc.tiles["CIB_R70C48:CIB_DCU3"].add_unknown(84, 10); + cc.tiles["CIB_R70C48:CIB_DCU3"].add_unknown(85, 10); + cc.tiles["CIB_R70C49:CIB_DCU2"].add_unknown(20, 10); + cc.tiles["CIB_R70C49:CIB_DCU2"].add_unknown(22, 10); + cc.tiles["CIB_R70C49:CIB_DCU2"].add_unknown(29, 10); + cc.tiles["CIB_R70C49:CIB_DCU2"].add_unknown(31, 10); + cc.tiles["CIB_R70C49:CIB_DCU2"].add_unknown(74, 10); + cc.tiles["CIB_R70C49:CIB_DCU2"].add_unknown(76, 10); + cc.tiles["CIB_R70C49:CIB_DCU2"].add_unknown(83, 10); + cc.tiles["CIB_R70C49:CIB_DCU2"].add_unknown(85, 10); + cc.tiles["CIB_R70C50:CIB_DCUG"].add_unknown(20, 10); + cc.tiles["CIB_R70C50:CIB_DCUG"].add_unknown(22, 10); + cc.tiles["CIB_R70C50:CIB_DCUG"].add_unknown(29, 10); + cc.tiles["CIB_R70C50:CIB_DCUG"].add_unknown(31, 10); + cc.tiles["CIB_R70C50:CIB_DCUG"].add_unknown(74, 10); + cc.tiles["CIB_R70C50:CIB_DCUG"].add_unknown(76, 10); + cc.tiles["CIB_R70C50:CIB_DCUG"].add_unknown(83, 10); + cc.tiles["CIB_R70C50:CIB_DCUG"].add_unknown(85, 10); + cc.tiles["CIB_R70C51:CIB_DCUH"].add_unknown(20, 10); + cc.tiles["CIB_R70C51:CIB_DCUH"].add_unknown(22, 10); + cc.tiles["CIB_R70C51:CIB_DCUH"].add_unknown(29, 10); + cc.tiles["CIB_R70C51:CIB_DCUH"].add_unknown(31, 10); + cc.tiles["CIB_R70C51:CIB_DCUH"].add_unknown(74, 10); + cc.tiles["CIB_R70C51:CIB_DCUH"].add_unknown(76, 10); + cc.tiles["CIB_R70C51:CIB_DCUH"].add_unknown(83, 10); + cc.tiles["CIB_R70C51:CIB_DCUH"].add_unknown(85, 10); + cc.tiles["CIB_R70C52:CIB_DCUI"].add_unknown(20, 10); + cc.tiles["CIB_R70C52:CIB_DCUI"].add_unknown(22, 10); + cc.tiles["CIB_R70C52:CIB_DCUI"].add_unknown(29, 10); + cc.tiles["CIB_R70C52:CIB_DCUI"].add_unknown(31, 10); + cc.tiles["CIB_R70C52:CIB_DCUI"].add_unknown(74, 10); + cc.tiles["CIB_R70C52:CIB_DCUI"].add_unknown(76, 10); + cc.tiles["CIB_R70C52:CIB_DCUI"].add_unknown(83, 10); + cc.tiles["CIB_R70C52:CIB_DCUI"].add_unknown(85, 10); + cc.tiles["CIB_R70C53:CIB_DCU1"].add_unknown(20, 10); + cc.tiles["CIB_R70C53:CIB_DCU1"].add_unknown(22, 10); + cc.tiles["CIB_R70C53:CIB_DCU1"].add_unknown(29, 10); + cc.tiles["CIB_R70C53:CIB_DCU1"].add_unknown(31, 10); + cc.tiles["CIB_R70C53:CIB_DCU1"].add_unknown(74, 10); + cc.tiles["CIB_R70C69:CIB_DCU0"].add_unknown(20, 10); + cc.tiles["CIB_R70C69:CIB_DCU0"].add_unknown(21, 10); + cc.tiles["CIB_R70C69:CIB_DCU0"].add_unknown(22, 10); + cc.tiles["CIB_R70C69:CIB_DCU0"].add_unknown(23, 10); + cc.tiles["CIB_R70C69:CIB_DCU0"].add_unknown(28, 10); + cc.tiles["CIB_R70C69:CIB_DCU0"].add_unknown(29, 10); + cc.tiles["CIB_R70C69:CIB_DCU0"].add_unknown(30, 10); + cc.tiles["CIB_R70C69:CIB_DCU0"].add_unknown(31, 10); + cc.tiles["CIB_R70C69:CIB_DCU0"].add_unknown(74, 10); + cc.tiles["CIB_R70C69:CIB_DCU0"].add_unknown(75, 10); + cc.tiles["CIB_R70C69:CIB_DCU0"].add_unknown(76, 10); + cc.tiles["CIB_R70C69:CIB_DCU0"].add_unknown(77, 10); + cc.tiles["CIB_R70C69:CIB_DCU0"].add_unknown(82, 10); + cc.tiles["CIB_R70C69:CIB_DCU0"].add_unknown(83, 10); + cc.tiles["CIB_R70C69:CIB_DCU0"].add_unknown(84, 10); + cc.tiles["CIB_R70C69:CIB_DCU0"].add_unknown(85, 10); + cc.tiles["CIB_R70C6:CIB_EFB0"].add_enum("CIB.JB3MUX", "0"); + cc.tiles["CIB_R70C6:CIB_EFB0"].add_enum("CIB.JC6MUX", "0"); + cc.tiles["CIB_R70C6:CIB_EFB0"].add_enum("CIB.JD6MUX", "0"); + cc.tiles["CIB_R70C70:CIB_DCUA"].add_unknown(20, 10); + cc.tiles["CIB_R70C70:CIB_DCUA"].add_unknown(21, 10); + cc.tiles["CIB_R70C70:CIB_DCUA"].add_unknown(22, 10); + cc.tiles["CIB_R70C70:CIB_DCUA"].add_unknown(23, 10); + cc.tiles["CIB_R70C70:CIB_DCUA"].add_unknown(28, 10); + cc.tiles["CIB_R70C70:CIB_DCUA"].add_unknown(29, 10); + cc.tiles["CIB_R70C70:CIB_DCUA"].add_unknown(30, 10); + cc.tiles["CIB_R70C70:CIB_DCUA"].add_unknown(31, 10); + cc.tiles["CIB_R70C70:CIB_DCUA"].add_unknown(74, 10); + cc.tiles["CIB_R70C70:CIB_DCUA"].add_unknown(75, 10); + cc.tiles["CIB_R70C70:CIB_DCUA"].add_unknown(76, 10); + cc.tiles["CIB_R70C70:CIB_DCUA"].add_unknown(77, 10); + cc.tiles["CIB_R70C70:CIB_DCUA"].add_unknown(82, 10); + cc.tiles["CIB_R70C70:CIB_DCUA"].add_unknown(83, 10); + cc.tiles["CIB_R70C70:CIB_DCUA"].add_unknown(84, 10); + cc.tiles["CIB_R70C70:CIB_DCUA"].add_unknown(85, 10); + cc.tiles["CIB_R70C71:CIB_DCUB"].add_unknown(20, 10); + cc.tiles["CIB_R70C71:CIB_DCUB"].add_unknown(21, 10); + cc.tiles["CIB_R70C71:CIB_DCUB"].add_unknown(22, 10); + cc.tiles["CIB_R70C71:CIB_DCUB"].add_unknown(23, 10); + cc.tiles["CIB_R70C71:CIB_DCUB"].add_unknown(28, 10); + cc.tiles["CIB_R70C71:CIB_DCUB"].add_unknown(29, 10); + cc.tiles["CIB_R70C71:CIB_DCUB"].add_unknown(30, 10); + cc.tiles["CIB_R70C71:CIB_DCUB"].add_unknown(31, 10); + cc.tiles["CIB_R70C71:CIB_DCUB"].add_unknown(74, 10); + cc.tiles["CIB_R70C71:CIB_DCUB"].add_unknown(75, 10); + cc.tiles["CIB_R70C71:CIB_DCUB"].add_unknown(76, 10); + cc.tiles["CIB_R70C71:CIB_DCUB"].add_unknown(77, 10); + cc.tiles["CIB_R70C71:CIB_DCUB"].add_unknown(82, 10); + cc.tiles["CIB_R70C71:CIB_DCUB"].add_unknown(83, 10); + cc.tiles["CIB_R70C71:CIB_DCUB"].add_unknown(84, 10); + cc.tiles["CIB_R70C71:CIB_DCUB"].add_unknown(85, 10); + cc.tiles["CIB_R70C72:CIB_DCUC"].add_unknown(20, 10); + cc.tiles["CIB_R70C72:CIB_DCUC"].add_unknown(21, 10); + cc.tiles["CIB_R70C72:CIB_DCUC"].add_unknown(22, 10); + cc.tiles["CIB_R70C72:CIB_DCUC"].add_unknown(23, 10); + cc.tiles["CIB_R70C72:CIB_DCUC"].add_unknown(28, 10); + cc.tiles["CIB_R70C72:CIB_DCUC"].add_unknown(29, 10); + cc.tiles["CIB_R70C72:CIB_DCUC"].add_unknown(30, 10); + cc.tiles["CIB_R70C72:CIB_DCUC"].add_unknown(31, 10); + cc.tiles["CIB_R70C72:CIB_DCUC"].add_unknown(74, 10); + cc.tiles["CIB_R70C72:CIB_DCUC"].add_unknown(75, 10); + cc.tiles["CIB_R70C72:CIB_DCUC"].add_unknown(76, 10); + cc.tiles["CIB_R70C72:CIB_DCUC"].add_unknown(77, 10); + cc.tiles["CIB_R70C72:CIB_DCUC"].add_unknown(82, 10); + cc.tiles["CIB_R70C72:CIB_DCUC"].add_unknown(83, 10); + cc.tiles["CIB_R70C72:CIB_DCUC"].add_unknown(84, 10); + cc.tiles["CIB_R70C72:CIB_DCUC"].add_unknown(85, 10); + cc.tiles["CIB_R70C73:CIB_DCUD"].add_unknown(20, 10); + cc.tiles["CIB_R70C73:CIB_DCUD"].add_unknown(21, 10); + cc.tiles["CIB_R70C73:CIB_DCUD"].add_unknown(22, 10); + cc.tiles["CIB_R70C73:CIB_DCUD"].add_unknown(23, 10); + cc.tiles["CIB_R70C73:CIB_DCUD"].add_unknown(28, 10); + cc.tiles["CIB_R70C73:CIB_DCUD"].add_unknown(29, 10); + cc.tiles["CIB_R70C73:CIB_DCUD"].add_unknown(31, 10); + cc.tiles["CIB_R70C73:CIB_DCUD"].add_unknown(74, 10); + cc.tiles["CIB_R70C73:CIB_DCUD"].add_unknown(75, 10); + cc.tiles["CIB_R70C73:CIB_DCUD"].add_unknown(76, 10); + cc.tiles["CIB_R70C73:CIB_DCUD"].add_unknown(77, 10); + cc.tiles["CIB_R70C73:CIB_DCUD"].add_unknown(82, 10); + cc.tiles["CIB_R70C73:CIB_DCUD"].add_unknown(83, 10); + cc.tiles["CIB_R70C73:CIB_DCUD"].add_unknown(84, 10); + cc.tiles["CIB_R70C73:CIB_DCUD"].add_unknown(85, 10); + cc.tiles["CIB_R70C74:CIB_DCUF"].add_unknown(20, 10); + cc.tiles["CIB_R70C74:CIB_DCUF"].add_unknown(21, 10); + cc.tiles["CIB_R70C74:CIB_DCUF"].add_unknown(22, 10); + cc.tiles["CIB_R70C74:CIB_DCUF"].add_unknown(23, 10); + cc.tiles["CIB_R70C74:CIB_DCUF"].add_unknown(28, 10); + cc.tiles["CIB_R70C74:CIB_DCUF"].add_unknown(29, 10); + cc.tiles["CIB_R70C74:CIB_DCUF"].add_unknown(30, 10); + cc.tiles["CIB_R70C74:CIB_DCUF"].add_unknown(31, 10); + cc.tiles["CIB_R70C74:CIB_DCUF"].add_unknown(74, 10); + cc.tiles["CIB_R70C74:CIB_DCUF"].add_unknown(75, 10); + cc.tiles["CIB_R70C74:CIB_DCUF"].add_unknown(76, 10); + cc.tiles["CIB_R70C74:CIB_DCUF"].add_unknown(77, 10); + cc.tiles["CIB_R70C74:CIB_DCUF"].add_unknown(82, 10); + cc.tiles["CIB_R70C74:CIB_DCUF"].add_unknown(83, 10); + cc.tiles["CIB_R70C74:CIB_DCUF"].add_unknown(84, 10); + cc.tiles["CIB_R70C74:CIB_DCUF"].add_unknown(85, 10); + cc.tiles["CIB_R70C75:CIB_DCU3"].add_unknown(20, 10); + cc.tiles["CIB_R70C75:CIB_DCU3"].add_unknown(22, 10); + cc.tiles["CIB_R70C75:CIB_DCU3"].add_unknown(23, 10); + cc.tiles["CIB_R70C75:CIB_DCU3"].add_unknown(29, 10); + cc.tiles["CIB_R70C75:CIB_DCU3"].add_unknown(31, 10); + cc.tiles["CIB_R70C75:CIB_DCU3"].add_unknown(74, 10); + cc.tiles["CIB_R70C75:CIB_DCU3"].add_unknown(75, 10); + cc.tiles["CIB_R70C75:CIB_DCU3"].add_unknown(76, 10); + cc.tiles["CIB_R70C75:CIB_DCU3"].add_unknown(77, 10); + cc.tiles["CIB_R70C75:CIB_DCU3"].add_unknown(82, 10); + cc.tiles["CIB_R70C75:CIB_DCU3"].add_unknown(83, 10); + cc.tiles["CIB_R70C75:CIB_DCU3"].add_unknown(84, 10); + cc.tiles["CIB_R70C75:CIB_DCU3"].add_unknown(85, 10); + cc.tiles["CIB_R70C76:CIB_DCU2"].add_unknown(20, 10); + cc.tiles["CIB_R70C76:CIB_DCU2"].add_unknown(22, 10); + cc.tiles["CIB_R70C76:CIB_DCU2"].add_unknown(29, 10); + cc.tiles["CIB_R70C76:CIB_DCU2"].add_unknown(31, 10); + cc.tiles["CIB_R70C76:CIB_DCU2"].add_unknown(74, 10); + cc.tiles["CIB_R70C76:CIB_DCU2"].add_unknown(76, 10); + cc.tiles["CIB_R70C76:CIB_DCU2"].add_unknown(83, 10); + cc.tiles["CIB_R70C76:CIB_DCU2"].add_unknown(85, 10); + cc.tiles["CIB_R70C77:CIB_DCUG"].add_unknown(20, 10); + cc.tiles["CIB_R70C77:CIB_DCUG"].add_unknown(22, 10); + cc.tiles["CIB_R70C77:CIB_DCUG"].add_unknown(29, 10); + cc.tiles["CIB_R70C77:CIB_DCUG"].add_unknown(31, 10); + cc.tiles["CIB_R70C77:CIB_DCUG"].add_unknown(74, 10); + cc.tiles["CIB_R70C77:CIB_DCUG"].add_unknown(76, 10); + cc.tiles["CIB_R70C77:CIB_DCUG"].add_unknown(83, 10); + cc.tiles["CIB_R70C77:CIB_DCUG"].add_unknown(85, 10); + cc.tiles["CIB_R70C78:CIB_DCUH"].add_unknown(20, 10); + cc.tiles["CIB_R70C78:CIB_DCUH"].add_unknown(22, 10); + cc.tiles["CIB_R70C78:CIB_DCUH"].add_unknown(29, 10); + cc.tiles["CIB_R70C78:CIB_DCUH"].add_unknown(31, 10); + cc.tiles["CIB_R70C78:CIB_DCUH"].add_unknown(74, 10); + cc.tiles["CIB_R70C78:CIB_DCUH"].add_unknown(76, 10); + cc.tiles["CIB_R70C78:CIB_DCUH"].add_unknown(83, 10); + cc.tiles["CIB_R70C78:CIB_DCUH"].add_unknown(85, 10); + cc.tiles["CIB_R70C79:CIB_DCUI"].add_unknown(20, 10); + cc.tiles["CIB_R70C79:CIB_DCUI"].add_unknown(22, 10); + cc.tiles["CIB_R70C79:CIB_DCUI"].add_unknown(29, 10); + cc.tiles["CIB_R70C79:CIB_DCUI"].add_unknown(31, 10); + cc.tiles["CIB_R70C79:CIB_DCUI"].add_unknown(74, 10); + cc.tiles["CIB_R70C79:CIB_DCUI"].add_unknown(76, 10); + cc.tiles["CIB_R70C79:CIB_DCUI"].add_unknown(83, 10); + cc.tiles["CIB_R70C79:CIB_DCUI"].add_unknown(85, 10); + cc.tiles["CIB_R70C7:CIB_EFB1"].add_enum("CIB.JA3MUX", "0"); + cc.tiles["CIB_R70C7:CIB_EFB1"].add_enum("CIB.JA4MUX", "0"); + cc.tiles["CIB_R70C7:CIB_EFB1"].add_enum("CIB.JA5MUX", "0"); + cc.tiles["CIB_R70C7:CIB_EFB1"].add_enum("CIB.JA6MUX", "0"); + cc.tiles["CIB_R70C7:CIB_EFB1"].add_enum("CIB.JB3MUX", "0"); + cc.tiles["CIB_R70C7:CIB_EFB1"].add_enum("CIB.JB4MUX", "0"); + cc.tiles["CIB_R70C7:CIB_EFB1"].add_enum("CIB.JB5MUX", "0"); + cc.tiles["CIB_R70C7:CIB_EFB1"].add_enum("CIB.JB6MUX", "0"); + cc.tiles["CIB_R70C7:CIB_EFB1"].add_enum("CIB.JC3MUX", "0"); + cc.tiles["CIB_R70C7:CIB_EFB1"].add_enum("CIB.JC4MUX", "0"); + cc.tiles["CIB_R70C7:CIB_EFB1"].add_enum("CIB.JC5MUX", "0"); + cc.tiles["CIB_R70C7:CIB_EFB1"].add_enum("CIB.JD3MUX", "0"); + cc.tiles["CIB_R70C7:CIB_EFB1"].add_enum("CIB.JD4MUX", "0"); + cc.tiles["CIB_R70C7:CIB_EFB1"].add_enum("CIB.JD5MUX", "0"); + cc.tiles["CIB_R70C80:CIB_DCU1"].add_unknown(20, 10); + cc.tiles["CIB_R70C80:CIB_DCU1"].add_unknown(22, 10); + cc.tiles["CIB_R70C80:CIB_DCU1"].add_unknown(29, 10); + cc.tiles["CIB_R70C80:CIB_DCU1"].add_unknown(31, 10); + cc.tiles["CIB_R70C80:CIB_DCU1"].add_unknown(74, 10); + cc.tiles["CIB_R70C87:CIB_PLL3"].add_enum("CIB.JA3MUX", "0"); + cc.tiles["CIB_R70C87:CIB_PLL3"].add_enum("CIB.JB3MUX", "0"); + cc.tiles["MIB_R10C40:CMUX_UL_0"].add_arc("G_DCS0CLK0", "G_VPFN0000"); + cc.tiles["MIB_R10C41:CMUX_UR_0"].add_arc("G_DCS0CLK1", "G_VPFN0000"); + cc.tiles["MIB_R58C40:CMUX_LL_0"].add_arc("G_DCS1CLK0", "G_VPFN0000"); + cc.tiles["MIB_R58C41:CMUX_LR_0"].add_arc("G_DCS1CLK1", "G_VPFN0000"); + cc.tiles["MIB_R71C4:EFB0_PICB0"].add_unknown(54, 1); + cc.tiles["MIB_R71C4:EFB0_PICB0"].add_unknown(56, 1); + cc.tiles["MIB_R71C4:EFB0_PICB0"].add_unknown(82, 1); + cc.tiles["MIB_R71C4:EFB0_PICB0"].add_unknown(94, 1); +} + +void config_empty_lfe5um5g_85f(ChipConfig &cc) +{ + cc.chip_name = "LFE5UM5G-85F"; + cc.tiles["CIB_R10C3:PVT_COUNT2"].add_unknown(2, 0); + cc.tiles["CIB_R10C3:PVT_COUNT2"].add_unknown(3, 0); + cc.tiles["CIB_R10C3:PVT_COUNT2"].add_unknown(5, 0); + cc.tiles["CIB_R10C3:PVT_COUNT2"].add_unknown(11, 0); + cc.tiles["CIB_R10C3:PVT_COUNT2"].add_unknown(13, 0); + cc.tiles["CIB_R5C125:CIB_PLL1"].add_enum("CIB.JA3MUX", "0"); + cc.tiles["CIB_R5C125:CIB_PLL1"].add_enum("CIB.JB3MUX", "0"); + cc.tiles["CIB_R5C1:CIB_PLL1"].add_enum("CIB.JA3MUX", "0"); + cc.tiles["CIB_R5C1:CIB_PLL1"].add_enum("CIB.JB3MUX", "0"); + cc.tiles["CIB_R94C123:CIB_PLL3"].add_enum("CIB.JA3MUX", "0"); + cc.tiles["CIB_R94C123:CIB_PLL3"].add_enum("CIB.JB3MUX", "0"); + cc.tiles["CIB_R94C3:CIB_PLL3"].add_enum("CIB.JA3MUX", "0"); + cc.tiles["CIB_R94C3:CIB_PLL3"].add_enum("CIB.JB3MUX", "0"); + cc.tiles["CIB_R94C46:CIB_DCU0"].add_unknown(20, 10); + cc.tiles["CIB_R94C46:CIB_DCU0"].add_unknown(21, 10); + cc.tiles["CIB_R94C46:CIB_DCU0"].add_unknown(22, 10); + cc.tiles["CIB_R94C46:CIB_DCU0"].add_unknown(23, 10); + cc.tiles["CIB_R94C46:CIB_DCU0"].add_unknown(28, 10); + cc.tiles["CIB_R94C46:CIB_DCU0"].add_unknown(29, 10); + cc.tiles["CIB_R94C46:CIB_DCU0"].add_unknown(30, 10); + cc.tiles["CIB_R94C46:CIB_DCU0"].add_unknown(31, 10); + cc.tiles["CIB_R94C46:CIB_DCU0"].add_unknown(74, 10); + cc.tiles["CIB_R94C46:CIB_DCU0"].add_unknown(75, 10); + cc.tiles["CIB_R94C46:CIB_DCU0"].add_unknown(76, 10); + cc.tiles["CIB_R94C46:CIB_DCU0"].add_unknown(77, 10); + cc.tiles["CIB_R94C46:CIB_DCU0"].add_unknown(82, 10); + cc.tiles["CIB_R94C46:CIB_DCU0"].add_unknown(83, 10); + cc.tiles["CIB_R94C46:CIB_DCU0"].add_unknown(84, 10); + cc.tiles["CIB_R94C46:CIB_DCU0"].add_unknown(85, 10); + cc.tiles["CIB_R94C47:CIB_DCUA"].add_unknown(20, 10); + cc.tiles["CIB_R94C47:CIB_DCUA"].add_unknown(21, 10); + cc.tiles["CIB_R94C47:CIB_DCUA"].add_unknown(22, 10); + cc.tiles["CIB_R94C47:CIB_DCUA"].add_unknown(23, 10); + cc.tiles["CIB_R94C47:CIB_DCUA"].add_unknown(28, 10); + cc.tiles["CIB_R94C47:CIB_DCUA"].add_unknown(29, 10); + cc.tiles["CIB_R94C47:CIB_DCUA"].add_unknown(30, 10); + cc.tiles["CIB_R94C47:CIB_DCUA"].add_unknown(31, 10); + cc.tiles["CIB_R94C47:CIB_DCUA"].add_unknown(74, 10); + cc.tiles["CIB_R94C47:CIB_DCUA"].add_unknown(75, 10); + cc.tiles["CIB_R94C47:CIB_DCUA"].add_unknown(76, 10); + cc.tiles["CIB_R94C47:CIB_DCUA"].add_unknown(77, 10); + cc.tiles["CIB_R94C47:CIB_DCUA"].add_unknown(82, 10); + cc.tiles["CIB_R94C47:CIB_DCUA"].add_unknown(83, 10); + cc.tiles["CIB_R94C47:CIB_DCUA"].add_unknown(84, 10); + cc.tiles["CIB_R94C47:CIB_DCUA"].add_unknown(85, 10); + cc.tiles["CIB_R94C48:CIB_DCUB"].add_unknown(20, 10); + cc.tiles["CIB_R94C48:CIB_DCUB"].add_unknown(21, 10); + cc.tiles["CIB_R94C48:CIB_DCUB"].add_unknown(22, 10); + cc.tiles["CIB_R94C48:CIB_DCUB"].add_unknown(23, 10); + cc.tiles["CIB_R94C48:CIB_DCUB"].add_unknown(28, 10); + cc.tiles["CIB_R94C48:CIB_DCUB"].add_unknown(29, 10); + cc.tiles["CIB_R94C48:CIB_DCUB"].add_unknown(30, 10); + cc.tiles["CIB_R94C48:CIB_DCUB"].add_unknown(31, 10); + cc.tiles["CIB_R94C48:CIB_DCUB"].add_unknown(74, 10); + cc.tiles["CIB_R94C48:CIB_DCUB"].add_unknown(75, 10); + cc.tiles["CIB_R94C48:CIB_DCUB"].add_unknown(76, 10); + cc.tiles["CIB_R94C48:CIB_DCUB"].add_unknown(77, 10); + cc.tiles["CIB_R94C48:CIB_DCUB"].add_unknown(82, 10); + cc.tiles["CIB_R94C48:CIB_DCUB"].add_unknown(83, 10); + cc.tiles["CIB_R94C48:CIB_DCUB"].add_unknown(84, 10); + cc.tiles["CIB_R94C48:CIB_DCUB"].add_unknown(85, 10); + cc.tiles["CIB_R94C49:CIB_DCUC"].add_unknown(20, 10); + cc.tiles["CIB_R94C49:CIB_DCUC"].add_unknown(21, 10); + cc.tiles["CIB_R94C49:CIB_DCUC"].add_unknown(22, 10); + cc.tiles["CIB_R94C49:CIB_DCUC"].add_unknown(23, 10); + cc.tiles["CIB_R94C49:CIB_DCUC"].add_unknown(28, 10); + cc.tiles["CIB_R94C49:CIB_DCUC"].add_unknown(29, 10); + cc.tiles["CIB_R94C49:CIB_DCUC"].add_unknown(30, 10); + cc.tiles["CIB_R94C49:CIB_DCUC"].add_unknown(31, 10); + cc.tiles["CIB_R94C49:CIB_DCUC"].add_unknown(74, 10); + cc.tiles["CIB_R94C49:CIB_DCUC"].add_unknown(75, 10); + cc.tiles["CIB_R94C49:CIB_DCUC"].add_unknown(76, 10); + cc.tiles["CIB_R94C49:CIB_DCUC"].add_unknown(77, 10); + cc.tiles["CIB_R94C49:CIB_DCUC"].add_unknown(82, 10); + cc.tiles["CIB_R94C49:CIB_DCUC"].add_unknown(83, 10); + cc.tiles["CIB_R94C49:CIB_DCUC"].add_unknown(84, 10); + cc.tiles["CIB_R94C49:CIB_DCUC"].add_unknown(85, 10); + cc.tiles["CIB_R94C50:CIB_DCUD"].add_unknown(20, 10); + cc.tiles["CIB_R94C50:CIB_DCUD"].add_unknown(21, 10); + cc.tiles["CIB_R94C50:CIB_DCUD"].add_unknown(22, 10); + cc.tiles["CIB_R94C50:CIB_DCUD"].add_unknown(23, 10); + cc.tiles["CIB_R94C50:CIB_DCUD"].add_unknown(28, 10); + cc.tiles["CIB_R94C50:CIB_DCUD"].add_unknown(29, 10); + cc.tiles["CIB_R94C50:CIB_DCUD"].add_unknown(31, 10); + cc.tiles["CIB_R94C50:CIB_DCUD"].add_unknown(74, 10); + cc.tiles["CIB_R94C50:CIB_DCUD"].add_unknown(75, 10); + cc.tiles["CIB_R94C50:CIB_DCUD"].add_unknown(76, 10); + cc.tiles["CIB_R94C50:CIB_DCUD"].add_unknown(77, 10); + cc.tiles["CIB_R94C50:CIB_DCUD"].add_unknown(82, 10); + cc.tiles["CIB_R94C50:CIB_DCUD"].add_unknown(83, 10); + cc.tiles["CIB_R94C50:CIB_DCUD"].add_unknown(84, 10); + cc.tiles["CIB_R94C50:CIB_DCUD"].add_unknown(85, 10); + cc.tiles["CIB_R94C51:CIB_DCUF"].add_unknown(20, 10); + cc.tiles["CIB_R94C51:CIB_DCUF"].add_unknown(21, 10); + cc.tiles["CIB_R94C51:CIB_DCUF"].add_unknown(22, 10); + cc.tiles["CIB_R94C51:CIB_DCUF"].add_unknown(23, 10); + cc.tiles["CIB_R94C51:CIB_DCUF"].add_unknown(28, 10); + cc.tiles["CIB_R94C51:CIB_DCUF"].add_unknown(29, 10); + cc.tiles["CIB_R94C51:CIB_DCUF"].add_unknown(30, 10); + cc.tiles["CIB_R94C51:CIB_DCUF"].add_unknown(31, 10); + cc.tiles["CIB_R94C51:CIB_DCUF"].add_unknown(74, 10); + cc.tiles["CIB_R94C51:CIB_DCUF"].add_unknown(75, 10); + cc.tiles["CIB_R94C51:CIB_DCUF"].add_unknown(76, 10); + cc.tiles["CIB_R94C51:CIB_DCUF"].add_unknown(77, 10); + cc.tiles["CIB_R94C51:CIB_DCUF"].add_unknown(82, 10); + cc.tiles["CIB_R94C51:CIB_DCUF"].add_unknown(83, 10); + cc.tiles["CIB_R94C51:CIB_DCUF"].add_unknown(84, 10); + cc.tiles["CIB_R94C51:CIB_DCUF"].add_unknown(85, 10); + cc.tiles["CIB_R94C52:CIB_DCU3"].add_unknown(20, 10); + cc.tiles["CIB_R94C52:CIB_DCU3"].add_unknown(22, 10); + cc.tiles["CIB_R94C52:CIB_DCU3"].add_unknown(23, 10); + cc.tiles["CIB_R94C52:CIB_DCU3"].add_unknown(29, 10); + cc.tiles["CIB_R94C52:CIB_DCU3"].add_unknown(31, 10); + cc.tiles["CIB_R94C52:CIB_DCU3"].add_unknown(74, 10); + cc.tiles["CIB_R94C52:CIB_DCU3"].add_unknown(75, 10); + cc.tiles["CIB_R94C52:CIB_DCU3"].add_unknown(76, 10); + cc.tiles["CIB_R94C52:CIB_DCU3"].add_unknown(77, 10); + cc.tiles["CIB_R94C52:CIB_DCU3"].add_unknown(82, 10); + cc.tiles["CIB_R94C52:CIB_DCU3"].add_unknown(83, 10); + cc.tiles["CIB_R94C52:CIB_DCU3"].add_unknown(84, 10); + cc.tiles["CIB_R94C52:CIB_DCU3"].add_unknown(85, 10); + cc.tiles["CIB_R94C53:CIB_DCU2"].add_unknown(20, 10); + cc.tiles["CIB_R94C53:CIB_DCU2"].add_unknown(22, 10); + cc.tiles["CIB_R94C53:CIB_DCU2"].add_unknown(29, 10); + cc.tiles["CIB_R94C53:CIB_DCU2"].add_unknown(31, 10); + cc.tiles["CIB_R94C53:CIB_DCU2"].add_unknown(74, 10); + cc.tiles["CIB_R94C53:CIB_DCU2"].add_unknown(76, 10); + cc.tiles["CIB_R94C53:CIB_DCU2"].add_unknown(83, 10); + cc.tiles["CIB_R94C53:CIB_DCU2"].add_unknown(85, 10); + cc.tiles["CIB_R94C54:CIB_DCUG"].add_unknown(20, 10); + cc.tiles["CIB_R94C54:CIB_DCUG"].add_unknown(22, 10); + cc.tiles["CIB_R94C54:CIB_DCUG"].add_unknown(29, 10); + cc.tiles["CIB_R94C54:CIB_DCUG"].add_unknown(31, 10); + cc.tiles["CIB_R94C54:CIB_DCUG"].add_unknown(74, 10); + cc.tiles["CIB_R94C54:CIB_DCUG"].add_unknown(76, 10); + cc.tiles["CIB_R94C54:CIB_DCUG"].add_unknown(83, 10); + cc.tiles["CIB_R94C54:CIB_DCUG"].add_unknown(85, 10); + cc.tiles["CIB_R94C55:CIB_DCUH"].add_unknown(20, 10); + cc.tiles["CIB_R94C55:CIB_DCUH"].add_unknown(22, 10); + cc.tiles["CIB_R94C55:CIB_DCUH"].add_unknown(29, 10); + cc.tiles["CIB_R94C55:CIB_DCUH"].add_unknown(31, 10); + cc.tiles["CIB_R94C55:CIB_DCUH"].add_unknown(74, 10); + cc.tiles["CIB_R94C55:CIB_DCUH"].add_unknown(76, 10); + cc.tiles["CIB_R94C55:CIB_DCUH"].add_unknown(83, 10); + cc.tiles["CIB_R94C55:CIB_DCUH"].add_unknown(85, 10); + cc.tiles["CIB_R94C56:CIB_DCUI"].add_unknown(20, 10); + cc.tiles["CIB_R94C56:CIB_DCUI"].add_unknown(22, 10); + cc.tiles["CIB_R94C56:CIB_DCUI"].add_unknown(29, 10); + cc.tiles["CIB_R94C56:CIB_DCUI"].add_unknown(31, 10); + cc.tiles["CIB_R94C56:CIB_DCUI"].add_unknown(74, 10); + cc.tiles["CIB_R94C56:CIB_DCUI"].add_unknown(76, 10); + cc.tiles["CIB_R94C56:CIB_DCUI"].add_unknown(83, 10); + cc.tiles["CIB_R94C56:CIB_DCUI"].add_unknown(85, 10); + cc.tiles["CIB_R94C57:CIB_DCU1"].add_unknown(20, 10); + cc.tiles["CIB_R94C57:CIB_DCU1"].add_unknown(22, 10); + cc.tiles["CIB_R94C57:CIB_DCU1"].add_unknown(29, 10); + cc.tiles["CIB_R94C57:CIB_DCU1"].add_unknown(31, 10); + cc.tiles["CIB_R94C57:CIB_DCU1"].add_unknown(74, 10); + cc.tiles["CIB_R94C6:CIB_EFB0"].add_enum("CIB.JB3MUX", "0"); + cc.tiles["CIB_R94C6:CIB_EFB0"].add_enum("CIB.JC6MUX", "0"); + cc.tiles["CIB_R94C6:CIB_EFB0"].add_enum("CIB.JD6MUX", "0"); + cc.tiles["CIB_R94C71:CIB_DCU0"].add_unknown(20, 10); + cc.tiles["CIB_R94C71:CIB_DCU0"].add_unknown(21, 10); + cc.tiles["CIB_R94C71:CIB_DCU0"].add_unknown(22, 10); + cc.tiles["CIB_R94C71:CIB_DCU0"].add_unknown(23, 10); + cc.tiles["CIB_R94C71:CIB_DCU0"].add_unknown(28, 10); + cc.tiles["CIB_R94C71:CIB_DCU0"].add_unknown(29, 10); + cc.tiles["CIB_R94C71:CIB_DCU0"].add_unknown(30, 10); + cc.tiles["CIB_R94C71:CIB_DCU0"].add_unknown(31, 10); + cc.tiles["CIB_R94C71:CIB_DCU0"].add_unknown(74, 10); + cc.tiles["CIB_R94C71:CIB_DCU0"].add_unknown(75, 10); + cc.tiles["CIB_R94C71:CIB_DCU0"].add_unknown(76, 10); + cc.tiles["CIB_R94C71:CIB_DCU0"].add_unknown(77, 10); + cc.tiles["CIB_R94C71:CIB_DCU0"].add_unknown(82, 10); + cc.tiles["CIB_R94C71:CIB_DCU0"].add_unknown(83, 10); + cc.tiles["CIB_R94C71:CIB_DCU0"].add_unknown(84, 10); + cc.tiles["CIB_R94C71:CIB_DCU0"].add_unknown(85, 10); + cc.tiles["CIB_R94C72:CIB_DCUA"].add_unknown(20, 10); + cc.tiles["CIB_R94C72:CIB_DCUA"].add_unknown(21, 10); + cc.tiles["CIB_R94C72:CIB_DCUA"].add_unknown(22, 10); + cc.tiles["CIB_R94C72:CIB_DCUA"].add_unknown(23, 10); + cc.tiles["CIB_R94C72:CIB_DCUA"].add_unknown(28, 10); + cc.tiles["CIB_R94C72:CIB_DCUA"].add_unknown(29, 10); + cc.tiles["CIB_R94C72:CIB_DCUA"].add_unknown(30, 10); + cc.tiles["CIB_R94C72:CIB_DCUA"].add_unknown(31, 10); + cc.tiles["CIB_R94C72:CIB_DCUA"].add_unknown(74, 10); + cc.tiles["CIB_R94C72:CIB_DCUA"].add_unknown(75, 10); + cc.tiles["CIB_R94C72:CIB_DCUA"].add_unknown(76, 10); + cc.tiles["CIB_R94C72:CIB_DCUA"].add_unknown(77, 10); + cc.tiles["CIB_R94C72:CIB_DCUA"].add_unknown(82, 10); + cc.tiles["CIB_R94C72:CIB_DCUA"].add_unknown(83, 10); + cc.tiles["CIB_R94C72:CIB_DCUA"].add_unknown(84, 10); + cc.tiles["CIB_R94C72:CIB_DCUA"].add_unknown(85, 10); + cc.tiles["CIB_R94C73:CIB_DCUB"].add_unknown(20, 10); + cc.tiles["CIB_R94C73:CIB_DCUB"].add_unknown(21, 10); + cc.tiles["CIB_R94C73:CIB_DCUB"].add_unknown(22, 10); + cc.tiles["CIB_R94C73:CIB_DCUB"].add_unknown(23, 10); + cc.tiles["CIB_R94C73:CIB_DCUB"].add_unknown(28, 10); + cc.tiles["CIB_R94C73:CIB_DCUB"].add_unknown(29, 10); + cc.tiles["CIB_R94C73:CIB_DCUB"].add_unknown(30, 10); + cc.tiles["CIB_R94C73:CIB_DCUB"].add_unknown(31, 10); + cc.tiles["CIB_R94C73:CIB_DCUB"].add_unknown(74, 10); + cc.tiles["CIB_R94C73:CIB_DCUB"].add_unknown(75, 10); + cc.tiles["CIB_R94C73:CIB_DCUB"].add_unknown(76, 10); + cc.tiles["CIB_R94C73:CIB_DCUB"].add_unknown(77, 10); + cc.tiles["CIB_R94C73:CIB_DCUB"].add_unknown(82, 10); + cc.tiles["CIB_R94C73:CIB_DCUB"].add_unknown(83, 10); + cc.tiles["CIB_R94C73:CIB_DCUB"].add_unknown(84, 10); + cc.tiles["CIB_R94C73:CIB_DCUB"].add_unknown(85, 10); + cc.tiles["CIB_R94C74:CIB_DCUC"].add_unknown(20, 10); + cc.tiles["CIB_R94C74:CIB_DCUC"].add_unknown(21, 10); + cc.tiles["CIB_R94C74:CIB_DCUC"].add_unknown(22, 10); + cc.tiles["CIB_R94C74:CIB_DCUC"].add_unknown(23, 10); + cc.tiles["CIB_R94C74:CIB_DCUC"].add_unknown(28, 10); + cc.tiles["CIB_R94C74:CIB_DCUC"].add_unknown(29, 10); + cc.tiles["CIB_R94C74:CIB_DCUC"].add_unknown(30, 10); + cc.tiles["CIB_R94C74:CIB_DCUC"].add_unknown(31, 10); + cc.tiles["CIB_R94C74:CIB_DCUC"].add_unknown(74, 10); + cc.tiles["CIB_R94C74:CIB_DCUC"].add_unknown(75, 10); + cc.tiles["CIB_R94C74:CIB_DCUC"].add_unknown(76, 10); + cc.tiles["CIB_R94C74:CIB_DCUC"].add_unknown(77, 10); + cc.tiles["CIB_R94C74:CIB_DCUC"].add_unknown(82, 10); + cc.tiles["CIB_R94C74:CIB_DCUC"].add_unknown(83, 10); + cc.tiles["CIB_R94C74:CIB_DCUC"].add_unknown(84, 10); + cc.tiles["CIB_R94C74:CIB_DCUC"].add_unknown(85, 10); + cc.tiles["CIB_R94C75:CIB_DCUD"].add_unknown(20, 10); + cc.tiles["CIB_R94C75:CIB_DCUD"].add_unknown(21, 10); + cc.tiles["CIB_R94C75:CIB_DCUD"].add_unknown(22, 10); + cc.tiles["CIB_R94C75:CIB_DCUD"].add_unknown(23, 10); + cc.tiles["CIB_R94C75:CIB_DCUD"].add_unknown(28, 10); + cc.tiles["CIB_R94C75:CIB_DCUD"].add_unknown(29, 10); + cc.tiles["CIB_R94C75:CIB_DCUD"].add_unknown(31, 10); + cc.tiles["CIB_R94C75:CIB_DCUD"].add_unknown(74, 10); + cc.tiles["CIB_R94C75:CIB_DCUD"].add_unknown(75, 10); + cc.tiles["CIB_R94C75:CIB_DCUD"].add_unknown(76, 10); + cc.tiles["CIB_R94C75:CIB_DCUD"].add_unknown(77, 10); + cc.tiles["CIB_R94C75:CIB_DCUD"].add_unknown(82, 10); + cc.tiles["CIB_R94C75:CIB_DCUD"].add_unknown(83, 10); + cc.tiles["CIB_R94C75:CIB_DCUD"].add_unknown(84, 10); + cc.tiles["CIB_R94C75:CIB_DCUD"].add_unknown(85, 10); + cc.tiles["CIB_R94C76:CIB_DCUF"].add_unknown(20, 10); + cc.tiles["CIB_R94C76:CIB_DCUF"].add_unknown(21, 10); + cc.tiles["CIB_R94C76:CIB_DCUF"].add_unknown(22, 10); + cc.tiles["CIB_R94C76:CIB_DCUF"].add_unknown(23, 10); + cc.tiles["CIB_R94C76:CIB_DCUF"].add_unknown(28, 10); + cc.tiles["CIB_R94C76:CIB_DCUF"].add_unknown(29, 10); + cc.tiles["CIB_R94C76:CIB_DCUF"].add_unknown(30, 10); + cc.tiles["CIB_R94C76:CIB_DCUF"].add_unknown(31, 10); + cc.tiles["CIB_R94C76:CIB_DCUF"].add_unknown(74, 10); + cc.tiles["CIB_R94C76:CIB_DCUF"].add_unknown(75, 10); + cc.tiles["CIB_R94C76:CIB_DCUF"].add_unknown(76, 10); + cc.tiles["CIB_R94C76:CIB_DCUF"].add_unknown(77, 10); + cc.tiles["CIB_R94C76:CIB_DCUF"].add_unknown(82, 10); + cc.tiles["CIB_R94C76:CIB_DCUF"].add_unknown(83, 10); + cc.tiles["CIB_R94C76:CIB_DCUF"].add_unknown(84, 10); + cc.tiles["CIB_R94C76:CIB_DCUF"].add_unknown(85, 10); + cc.tiles["CIB_R94C77:CIB_DCU3"].add_unknown(20, 10); + cc.tiles["CIB_R94C77:CIB_DCU3"].add_unknown(22, 10); + cc.tiles["CIB_R94C77:CIB_DCU3"].add_unknown(23, 10); + cc.tiles["CIB_R94C77:CIB_DCU3"].add_unknown(29, 10); + cc.tiles["CIB_R94C77:CIB_DCU3"].add_unknown(31, 10); + cc.tiles["CIB_R94C77:CIB_DCU3"].add_unknown(74, 10); + cc.tiles["CIB_R94C77:CIB_DCU3"].add_unknown(75, 10); + cc.tiles["CIB_R94C77:CIB_DCU3"].add_unknown(76, 10); + cc.tiles["CIB_R94C77:CIB_DCU3"].add_unknown(77, 10); + cc.tiles["CIB_R94C77:CIB_DCU3"].add_unknown(82, 10); + cc.tiles["CIB_R94C77:CIB_DCU3"].add_unknown(83, 10); + cc.tiles["CIB_R94C77:CIB_DCU3"].add_unknown(84, 10); + cc.tiles["CIB_R94C77:CIB_DCU3"].add_unknown(85, 10); + cc.tiles["CIB_R94C78:CIB_DCU2"].add_unknown(20, 10); + cc.tiles["CIB_R94C78:CIB_DCU2"].add_unknown(22, 10); + cc.tiles["CIB_R94C78:CIB_DCU2"].add_unknown(29, 10); + cc.tiles["CIB_R94C78:CIB_DCU2"].add_unknown(31, 10); + cc.tiles["CIB_R94C78:CIB_DCU2"].add_unknown(74, 10); + cc.tiles["CIB_R94C78:CIB_DCU2"].add_unknown(76, 10); + cc.tiles["CIB_R94C78:CIB_DCU2"].add_unknown(83, 10); + cc.tiles["CIB_R94C78:CIB_DCU2"].add_unknown(85, 10); + cc.tiles["CIB_R94C79:CIB_DCUG"].add_unknown(20, 10); + cc.tiles["CIB_R94C79:CIB_DCUG"].add_unknown(22, 10); + cc.tiles["CIB_R94C79:CIB_DCUG"].add_unknown(29, 10); + cc.tiles["CIB_R94C79:CIB_DCUG"].add_unknown(31, 10); + cc.tiles["CIB_R94C79:CIB_DCUG"].add_unknown(74, 10); + cc.tiles["CIB_R94C79:CIB_DCUG"].add_unknown(76, 10); + cc.tiles["CIB_R94C79:CIB_DCUG"].add_unknown(83, 10); + cc.tiles["CIB_R94C79:CIB_DCUG"].add_unknown(85, 10); + cc.tiles["CIB_R94C7:CIB_EFB1"].add_enum("CIB.JA3MUX", "0"); + cc.tiles["CIB_R94C7:CIB_EFB1"].add_enum("CIB.JA4MUX", "0"); + cc.tiles["CIB_R94C7:CIB_EFB1"].add_enum("CIB.JA5MUX", "0"); + cc.tiles["CIB_R94C7:CIB_EFB1"].add_enum("CIB.JA6MUX", "0"); + cc.tiles["CIB_R94C7:CIB_EFB1"].add_enum("CIB.JB3MUX", "0"); + cc.tiles["CIB_R94C7:CIB_EFB1"].add_enum("CIB.JB4MUX", "0"); + cc.tiles["CIB_R94C7:CIB_EFB1"].add_enum("CIB.JB5MUX", "0"); + cc.tiles["CIB_R94C7:CIB_EFB1"].add_enum("CIB.JB6MUX", "0"); + cc.tiles["CIB_R94C7:CIB_EFB1"].add_enum("CIB.JC3MUX", "0"); + cc.tiles["CIB_R94C7:CIB_EFB1"].add_enum("CIB.JC4MUX", "0"); + cc.tiles["CIB_R94C7:CIB_EFB1"].add_enum("CIB.JC5MUX", "0"); + cc.tiles["CIB_R94C7:CIB_EFB1"].add_enum("CIB.JD3MUX", "0"); + cc.tiles["CIB_R94C7:CIB_EFB1"].add_enum("CIB.JD4MUX", "0"); + cc.tiles["CIB_R94C7:CIB_EFB1"].add_enum("CIB.JD5MUX", "0"); + cc.tiles["CIB_R94C80:CIB_DCUH"].add_unknown(20, 10); + cc.tiles["CIB_R94C80:CIB_DCUH"].add_unknown(22, 10); + cc.tiles["CIB_R94C80:CIB_DCUH"].add_unknown(29, 10); + cc.tiles["CIB_R94C80:CIB_DCUH"].add_unknown(31, 10); + cc.tiles["CIB_R94C80:CIB_DCUH"].add_unknown(74, 10); + cc.tiles["CIB_R94C80:CIB_DCUH"].add_unknown(76, 10); + cc.tiles["CIB_R94C80:CIB_DCUH"].add_unknown(83, 10); + cc.tiles["CIB_R94C80:CIB_DCUH"].add_unknown(85, 10); + cc.tiles["CIB_R94C81:CIB_DCUI"].add_unknown(20, 10); + cc.tiles["CIB_R94C81:CIB_DCUI"].add_unknown(22, 10); + cc.tiles["CIB_R94C81:CIB_DCUI"].add_unknown(29, 10); + cc.tiles["CIB_R94C81:CIB_DCUI"].add_unknown(31, 10); + cc.tiles["CIB_R94C81:CIB_DCUI"].add_unknown(74, 10); + cc.tiles["CIB_R94C81:CIB_DCUI"].add_unknown(76, 10); + cc.tiles["CIB_R94C81:CIB_DCUI"].add_unknown(83, 10); + cc.tiles["CIB_R94C81:CIB_DCUI"].add_unknown(85, 10); + cc.tiles["CIB_R94C82:CIB_DCU1"].add_unknown(20, 10); + cc.tiles["CIB_R94C82:CIB_DCU1"].add_unknown(22, 10); + cc.tiles["CIB_R94C82:CIB_DCU1"].add_unknown(29, 10); + cc.tiles["CIB_R94C82:CIB_DCU1"].add_unknown(31, 10); + cc.tiles["CIB_R94C82:CIB_DCU1"].add_unknown(74, 10); + cc.tiles["MIB_R22C67:CMUX_UL_0"].add_arc("G_DCS0CLK0", "G_VPFN0000"); + cc.tiles["MIB_R22C68:CMUX_UR_0"].add_arc("G_DCS0CLK1", "G_VPFN0000"); + cc.tiles["MIB_R70C67:CMUX_LL_0"].add_arc("G_DCS1CLK0", "G_VPFN0000"); + cc.tiles["MIB_R70C68:CMUX_LR_0"].add_arc("G_DCS1CLK1", "G_VPFN0000"); + cc.tiles["MIB_R95C101:PICB0"].add_unknown(0, 1); + cc.tiles["MIB_R95C102:PICB1"].add_unknown(0, 1); + cc.tiles["MIB_R95C103:PICB0"].add_unknown(0, 1); + cc.tiles["MIB_R95C104:PICB1"].add_unknown(0, 1); + cc.tiles["MIB_R95C105:PICB0"].add_unknown(0, 1); + cc.tiles["MIB_R95C106:PICB1"].add_unknown(0, 1); + cc.tiles["MIB_R95C107:PICB0"].add_unknown(0, 1); + cc.tiles["MIB_R95C108:PICB1"].add_unknown(0, 1); + cc.tiles["MIB_R95C110:PICB0"].add_unknown(0, 1); + cc.tiles["MIB_R95C111:PICB1"].add_unknown(0, 1); + cc.tiles["MIB_R95C112:PICB0"].add_unknown(0, 1); + cc.tiles["MIB_R95C113:PICB1"].add_unknown(0, 1); + cc.tiles["MIB_R95C114:PICB0"].add_unknown(0, 1); + cc.tiles["MIB_R95C115:PICB1"].add_unknown(0, 1); + cc.tiles["MIB_R95C116:PICB0"].add_unknown(0, 1); + cc.tiles["MIB_R95C117:PICB1"].add_unknown(0, 1); + cc.tiles["MIB_R95C119:PICB0"].add_unknown(0, 1); + cc.tiles["MIB_R95C120:PICB1"].add_unknown(0, 1); + cc.tiles["MIB_R95C121:PICB0"].add_unknown(0, 1); + cc.tiles["MIB_R95C122:PICB1"].add_unknown(0, 1); + cc.tiles["MIB_R95C4:EFB0_PICB0"].add_unknown(54, 1); + cc.tiles["MIB_R95C4:EFB0_PICB0"].add_unknown(56, 1); + cc.tiles["MIB_R95C4:EFB0_PICB0"].add_unknown(82, 1); + cc.tiles["MIB_R95C4:EFB0_PICB0"].add_unknown(94, 1); + cc.tiles["MIB_R95C96:PICB0"].add_unknown(0, 1); + cc.tiles["MIB_R95C97:PICB1"].add_unknown(0, 1); + cc.tiles["MIB_R95C98:PICB0"].add_unknown(0, 1); + cc.tiles["MIB_R95C99:PICB1"].add_unknown(0, 1); +} + +void config_empty_lfe5um_85f(ChipConfig &cc) +{ + cc.chip_name = "LFE5UM-85F"; + cc.tiles["CIB_R10C3:PVT_COUNT2"].add_unknown(2, 0); + cc.tiles["CIB_R10C3:PVT_COUNT2"].add_unknown(3, 0); + cc.tiles["CIB_R10C3:PVT_COUNT2"].add_unknown(5, 0); + cc.tiles["CIB_R10C3:PVT_COUNT2"].add_unknown(11, 0); + cc.tiles["CIB_R10C3:PVT_COUNT2"].add_unknown(13, 0); + cc.tiles["CIB_R5C125:CIB_PLL1"].add_enum("CIB.JA3MUX", "0"); + cc.tiles["CIB_R5C125:CIB_PLL1"].add_enum("CIB.JB3MUX", "0"); + cc.tiles["CIB_R5C1:CIB_PLL1"].add_enum("CIB.JA3MUX", "0"); + cc.tiles["CIB_R5C1:CIB_PLL1"].add_enum("CIB.JB3MUX", "0"); + cc.tiles["CIB_R94C123:CIB_PLL3"].add_enum("CIB.JA3MUX", "0"); + cc.tiles["CIB_R94C123:CIB_PLL3"].add_enum("CIB.JB3MUX", "0"); + cc.tiles["CIB_R94C3:CIB_PLL3"].add_enum("CIB.JA3MUX", "0"); + cc.tiles["CIB_R94C3:CIB_PLL3"].add_enum("CIB.JB3MUX", "0"); + cc.tiles["CIB_R94C46:CIB_DCU0"].add_unknown(20, 10); + cc.tiles["CIB_R94C46:CIB_DCU0"].add_unknown(21, 10); + cc.tiles["CIB_R94C46:CIB_DCU0"].add_unknown(22, 10); + cc.tiles["CIB_R94C46:CIB_DCU0"].add_unknown(23, 10); + cc.tiles["CIB_R94C46:CIB_DCU0"].add_unknown(28, 10); + cc.tiles["CIB_R94C46:CIB_DCU0"].add_unknown(29, 10); + cc.tiles["CIB_R94C46:CIB_DCU0"].add_unknown(30, 10); + cc.tiles["CIB_R94C46:CIB_DCU0"].add_unknown(31, 10); + cc.tiles["CIB_R94C46:CIB_DCU0"].add_unknown(74, 10); + cc.tiles["CIB_R94C46:CIB_DCU0"].add_unknown(75, 10); + cc.tiles["CIB_R94C46:CIB_DCU0"].add_unknown(76, 10); + cc.tiles["CIB_R94C46:CIB_DCU0"].add_unknown(77, 10); + cc.tiles["CIB_R94C46:CIB_DCU0"].add_unknown(82, 10); + cc.tiles["CIB_R94C46:CIB_DCU0"].add_unknown(83, 10); + cc.tiles["CIB_R94C46:CIB_DCU0"].add_unknown(84, 10); + cc.tiles["CIB_R94C46:CIB_DCU0"].add_unknown(85, 10); + cc.tiles["CIB_R94C47:CIB_DCUA"].add_unknown(20, 10); + cc.tiles["CIB_R94C47:CIB_DCUA"].add_unknown(21, 10); + cc.tiles["CIB_R94C47:CIB_DCUA"].add_unknown(22, 10); + cc.tiles["CIB_R94C47:CIB_DCUA"].add_unknown(23, 10); + cc.tiles["CIB_R94C47:CIB_DCUA"].add_unknown(28, 10); + cc.tiles["CIB_R94C47:CIB_DCUA"].add_unknown(29, 10); + cc.tiles["CIB_R94C47:CIB_DCUA"].add_unknown(30, 10); + cc.tiles["CIB_R94C47:CIB_DCUA"].add_unknown(31, 10); + cc.tiles["CIB_R94C47:CIB_DCUA"].add_unknown(74, 10); + cc.tiles["CIB_R94C47:CIB_DCUA"].add_unknown(75, 10); + cc.tiles["CIB_R94C47:CIB_DCUA"].add_unknown(76, 10); + cc.tiles["CIB_R94C47:CIB_DCUA"].add_unknown(77, 10); + cc.tiles["CIB_R94C47:CIB_DCUA"].add_unknown(82, 10); + cc.tiles["CIB_R94C47:CIB_DCUA"].add_unknown(83, 10); + cc.tiles["CIB_R94C47:CIB_DCUA"].add_unknown(84, 10); + cc.tiles["CIB_R94C47:CIB_DCUA"].add_unknown(85, 10); + cc.tiles["CIB_R94C48:CIB_DCUB"].add_unknown(20, 10); + cc.tiles["CIB_R94C48:CIB_DCUB"].add_unknown(21, 10); + cc.tiles["CIB_R94C48:CIB_DCUB"].add_unknown(22, 10); + cc.tiles["CIB_R94C48:CIB_DCUB"].add_unknown(23, 10); + cc.tiles["CIB_R94C48:CIB_DCUB"].add_unknown(28, 10); + cc.tiles["CIB_R94C48:CIB_DCUB"].add_unknown(29, 10); + cc.tiles["CIB_R94C48:CIB_DCUB"].add_unknown(30, 10); + cc.tiles["CIB_R94C48:CIB_DCUB"].add_unknown(31, 10); + cc.tiles["CIB_R94C48:CIB_DCUB"].add_unknown(74, 10); + cc.tiles["CIB_R94C48:CIB_DCUB"].add_unknown(75, 10); + cc.tiles["CIB_R94C48:CIB_DCUB"].add_unknown(76, 10); + cc.tiles["CIB_R94C48:CIB_DCUB"].add_unknown(77, 10); + cc.tiles["CIB_R94C48:CIB_DCUB"].add_unknown(82, 10); + cc.tiles["CIB_R94C48:CIB_DCUB"].add_unknown(83, 10); + cc.tiles["CIB_R94C48:CIB_DCUB"].add_unknown(84, 10); + cc.tiles["CIB_R94C48:CIB_DCUB"].add_unknown(85, 10); + cc.tiles["CIB_R94C49:CIB_DCUC"].add_unknown(20, 10); + cc.tiles["CIB_R94C49:CIB_DCUC"].add_unknown(21, 10); + cc.tiles["CIB_R94C49:CIB_DCUC"].add_unknown(22, 10); + cc.tiles["CIB_R94C49:CIB_DCUC"].add_unknown(23, 10); + cc.tiles["CIB_R94C49:CIB_DCUC"].add_unknown(28, 10); + cc.tiles["CIB_R94C49:CIB_DCUC"].add_unknown(29, 10); + cc.tiles["CIB_R94C49:CIB_DCUC"].add_unknown(30, 10); + cc.tiles["CIB_R94C49:CIB_DCUC"].add_unknown(31, 10); + cc.tiles["CIB_R94C49:CIB_DCUC"].add_unknown(74, 10); + cc.tiles["CIB_R94C49:CIB_DCUC"].add_unknown(75, 10); + cc.tiles["CIB_R94C49:CIB_DCUC"].add_unknown(76, 10); + cc.tiles["CIB_R94C49:CIB_DCUC"].add_unknown(77, 10); + cc.tiles["CIB_R94C49:CIB_DCUC"].add_unknown(82, 10); + cc.tiles["CIB_R94C49:CIB_DCUC"].add_unknown(83, 10); + cc.tiles["CIB_R94C49:CIB_DCUC"].add_unknown(84, 10); + cc.tiles["CIB_R94C49:CIB_DCUC"].add_unknown(85, 10); + cc.tiles["CIB_R94C50:CIB_DCUD"].add_unknown(20, 10); + cc.tiles["CIB_R94C50:CIB_DCUD"].add_unknown(21, 10); + cc.tiles["CIB_R94C50:CIB_DCUD"].add_unknown(22, 10); + cc.tiles["CIB_R94C50:CIB_DCUD"].add_unknown(23, 10); + cc.tiles["CIB_R94C50:CIB_DCUD"].add_unknown(28, 10); + cc.tiles["CIB_R94C50:CIB_DCUD"].add_unknown(29, 10); + cc.tiles["CIB_R94C50:CIB_DCUD"].add_unknown(31, 10); + cc.tiles["CIB_R94C50:CIB_DCUD"].add_unknown(74, 10); + cc.tiles["CIB_R94C50:CIB_DCUD"].add_unknown(75, 10); + cc.tiles["CIB_R94C50:CIB_DCUD"].add_unknown(76, 10); + cc.tiles["CIB_R94C50:CIB_DCUD"].add_unknown(77, 10); + cc.tiles["CIB_R94C50:CIB_DCUD"].add_unknown(82, 10); + cc.tiles["CIB_R94C50:CIB_DCUD"].add_unknown(83, 10); + cc.tiles["CIB_R94C50:CIB_DCUD"].add_unknown(84, 10); + cc.tiles["CIB_R94C50:CIB_DCUD"].add_unknown(85, 10); + cc.tiles["CIB_R94C51:CIB_DCUF"].add_unknown(20, 10); + cc.tiles["CIB_R94C51:CIB_DCUF"].add_unknown(21, 10); + cc.tiles["CIB_R94C51:CIB_DCUF"].add_unknown(22, 10); + cc.tiles["CIB_R94C51:CIB_DCUF"].add_unknown(23, 10); + cc.tiles["CIB_R94C51:CIB_DCUF"].add_unknown(28, 10); + cc.tiles["CIB_R94C51:CIB_DCUF"].add_unknown(29, 10); + cc.tiles["CIB_R94C51:CIB_DCUF"].add_unknown(30, 10); + cc.tiles["CIB_R94C51:CIB_DCUF"].add_unknown(31, 10); + cc.tiles["CIB_R94C51:CIB_DCUF"].add_unknown(74, 10); + cc.tiles["CIB_R94C51:CIB_DCUF"].add_unknown(75, 10); + cc.tiles["CIB_R94C51:CIB_DCUF"].add_unknown(76, 10); + cc.tiles["CIB_R94C51:CIB_DCUF"].add_unknown(77, 10); + cc.tiles["CIB_R94C51:CIB_DCUF"].add_unknown(82, 10); + cc.tiles["CIB_R94C51:CIB_DCUF"].add_unknown(83, 10); + cc.tiles["CIB_R94C51:CIB_DCUF"].add_unknown(84, 10); + cc.tiles["CIB_R94C51:CIB_DCUF"].add_unknown(85, 10); + cc.tiles["CIB_R94C52:CIB_DCU3"].add_unknown(20, 10); + cc.tiles["CIB_R94C52:CIB_DCU3"].add_unknown(22, 10); + cc.tiles["CIB_R94C52:CIB_DCU3"].add_unknown(23, 10); + cc.tiles["CIB_R94C52:CIB_DCU3"].add_unknown(29, 10); + cc.tiles["CIB_R94C52:CIB_DCU3"].add_unknown(31, 10); + cc.tiles["CIB_R94C52:CIB_DCU3"].add_unknown(74, 10); + cc.tiles["CIB_R94C52:CIB_DCU3"].add_unknown(75, 10); + cc.tiles["CIB_R94C52:CIB_DCU3"].add_unknown(76, 10); + cc.tiles["CIB_R94C52:CIB_DCU3"].add_unknown(77, 10); + cc.tiles["CIB_R94C52:CIB_DCU3"].add_unknown(82, 10); + cc.tiles["CIB_R94C52:CIB_DCU3"].add_unknown(83, 10); + cc.tiles["CIB_R94C52:CIB_DCU3"].add_unknown(84, 10); + cc.tiles["CIB_R94C52:CIB_DCU3"].add_unknown(85, 10); + cc.tiles["CIB_R94C53:CIB_DCU2"].add_unknown(20, 10); + cc.tiles["CIB_R94C53:CIB_DCU2"].add_unknown(22, 10); + cc.tiles["CIB_R94C53:CIB_DCU2"].add_unknown(29, 10); + cc.tiles["CIB_R94C53:CIB_DCU2"].add_unknown(31, 10); + cc.tiles["CIB_R94C53:CIB_DCU2"].add_unknown(74, 10); + cc.tiles["CIB_R94C53:CIB_DCU2"].add_unknown(76, 10); + cc.tiles["CIB_R94C53:CIB_DCU2"].add_unknown(83, 10); + cc.tiles["CIB_R94C53:CIB_DCU2"].add_unknown(85, 10); + cc.tiles["CIB_R94C54:CIB_DCUG"].add_unknown(20, 10); + cc.tiles["CIB_R94C54:CIB_DCUG"].add_unknown(22, 10); + cc.tiles["CIB_R94C54:CIB_DCUG"].add_unknown(29, 10); + cc.tiles["CIB_R94C54:CIB_DCUG"].add_unknown(31, 10); + cc.tiles["CIB_R94C54:CIB_DCUG"].add_unknown(74, 10); + cc.tiles["CIB_R94C54:CIB_DCUG"].add_unknown(76, 10); + cc.tiles["CIB_R94C54:CIB_DCUG"].add_unknown(83, 10); + cc.tiles["CIB_R94C54:CIB_DCUG"].add_unknown(85, 10); + cc.tiles["CIB_R94C55:CIB_DCUH"].add_unknown(20, 10); + cc.tiles["CIB_R94C55:CIB_DCUH"].add_unknown(22, 10); + cc.tiles["CIB_R94C55:CIB_DCUH"].add_unknown(29, 10); + cc.tiles["CIB_R94C55:CIB_DCUH"].add_unknown(31, 10); + cc.tiles["CIB_R94C55:CIB_DCUH"].add_unknown(74, 10); + cc.tiles["CIB_R94C55:CIB_DCUH"].add_unknown(76, 10); + cc.tiles["CIB_R94C55:CIB_DCUH"].add_unknown(83, 10); + cc.tiles["CIB_R94C55:CIB_DCUH"].add_unknown(85, 10); + cc.tiles["CIB_R94C56:CIB_DCUI"].add_unknown(20, 10); + cc.tiles["CIB_R94C56:CIB_DCUI"].add_unknown(22, 10); + cc.tiles["CIB_R94C56:CIB_DCUI"].add_unknown(29, 10); + cc.tiles["CIB_R94C56:CIB_DCUI"].add_unknown(31, 10); + cc.tiles["CIB_R94C56:CIB_DCUI"].add_unknown(74, 10); + cc.tiles["CIB_R94C56:CIB_DCUI"].add_unknown(76, 10); + cc.tiles["CIB_R94C56:CIB_DCUI"].add_unknown(83, 10); + cc.tiles["CIB_R94C56:CIB_DCUI"].add_unknown(85, 10); + cc.tiles["CIB_R94C57:CIB_DCU1"].add_unknown(20, 10); + cc.tiles["CIB_R94C57:CIB_DCU1"].add_unknown(22, 10); + cc.tiles["CIB_R94C57:CIB_DCU1"].add_unknown(29, 10); + cc.tiles["CIB_R94C57:CIB_DCU1"].add_unknown(31, 10); + cc.tiles["CIB_R94C57:CIB_DCU1"].add_unknown(74, 10); + cc.tiles["CIB_R94C6:CIB_EFB0"].add_enum("CIB.JB3MUX", "0"); + cc.tiles["CIB_R94C6:CIB_EFB0"].add_enum("CIB.JC6MUX", "0"); + cc.tiles["CIB_R94C6:CIB_EFB0"].add_enum("CIB.JD6MUX", "0"); + cc.tiles["CIB_R94C71:CIB_DCU0"].add_unknown(20, 10); + cc.tiles["CIB_R94C71:CIB_DCU0"].add_unknown(21, 10); + cc.tiles["CIB_R94C71:CIB_DCU0"].add_unknown(22, 10); + cc.tiles["CIB_R94C71:CIB_DCU0"].add_unknown(23, 10); + cc.tiles["CIB_R94C71:CIB_DCU0"].add_unknown(28, 10); + cc.tiles["CIB_R94C71:CIB_DCU0"].add_unknown(29, 10); + cc.tiles["CIB_R94C71:CIB_DCU0"].add_unknown(30, 10); + cc.tiles["CIB_R94C71:CIB_DCU0"].add_unknown(31, 10); + cc.tiles["CIB_R94C71:CIB_DCU0"].add_unknown(74, 10); + cc.tiles["CIB_R94C71:CIB_DCU0"].add_unknown(75, 10); + cc.tiles["CIB_R94C71:CIB_DCU0"].add_unknown(76, 10); + cc.tiles["CIB_R94C71:CIB_DCU0"].add_unknown(77, 10); + cc.tiles["CIB_R94C71:CIB_DCU0"].add_unknown(82, 10); + cc.tiles["CIB_R94C71:CIB_DCU0"].add_unknown(83, 10); + cc.tiles["CIB_R94C71:CIB_DCU0"].add_unknown(84, 10); + cc.tiles["CIB_R94C71:CIB_DCU0"].add_unknown(85, 10); + cc.tiles["CIB_R94C72:CIB_DCUA"].add_unknown(20, 10); + cc.tiles["CIB_R94C72:CIB_DCUA"].add_unknown(21, 10); + cc.tiles["CIB_R94C72:CIB_DCUA"].add_unknown(22, 10); + cc.tiles["CIB_R94C72:CIB_DCUA"].add_unknown(23, 10); + cc.tiles["CIB_R94C72:CIB_DCUA"].add_unknown(28, 10); + cc.tiles["CIB_R94C72:CIB_DCUA"].add_unknown(29, 10); + cc.tiles["CIB_R94C72:CIB_DCUA"].add_unknown(30, 10); + cc.tiles["CIB_R94C72:CIB_DCUA"].add_unknown(31, 10); + cc.tiles["CIB_R94C72:CIB_DCUA"].add_unknown(74, 10); + cc.tiles["CIB_R94C72:CIB_DCUA"].add_unknown(75, 10); + cc.tiles["CIB_R94C72:CIB_DCUA"].add_unknown(76, 10); + cc.tiles["CIB_R94C72:CIB_DCUA"].add_unknown(77, 10); + cc.tiles["CIB_R94C72:CIB_DCUA"].add_unknown(82, 10); + cc.tiles["CIB_R94C72:CIB_DCUA"].add_unknown(83, 10); + cc.tiles["CIB_R94C72:CIB_DCUA"].add_unknown(84, 10); + cc.tiles["CIB_R94C72:CIB_DCUA"].add_unknown(85, 10); + cc.tiles["CIB_R94C73:CIB_DCUB"].add_unknown(20, 10); + cc.tiles["CIB_R94C73:CIB_DCUB"].add_unknown(21, 10); + cc.tiles["CIB_R94C73:CIB_DCUB"].add_unknown(22, 10); + cc.tiles["CIB_R94C73:CIB_DCUB"].add_unknown(23, 10); + cc.tiles["CIB_R94C73:CIB_DCUB"].add_unknown(28, 10); + cc.tiles["CIB_R94C73:CIB_DCUB"].add_unknown(29, 10); + cc.tiles["CIB_R94C73:CIB_DCUB"].add_unknown(30, 10); + cc.tiles["CIB_R94C73:CIB_DCUB"].add_unknown(31, 10); + cc.tiles["CIB_R94C73:CIB_DCUB"].add_unknown(74, 10); + cc.tiles["CIB_R94C73:CIB_DCUB"].add_unknown(75, 10); + cc.tiles["CIB_R94C73:CIB_DCUB"].add_unknown(76, 10); + cc.tiles["CIB_R94C73:CIB_DCUB"].add_unknown(77, 10); + cc.tiles["CIB_R94C73:CIB_DCUB"].add_unknown(82, 10); + cc.tiles["CIB_R94C73:CIB_DCUB"].add_unknown(83, 10); + cc.tiles["CIB_R94C73:CIB_DCUB"].add_unknown(84, 10); + cc.tiles["CIB_R94C73:CIB_DCUB"].add_unknown(85, 10); + cc.tiles["CIB_R94C74:CIB_DCUC"].add_unknown(20, 10); + cc.tiles["CIB_R94C74:CIB_DCUC"].add_unknown(21, 10); + cc.tiles["CIB_R94C74:CIB_DCUC"].add_unknown(22, 10); + cc.tiles["CIB_R94C74:CIB_DCUC"].add_unknown(23, 10); + cc.tiles["CIB_R94C74:CIB_DCUC"].add_unknown(28, 10); + cc.tiles["CIB_R94C74:CIB_DCUC"].add_unknown(29, 10); + cc.tiles["CIB_R94C74:CIB_DCUC"].add_unknown(30, 10); + cc.tiles["CIB_R94C74:CIB_DCUC"].add_unknown(31, 10); + cc.tiles["CIB_R94C74:CIB_DCUC"].add_unknown(74, 10); + cc.tiles["CIB_R94C74:CIB_DCUC"].add_unknown(75, 10); + cc.tiles["CIB_R94C74:CIB_DCUC"].add_unknown(76, 10); + cc.tiles["CIB_R94C74:CIB_DCUC"].add_unknown(77, 10); + cc.tiles["CIB_R94C74:CIB_DCUC"].add_unknown(82, 10); + cc.tiles["CIB_R94C74:CIB_DCUC"].add_unknown(83, 10); + cc.tiles["CIB_R94C74:CIB_DCUC"].add_unknown(84, 10); + cc.tiles["CIB_R94C74:CIB_DCUC"].add_unknown(85, 10); + cc.tiles["CIB_R94C75:CIB_DCUD"].add_unknown(20, 10); + cc.tiles["CIB_R94C75:CIB_DCUD"].add_unknown(21, 10); + cc.tiles["CIB_R94C75:CIB_DCUD"].add_unknown(22, 10); + cc.tiles["CIB_R94C75:CIB_DCUD"].add_unknown(23, 10); + cc.tiles["CIB_R94C75:CIB_DCUD"].add_unknown(28, 10); + cc.tiles["CIB_R94C75:CIB_DCUD"].add_unknown(29, 10); + cc.tiles["CIB_R94C75:CIB_DCUD"].add_unknown(31, 10); + cc.tiles["CIB_R94C75:CIB_DCUD"].add_unknown(74, 10); + cc.tiles["CIB_R94C75:CIB_DCUD"].add_unknown(75, 10); + cc.tiles["CIB_R94C75:CIB_DCUD"].add_unknown(76, 10); + cc.tiles["CIB_R94C75:CIB_DCUD"].add_unknown(77, 10); + cc.tiles["CIB_R94C75:CIB_DCUD"].add_unknown(82, 10); + cc.tiles["CIB_R94C75:CIB_DCUD"].add_unknown(83, 10); + cc.tiles["CIB_R94C75:CIB_DCUD"].add_unknown(84, 10); + cc.tiles["CIB_R94C75:CIB_DCUD"].add_unknown(85, 10); + cc.tiles["CIB_R94C76:CIB_DCUF"].add_unknown(20, 10); + cc.tiles["CIB_R94C76:CIB_DCUF"].add_unknown(21, 10); + cc.tiles["CIB_R94C76:CIB_DCUF"].add_unknown(22, 10); + cc.tiles["CIB_R94C76:CIB_DCUF"].add_unknown(23, 10); + cc.tiles["CIB_R94C76:CIB_DCUF"].add_unknown(28, 10); + cc.tiles["CIB_R94C76:CIB_DCUF"].add_unknown(29, 10); + cc.tiles["CIB_R94C76:CIB_DCUF"].add_unknown(30, 10); + cc.tiles["CIB_R94C76:CIB_DCUF"].add_unknown(31, 10); + cc.tiles["CIB_R94C76:CIB_DCUF"].add_unknown(74, 10); + cc.tiles["CIB_R94C76:CIB_DCUF"].add_unknown(75, 10); + cc.tiles["CIB_R94C76:CIB_DCUF"].add_unknown(76, 10); + cc.tiles["CIB_R94C76:CIB_DCUF"].add_unknown(77, 10); + cc.tiles["CIB_R94C76:CIB_DCUF"].add_unknown(82, 10); + cc.tiles["CIB_R94C76:CIB_DCUF"].add_unknown(83, 10); + cc.tiles["CIB_R94C76:CIB_DCUF"].add_unknown(84, 10); + cc.tiles["CIB_R94C76:CIB_DCUF"].add_unknown(85, 10); + cc.tiles["CIB_R94C77:CIB_DCU3"].add_unknown(20, 10); + cc.tiles["CIB_R94C77:CIB_DCU3"].add_unknown(22, 10); + cc.tiles["CIB_R94C77:CIB_DCU3"].add_unknown(23, 10); + cc.tiles["CIB_R94C77:CIB_DCU3"].add_unknown(29, 10); + cc.tiles["CIB_R94C77:CIB_DCU3"].add_unknown(31, 10); + cc.tiles["CIB_R94C77:CIB_DCU3"].add_unknown(74, 10); + cc.tiles["CIB_R94C77:CIB_DCU3"].add_unknown(75, 10); + cc.tiles["CIB_R94C77:CIB_DCU3"].add_unknown(76, 10); + cc.tiles["CIB_R94C77:CIB_DCU3"].add_unknown(77, 10); + cc.tiles["CIB_R94C77:CIB_DCU3"].add_unknown(82, 10); + cc.tiles["CIB_R94C77:CIB_DCU3"].add_unknown(83, 10); + cc.tiles["CIB_R94C77:CIB_DCU3"].add_unknown(84, 10); + cc.tiles["CIB_R94C77:CIB_DCU3"].add_unknown(85, 10); + cc.tiles["CIB_R94C78:CIB_DCU2"].add_unknown(20, 10); + cc.tiles["CIB_R94C78:CIB_DCU2"].add_unknown(22, 10); + cc.tiles["CIB_R94C78:CIB_DCU2"].add_unknown(29, 10); + cc.tiles["CIB_R94C78:CIB_DCU2"].add_unknown(31, 10); + cc.tiles["CIB_R94C78:CIB_DCU2"].add_unknown(74, 10); + cc.tiles["CIB_R94C78:CIB_DCU2"].add_unknown(76, 10); + cc.tiles["CIB_R94C78:CIB_DCU2"].add_unknown(83, 10); + cc.tiles["CIB_R94C78:CIB_DCU2"].add_unknown(85, 10); + cc.tiles["CIB_R94C79:CIB_DCUG"].add_unknown(20, 10); + cc.tiles["CIB_R94C79:CIB_DCUG"].add_unknown(22, 10); + cc.tiles["CIB_R94C79:CIB_DCUG"].add_unknown(29, 10); + cc.tiles["CIB_R94C79:CIB_DCUG"].add_unknown(31, 10); + cc.tiles["CIB_R94C79:CIB_DCUG"].add_unknown(74, 10); + cc.tiles["CIB_R94C79:CIB_DCUG"].add_unknown(76, 10); + cc.tiles["CIB_R94C79:CIB_DCUG"].add_unknown(83, 10); + cc.tiles["CIB_R94C79:CIB_DCUG"].add_unknown(85, 10); + cc.tiles["CIB_R94C7:CIB_EFB1"].add_enum("CIB.JA3MUX", "0"); + cc.tiles["CIB_R94C7:CIB_EFB1"].add_enum("CIB.JA4MUX", "0"); + cc.tiles["CIB_R94C7:CIB_EFB1"].add_enum("CIB.JA5MUX", "0"); + cc.tiles["CIB_R94C7:CIB_EFB1"].add_enum("CIB.JA6MUX", "0"); + cc.tiles["CIB_R94C7:CIB_EFB1"].add_enum("CIB.JB3MUX", "0"); + cc.tiles["CIB_R94C7:CIB_EFB1"].add_enum("CIB.JB4MUX", "0"); + cc.tiles["CIB_R94C7:CIB_EFB1"].add_enum("CIB.JB5MUX", "0"); + cc.tiles["CIB_R94C7:CIB_EFB1"].add_enum("CIB.JB6MUX", "0"); + cc.tiles["CIB_R94C7:CIB_EFB1"].add_enum("CIB.JC3MUX", "0"); + cc.tiles["CIB_R94C7:CIB_EFB1"].add_enum("CIB.JC4MUX", "0"); + cc.tiles["CIB_R94C7:CIB_EFB1"].add_enum("CIB.JC5MUX", "0"); + cc.tiles["CIB_R94C7:CIB_EFB1"].add_enum("CIB.JD3MUX", "0"); + cc.tiles["CIB_R94C7:CIB_EFB1"].add_enum("CIB.JD4MUX", "0"); + cc.tiles["CIB_R94C7:CIB_EFB1"].add_enum("CIB.JD5MUX", "0"); + cc.tiles["CIB_R94C80:CIB_DCUH"].add_unknown(20, 10); + cc.tiles["CIB_R94C80:CIB_DCUH"].add_unknown(22, 10); + cc.tiles["CIB_R94C80:CIB_DCUH"].add_unknown(29, 10); + cc.tiles["CIB_R94C80:CIB_DCUH"].add_unknown(31, 10); + cc.tiles["CIB_R94C80:CIB_DCUH"].add_unknown(74, 10); + cc.tiles["CIB_R94C80:CIB_DCUH"].add_unknown(76, 10); + cc.tiles["CIB_R94C80:CIB_DCUH"].add_unknown(83, 10); + cc.tiles["CIB_R94C80:CIB_DCUH"].add_unknown(85, 10); + cc.tiles["CIB_R94C81:CIB_DCUI"].add_unknown(20, 10); + cc.tiles["CIB_R94C81:CIB_DCUI"].add_unknown(22, 10); + cc.tiles["CIB_R94C81:CIB_DCUI"].add_unknown(29, 10); + cc.tiles["CIB_R94C81:CIB_DCUI"].add_unknown(31, 10); + cc.tiles["CIB_R94C81:CIB_DCUI"].add_unknown(74, 10); + cc.tiles["CIB_R94C81:CIB_DCUI"].add_unknown(76, 10); + cc.tiles["CIB_R94C81:CIB_DCUI"].add_unknown(83, 10); + cc.tiles["CIB_R94C81:CIB_DCUI"].add_unknown(85, 10); + cc.tiles["CIB_R94C82:CIB_DCU1"].add_unknown(20, 10); + cc.tiles["CIB_R94C82:CIB_DCU1"].add_unknown(22, 10); + cc.tiles["CIB_R94C82:CIB_DCU1"].add_unknown(29, 10); + cc.tiles["CIB_R94C82:CIB_DCU1"].add_unknown(31, 10); + cc.tiles["CIB_R94C82:CIB_DCU1"].add_unknown(74, 10); + cc.tiles["MIB_R22C67:CMUX_UL_0"].add_arc("G_DCS0CLK0", "G_VPFN0000"); + cc.tiles["MIB_R22C68:CMUX_UR_0"].add_arc("G_DCS0CLK1", "G_VPFN0000"); + cc.tiles["MIB_R70C67:CMUX_LL_0"].add_arc("G_DCS1CLK0", "G_VPFN0000"); + cc.tiles["MIB_R70C68:CMUX_LR_0"].add_arc("G_DCS1CLK1", "G_VPFN0000"); + cc.tiles["MIB_R95C101:PICB0"].add_unknown(0, 1); + cc.tiles["MIB_R95C102:PICB1"].add_unknown(0, 1); + cc.tiles["MIB_R95C103:PICB0"].add_unknown(0, 1); + cc.tiles["MIB_R95C104:PICB1"].add_unknown(0, 1); + cc.tiles["MIB_R95C105:PICB0"].add_unknown(0, 1); + cc.tiles["MIB_R95C106:PICB1"].add_unknown(0, 1); + cc.tiles["MIB_R95C107:PICB0"].add_unknown(0, 1); + cc.tiles["MIB_R95C108:PICB1"].add_unknown(0, 1); + cc.tiles["MIB_R95C110:PICB0"].add_unknown(0, 1); + cc.tiles["MIB_R95C111:PICB1"].add_unknown(0, 1); + cc.tiles["MIB_R95C112:PICB0"].add_unknown(0, 1); + cc.tiles["MIB_R95C113:PICB1"].add_unknown(0, 1); + cc.tiles["MIB_R95C114:PICB0"].add_unknown(0, 1); + cc.tiles["MIB_R95C115:PICB1"].add_unknown(0, 1); + cc.tiles["MIB_R95C116:PICB0"].add_unknown(0, 1); + cc.tiles["MIB_R95C117:PICB1"].add_unknown(0, 1); + cc.tiles["MIB_R95C119:PICB0"].add_unknown(0, 1); + cc.tiles["MIB_R95C120:PICB1"].add_unknown(0, 1); + cc.tiles["MIB_R95C121:PICB0"].add_unknown(0, 1); + cc.tiles["MIB_R95C122:PICB1"].add_unknown(0, 1); + cc.tiles["MIB_R95C4:EFB0_PICB0"].add_unknown(54, 1); + cc.tiles["MIB_R95C4:EFB0_PICB0"].add_unknown(56, 1); + cc.tiles["MIB_R95C4:EFB0_PICB0"].add_unknown(82, 1); + cc.tiles["MIB_R95C4:EFB0_PICB0"].add_unknown(94, 1); + cc.tiles["MIB_R95C96:PICB0"].add_unknown(0, 1); + cc.tiles["MIB_R95C97:PICB1"].add_unknown(0, 1); + cc.tiles["MIB_R95C98:PICB0"].add_unknown(0, 1); + cc.tiles["MIB_R95C99:PICB1"].add_unknown(0, 1); +} + +} // namespace BaseConfigs +NEXTPNR_NAMESPACE_END diff --git a/ecp5/bitstream.cc b/ecp5/bitstream.cc index df16946d..a9c82524 100644 --- a/ecp5/bitstream.cc +++ b/ecp5/bitstream.cc @@ -34,6 +34,18 @@ NEXTPNR_NAMESPACE_BEGIN +namespace BaseConfigs { +void config_empty_lfe5u_25f(ChipConfig &cc); +void config_empty_lfe5u_45f(ChipConfig &cc); +void config_empty_lfe5u_85f(ChipConfig &cc); +void config_empty_lfe5um_25f(ChipConfig &cc); +void config_empty_lfe5um_45f(ChipConfig &cc); +void config_empty_lfe5um_85f(ChipConfig &cc); +void config_empty_lfe5um5g_25f(ChipConfig &cc); +void config_empty_lfe5um5g_45f(ChipConfig &cc); +void config_empty_lfe5um5g_85f(ChipConfig &cc); +} // namespace BaseConfigs + // Convert an absolute wire name to a relative Trellis one static std::string get_trellis_wirename(Context *ctx, Location loc, WireId wire) { @@ -538,8 +550,37 @@ void write_bitstream(Context *ctx, std::string base_config_file, std::string tex } config_file >> cc; } else { - cc.chip_name = ctx->getChipName(); - // TODO: .bit metadata + switch (ctx->args.type) { + case ArchArgs::LFE5U_25F: + BaseConfigs::config_empty_lfe5u_25f(cc); + break; + case ArchArgs::LFE5U_45F: + BaseConfigs::config_empty_lfe5u_45f(cc); + break; + case ArchArgs::LFE5U_85F: + BaseConfigs::config_empty_lfe5u_85f(cc); + break; + case ArchArgs::LFE5UM_25F: + BaseConfigs::config_empty_lfe5um_25f(cc); + break; + case ArchArgs::LFE5UM_45F: + BaseConfigs::config_empty_lfe5um_45f(cc); + break; + case ArchArgs::LFE5UM_85F: + BaseConfigs::config_empty_lfe5um_85f(cc); + break; + case ArchArgs::LFE5UM5G_25F: + BaseConfigs::config_empty_lfe5um5g_25f(cc); + break; + case ArchArgs::LFE5UM5G_45F: + BaseConfigs::config_empty_lfe5um5g_45f(cc); + break; + case ArchArgs::LFE5UM5G_85F: + BaseConfigs::config_empty_lfe5um5g_85f(cc); + break; + default: + NPNR_ASSERT_FALSE("Unsupported device type"); + } } // Clear out DCU tieoffs in base config if DCU used @@ -578,7 +619,7 @@ void write_bitstream(Context *ctx, std::string base_config_file, std::string tex } // Find bank voltages std::unordered_map<int, IOVoltage> bankVcc; - std::unordered_map<int, bool> bankLvds; + std::unordered_map<int, bool> bankLvds, bankVref; for (auto &cell : ctx->cells) { CellInfo *ci = cell.second.get(); @@ -587,7 +628,7 @@ void write_bitstream(Context *ctx, std::string base_config_file, std::string tex std::string dir = str_or_default(ci->params, ctx->id("DIR"), "INPUT"); std::string iotype = str_or_default(ci->attrs, ctx->id("IO_TYPE"), "LVCMOS33"); - if (dir != "INPUT") { + if (dir != "INPUT" || is_referenced(ioType_from_str(iotype))) { IOVoltage vcc = get_vccio(ioType_from_str(iotype)); if (bankVcc.find(bank) != bankVcc.end()) { // TODO: strong and weak constraints @@ -603,6 +644,8 @@ void write_bitstream(Context *ctx, std::string base_config_file, std::string tex if (iotype == "LVDS") bankLvds[bank] = true; + if ((dir == "INPUT" || dir == "BIDIR") && is_referenced(ioType_from_str(iotype))) + bankVref[bank] = true; } } @@ -614,17 +657,67 @@ void write_bitstream(Context *ctx, std::string base_config_file, std::string tex std::string type = tile.second; if (type.find("BANKREF") != std::string::npos && type != "BANKREF8") { int bank = std::stoi(type.substr(7)); - if (bankVcc.find(bank) != bankVcc.end()) - cc.tiles[tile.first].add_enum("BANK.VCCIO", iovoltage_to_str(bankVcc[bank])); + if (bankVcc.find(bank) != bankVcc.end()) { + if (bankVcc[bank] == IOVoltage::VCC_1V35) + cc.tiles[tile.first].add_enum("BANK.VCCIO", "1V2"); + else + cc.tiles[tile.first].add_enum("BANK.VCCIO", iovoltage_to_str(bankVcc[bank])); + } if (bankLvds[bank]) { cc.tiles[tile.first].add_enum("BANK.DIFF_REF", "ON"); cc.tiles[tile.first].add_enum("BANK.LVDSO", "ON"); } + if (bankVref[bank]) { + cc.tiles[tile.first].add_enum("BANK.DIFF_REF", "ON"); + cc.tiles[tile.first].add_enum("BANK.VREF", "ON"); + } } } } } + // Create dummy outputs used as Vref input buffer for banks where Vref is used + for (auto bv : bankVref) { + if (!bv.second) + continue; + BelId vrefIO = ctx->getPioByFunctionName(fmt_str("VREF1_" << bv.first)); + if (vrefIO == BelId()) + log_error("unable to find VREF input for bank %d\n", bv.first); + if (!ctx->checkBelAvail(vrefIO)) { + CellInfo *bound = ctx->getBoundBelCell(vrefIO); + if (bound != nullptr) + log_error("VREF pin %s of bank %d is occupied by IO '%s'\n", ctx->getBelPackagePin(vrefIO).c_str(), + bv.first, bound->name.c_str(ctx)); + else + log_error("VREF pin %s of bank %d is unavailable\n", ctx->getBelPackagePin(vrefIO).c_str(), bv.first); + } + log_info("Using pin %s as VREF for bank %d\n", ctx->getBelPackagePin(vrefIO).c_str(), bv.first); + std::string pio_tile = get_pio_tile(ctx, vrefIO); + + std::string iotype; + switch (bankVcc[bv.first]) { + case IOVoltage::VCC_1V2: + iotype = "HSUL12"; + break; + case IOVoltage::VCC_1V35: + iotype = "SSTL18_I"; + break; + case IOVoltage::VCC_1V5: + iotype = "SSTL18_I"; + break; + case IOVoltage::VCC_1V8: + iotype = "SSTL18_I"; + break; + default: + log_error("Referenced inputs are not supported with bank VccIO of %s.\n", + iovoltage_to_str(bankVcc[bv.first]).c_str()); + } + + std::string pio = ctx->locInfo(vrefIO)->bel_data[vrefIO.index].name.get(); + cc.tiles[pio_tile].add_enum(pio + ".BASE_TYPE", "OUTPUT_" + iotype); + cc.tiles[pio_tile].add_enum(pio + ".PULLMODE", "NONE"); + } + // Configure slices for (auto &cell : ctx->cells) { CellInfo *ci = cell.second.get(); @@ -727,9 +820,13 @@ void write_bitstream(Context *ctx, std::string base_config_file, std::string tex // cc.tiles[pic_tile].add_enum(other + ".BASE_TYPE", "_NONE_"); cc.tiles[pio_tile].add_enum(other + ".PULLMODE", "NONE"); cc.tiles[pio_tile].add_enum(pio + ".PULLMODE", "NONE"); + } else if (is_referenced(ioType_from_str(iotype))) { + cc.tiles[pio_tile].add_enum(pio + ".PULLMODE", "NONE"); } if (dir != "INPUT" && - (ci->ports.find(ctx->id("T")) == ci->ports.end() || ci->ports.at(ctx->id("T")).net == nullptr)) { + (ci->ports.find(ctx->id("T")) == ci->ports.end() || ci->ports.at(ctx->id("T")).net == nullptr) && + (ci->ports.find(ctx->id("IOLTO")) == ci->ports.end() || + ci->ports.at(ctx->id("IOLTO")).net == nullptr)) { // Tie tristate low if unconnected for outputs or bidir std::string jpt = fmt_str("X" << bel.location.x << "/Y" << bel.location.y << "/JPADDT" << pio.back()); WireId jpt_wire = ctx->getWireByName(ctx->id(jpt)); @@ -740,11 +837,43 @@ void write_bitstream(Context *ctx, std::string base_config_file, std::string tex std::string cib_wirename = ctx->locInfo(cib_wire)->wire_data[cib_wire.index].name.get(); cc.tiles[cib_tile].add_enum("CIB." + cib_wirename + "MUX", "0"); } - if (dir == "INPUT" && !is_differential(ioType_from_str(iotype))) { + if (dir == "INPUT" && !is_differential(ioType_from_str(iotype)) && + !is_referenced(ioType_from_str(iotype))) { cc.tiles[pio_tile].add_enum(pio + ".HYSTERESIS", "ON"); } - if (ci->attrs.count(ctx->id("SLEWRATE"))) + if (ci->attrs.count(ctx->id("SLEWRATE")) && !is_referenced(ioType_from_str(iotype))) cc.tiles[pio_tile].add_enum(pio + ".SLEWRATE", str_or_default(ci->attrs, ctx->id("SLEWRATE"), "SLOW")); + if (ci->attrs.count(ctx->id("PULLMODE"))) + cc.tiles[pio_tile].add_enum(pio + ".PULLMODE", str_or_default(ci->attrs, ctx->id("PULLMODE"), "NONE")); + if (ci->attrs.count(ctx->id("DIFFRESISTOR"))) + cc.tiles[pio_tile].add_enum(pio + ".DIFFRESISTOR", + str_or_default(ci->attrs, ctx->id("DIFFRESISTOR"), "OFF")); + if (ci->attrs.count(ctx->id("TERMINATION"))) { + auto vccio = get_vccio(ioType_from_str(iotype)); + switch (vccio) { + case IOVoltage::VCC_1V8: + cc.tiles[pio_tile].add_enum(pio + ".TERMINATION_1V8", + str_or_default(ci->attrs, ctx->id("TERMINATION"), "OFF")); + break; + case IOVoltage::VCC_1V5: + cc.tiles[pio_tile].add_enum(pio + ".TERMINATION_1V5", + str_or_default(ci->attrs, ctx->id("TERMINATION"), "OFF")); + break; + case IOVoltage::VCC_1V35: + cc.tiles[pio_tile].add_enum(pio + ".TERMINATION_1V35", + str_or_default(ci->attrs, ctx->id("TERMINATION"), "OFF")); + break; + default: + log_error("TERMINATION is not supported with Vcc = %s (on PIO %s)\n", + iovoltage_to_str(vccio).c_str(), ci->name.c_str(ctx)); + } + } + std::string datamux_oddr = str_or_default(ci->params, ctx->id("DATAMUX_ODDR"), "PADDO"); + if (datamux_oddr != "PADDO") + cc.tiles[pic_tile].add_enum(pio + ".DATAMUX_ODDR", datamux_oddr); + std::string datamux_mddr = str_or_default(ci->params, ctx->id("DATAMUX_MDDR"), "PADDO"); + if (datamux_mddr != "PADDO") + cc.tiles[pic_tile].add_enum(pio + ".DATAMUX_MDDR", datamux_mddr); } else if (ci->type == ctx->id("DCCA")) { // Nothing to do } else if (ci->type == ctx->id("DP16KD")) { @@ -1078,6 +1207,18 @@ void write_bitstream(Context *ctx, std::string base_config_file, std::string tex int_to_bitvector(int_or_default(ci->attrs, ctx->id("MFG_ENABLE_FILTEROPAMP"), 0), 1)); cc.tilegroups.push_back(tg); + } else if (ci->type == id_IOLOGIC || ci->type == id_SIOLOGIC) { + Loc pio_loc = ctx->getBelLocation(ci->bel); + pio_loc.z -= ci->type == id_SIOLOGIC ? 2 : 4; + std::string pic_tile = get_pic_tile(ctx, ctx->getBelByLocation(pio_loc)); + std::string prim = std::string("IOLOGIC") + "ABCD"[pio_loc.z]; + for (auto ¶m : ci->params) { + if (param.first == ctx->id("DELAY.DEL_VALUE")) + cc.tiles[pic_tile].add_word(prim + "." + param.first.str(ctx), + int_to_bitvector(std::stoi(param.second), 7)); + else + cc.tiles[pic_tile].add_enum(prim + "." + param.first.str(ctx), param.second); + } } else if (ci->type == id_DCUA) { TileGroup tg; tg.tiles = get_dcu_tiles(ctx, ci->bel); @@ -1100,6 +1241,85 @@ void write_bitstream(Context *ctx, std::string base_config_file, std::string tex std::string tname = ctx->getTileByTypeAndLocation(loc.y + 1, loc.x, "BMID_0H"); cc.tiles[tname].add_enum("PCSCLKDIV" + std::to_string(loc.z), str_or_default(ci->params, ctx->id("GSR"), "ENABLED")); + } else if (ci->type == id_DTR) { + cc.tiles[ctx->getTileByType("DTR")].add_enum("DTR.MODE", "DTR"); + } else if (ci->type == id_OSCG) { + int div = int_or_default(ci->params, ctx->id("DIV"), 128); + if (div == 128) + div = 127; + cc.tiles[ctx->getTileByType("EFB0_PICB0")].add_enum("OSC.DIV", std::to_string(div)); + cc.tiles[ctx->getTileByType("EFB1_PICB1")].add_enum("OSC.DIV", std::to_string(div)); + cc.tiles[ctx->getTileByType("EFB1_PICB1")].add_enum("OSC.MODE", "OSCG"); + cc.tiles[ctx->getTileByType("EFB1_PICB1")].add_enum("CCLK.MODE", "_NONE_"); + } else if (ci->type == id_USRMCLK) { + cc.tiles[ctx->getTileByType("EFB3_PICB1")].add_enum("CCLK.MODE", "USRMCLK"); + } else if (ci->type == id_GSR) { + cc.tiles[ctx->getTileByType("EFB0_PICB0")].add_enum( + "GSR.GSRMODE", str_or_default(ci->params, ctx->id("MODE"), "ACTIVE_HIGH")); + cc.tiles[ctx->getTileByType("VIQ_BUF")].add_enum("GSR.SYNCMODE", + str_or_default(ci->params, ctx->id("SYNCMODE"), "ASYNC")); + } else if (ci->type == id_JTAGG) { + cc.tiles[ctx->getTileByType("EFB0_PICB0")].add_enum("JTAG.ER1", + str_or_default(ci->params, ctx->id("ER1"), "ENABLED")); + cc.tiles[ctx->getTileByType("EFB0_PICB0")].add_enum("JTAG.ER2", + str_or_default(ci->params, ctx->id("ER2"), "ENABLED")); + } else if (ci->type == id_CLKDIVF) { + Loc loc = ctx->getBelLocation(ci->bel); + bool r = loc.x > 5; + std::string clkdiv = std::string("CLKDIV_") + (r ? "R" : "L") + std::to_string(loc.z); + std::string tile = ctx->getTileByType(std::string("ECLK_") + (r ? "R" : "L")); + cc.tiles[tile].add_enum(clkdiv + ".DIV", str_or_default(ci->params, ctx->id("DIV"), "2.0")); + cc.tiles[tile].add_enum(clkdiv + ".GSR", str_or_default(ci->params, ctx->id("GSR"), "DISABLED")); + } else if (ci->type == id_TRELLIS_ECLKBUF) { + } else if (ci->type == id_DQSBUFM) { + Loc loc = ctx->getBelLocation(ci->bel); + bool l = loc.x < 10; + std::string pic = l ? "PICL" : "PICR"; + TileGroup tg; + tg.tiles.push_back(ctx->getTileByTypeAndLocation(loc.y - 2, loc.x, pic + "1_DQS0")); + tg.tiles.push_back(ctx->getTileByTypeAndLocation(loc.y - 1, loc.x, pic + "2_DQS1")); + tg.tiles.push_back(ctx->getTileByTypeAndLocation(loc.y, loc.x, pic + "0_DQS2")); + tg.tiles.push_back(ctx->getTileByTypeAndLocation(loc.y + 1, loc.x, pic + "1_DQS3")); + tg.config.add_enum("DQS.MODE", "DQSBUFM"); + tg.config.add_enum("DQS.DQS_LI_DEL_ADJ", str_or_default(ci->params, ctx->id("DQS_LI_DEL_ADJ"), "PLUS")); + tg.config.add_enum("DQS.DQS_LO_DEL_ADJ", str_or_default(ci->params, ctx->id("DQS_LO_DEL_ADJ"), "PLUS")); + int li_del_value = int_or_default(ci->params, ctx->id("DQS_LI_DEL_VAL"), 0); + if (str_or_default(ci->params, ctx->id("DQS_LI_DEL_ADJ"), "PLUS") == "MINUS") + li_del_value = (256 - li_del_value) & 0xFF; + int lo_del_value = int_or_default(ci->params, ctx->id("DQS_LO_DEL_VAL"), 0); + if (str_or_default(ci->params, ctx->id("DQS_LO_DEL_ADJ"), "PLUS") == "MINUS") + lo_del_value = (256 - lo_del_value) & 0xFF; + tg.config.add_word("DQS.DQS_LI_DEL_VAL", int_to_bitvector(li_del_value, 8)); + tg.config.add_word("DQS.DQS_LO_DEL_VAL", int_to_bitvector(lo_del_value, 8)); + tg.config.add_enum("DQS.WRLOADN_USED", get_net_or_empty(ci, id_WRLOADN) != nullptr ? "YES" : "NO"); + tg.config.add_enum("DQS.RDLOADN_USED", get_net_or_empty(ci, id_RDLOADN) != nullptr ? "YES" : "NO"); + tg.config.add_enum("DQS.PAUSE_USED", get_net_or_empty(ci, id_PAUSE) != nullptr ? "YES" : "NO"); + tg.config.add_enum("DQS.READ_USED", + (get_net_or_empty(ci, id_READ0) != nullptr || get_net_or_empty(ci, id_READ1) != nullptr) + ? "YES" + : "NO"); + tg.config.add_enum("DQS.DDRDEL", get_net_or_empty(ci, id_DDRDEL) != nullptr ? "DDRDEL" : "0"); + tg.config.add_enum("DQS.GSR", str_or_default(ci->params, ctx->id("GSR"), "DISABLED")); + cc.tilegroups.push_back(tg); + } else if (ci->type == id_ECLKSYNCB) { + Loc loc = ctx->getBelLocation(ci->bel); + bool r = loc.x > 5; + std::string eclksync = ctx->locInfo(bel)->bel_data[bel.index].name.get(); + std::string tile = ctx->getTileByType(std::string("ECLK_") + (r ? "R" : "L")); + if (get_net_or_empty(ci, id_STOP) != nullptr) + cc.tiles[tile].add_enum(eclksync + ".MODE", "ECLKSYNCB"); + } else if (ci->type == id_DDRDLL) { + Loc loc = ctx->getBelLocation(ci->bel); + bool u = loc.y<15, r = loc.x> 15; + std::string tiletype = fmt_str("DDRDLL_" << (u ? 'U' : 'L') << (r ? 'R' : 'L')); + if (ctx->args.type == ArchArgs::LFE5U_25F || ctx->args.type == ArchArgs::LFE5UM_25F || + ctx->args.type == ArchArgs::LFE5UM5G_25F) + tiletype += "A"; + std::string tile = ctx->getTileByType(tiletype); + cc.tiles[tile].add_enum("DDRDLL.MODE", "DDRDLLA"); + cc.tiles[tile].add_enum("DDRDLL.GSR", str_or_default(ci->params, ctx->id("GSR"), "DISABLED")); + cc.tiles[tile].add_enum("DDRDLL.FORCE_MAX_DELAY", + str_or_default(ci->params, ctx->id("FORCE_MAX_DELAY"), "NO")); } else { NPNR_ASSERT_FALSE("unsupported cell type"); } diff --git a/ecp5/cells.cc b/ecp5/cells.cc index 31839ee4..38bcc17c 100644 --- a/ecp5/cells.cc +++ b/ecp5/cells.cc @@ -41,6 +41,22 @@ std::unique_ptr<CellInfo> create_ecp5_cell(Context *ctx, IdString type, std::str new_cell->name = ctx->id(name); } new_cell->type = type; + + auto copy_bel_ports = [&]() { + // First find a Bel of the target type + BelId tgt; + for (auto bel : ctx->getBels()) { + if (ctx->getBelType(bel) == type) { + tgt = bel; + break; + } + } + NPNR_ASSERT(tgt != BelId()); + for (auto port : ctx->getBelPins(tgt)) { + add_port(ctx, new_cell.get(), port.str(ctx), ctx->getBelPinType(tgt, port)); + } + }; + if (type == ctx->id("TRELLIS_SLICE")) { new_cell->params[ctx->id("MODE")] = "LOGIC"; new_cell->params[ctx->id("GSR")] = "DISABLED"; @@ -111,11 +127,17 @@ std::unique_ptr<CellInfo> create_ecp5_cell(Context *ctx, IdString type, std::str } else if (type == ctx->id("TRELLIS_IO")) { new_cell->params[ctx->id("DIR")] = "INPUT"; new_cell->attrs[ctx->id("IO_TYPE")] = "LVCMOS33"; + new_cell->params[ctx->id("DATAMUX_ODDR")] = "PADDO"; + new_cell->params[ctx->id("DATAMUX_MDDR")] = "PADDO"; add_port(ctx, new_cell.get(), "B", PORT_INOUT); add_port(ctx, new_cell.get(), "I", PORT_IN); add_port(ctx, new_cell.get(), "T", PORT_IN); add_port(ctx, new_cell.get(), "O", PORT_OUT); + + add_port(ctx, new_cell.get(), "IOLDO", PORT_IN); + add_port(ctx, new_cell.get(), "IOLTO", PORT_IN); + } else if (type == ctx->id("LUT4")) { new_cell->params[ctx->id("INIT")] = "0"; @@ -150,6 +172,38 @@ std::unique_ptr<CellInfo> create_ecp5_cell(Context *ctx, IdString type, std::str add_port(ctx, new_cell.get(), "CLKI", PORT_IN); add_port(ctx, new_cell.get(), "CLKO", PORT_OUT); add_port(ctx, new_cell.get(), "CE", PORT_IN); + } else if (type == id_IOLOGIC || type == id_SIOLOGIC) { + new_cell->params[ctx->id("MODE")] = "NONE"; + new_cell->params[ctx->id("GSR")] = "DISABLED"; + new_cell->params[ctx->id("CLKIMUX")] = "CLK"; + new_cell->params[ctx->id("CLKOMUX")] = "CLK"; + new_cell->params[ctx->id("LSRIMUX")] = "0"; + new_cell->params[ctx->id("LSROMUX")] = "0"; + new_cell->params[ctx->id("LSRMUX")] = "LSR"; + + new_cell->params[ctx->id("DELAY.OUTDEL")] = "DISABLED"; + new_cell->params[ctx->id("DELAY.DEL_VALUE")] = "0"; + new_cell->params[ctx->id("DELAY.WAIT_FOR_EDGE")] = "DISABLED"; + + if (type == id_IOLOGIC) { + new_cell->params[ctx->id("IDDRXN.MODE")] = "NONE"; + new_cell->params[ctx->id("ODDRXN.MODE")] = "NONE"; + + new_cell->params[ctx->id("MIDDRX.MODE")] = "NONE"; + new_cell->params[ctx->id("MODDRX.MODE")] = "NONE"; + new_cell->params[ctx->id("MTDDRX.MODE")] = "NONE"; + + new_cell->params[ctx->id("IOLTOMUX")] = "NONE"; + new_cell->params[ctx->id("MTDDRX.DQSW_INVERT")] = "DISABLED"; + new_cell->params[ctx->id("MTDDRX.REGSET")] = "RESET"; + + new_cell->params[ctx->id("MIDDRX_MODDRX.WRCLKMUX")] = "NONE"; + } + // Just copy ports from the Bel + copy_bel_ports(); + } else if (type == id_TRELLIS_ECLKBUF) { + add_port(ctx, new_cell.get(), "ECLKI", PORT_IN); + add_port(ctx, new_cell.get(), "ECLKO", PORT_OUT); } else { log_error("unable to create ECP5 cell of type %s", type.c_str(ctx)); } @@ -365,7 +419,7 @@ void nxio_to_tr(Context *ctx, CellInfo *nxio, CellInfo *trio, std::vector<std::u ctx, donet, [](const Context *ctx, const CellInfo *cell) { return cell->type == ctx->id("$_TBUF_"); }, ctx->id("Y")); if (tbuf) { - replace_port(tbuf, ctx->id("I"), trio, ctx->id("I")); + replace_port(tbuf, ctx->id("A"), trio, ctx->id("I")); // Need to invert E to form T std::unique_ptr<CellInfo> inv_lut = create_ecp5_cell(ctx, ctx->id("LUT4"), trio->name.str(ctx) + "$invert_T"); replace_port(tbuf, ctx->id("E"), inv_lut.get(), ctx->id("A")); diff --git a/ecp5/cells.h b/ecp5/cells.h index dcef99e3..e66f8f21 100644 --- a/ecp5/cells.h +++ b/ecp5/cells.h @@ -46,6 +46,17 @@ inline bool is_pfumx(const BaseCtx *ctx, const CellInfo *cell) { return cell->ty inline bool is_l6mux(const BaseCtx *ctx, const CellInfo *cell) { return cell->type == ctx->id("L6MUX21"); } +inline bool is_iologic_input_cell(const BaseCtx *ctx, const CellInfo *cell) +{ + return cell->type == ctx->id("IDDRX1F") || cell->type == ctx->id("IDDRX2F") || cell->type == ctx->id("IDDR71B") || + cell->type == ctx->id("IDDRX2DQA"); +} +inline bool is_iologic_output_cell(const BaseCtx *ctx, const CellInfo *cell) +{ + return cell->type == ctx->id("ODDRX1F") || cell->type == ctx->id("ODDRX2F") || cell->type == ctx->id("ODDR71B") || + cell->type == ctx->id("ODDRX2DQA") || cell->type == ctx->id("ODDRX2DQSB") || cell->type == ctx->id("OSHX2A"); +} + void ff_to_slice(Context *ctx, CellInfo *ff, CellInfo *lc, int index, bool driven_by_lut); void lut_to_slice(Context *ctx, CellInfo *lut, CellInfo *lc, int index); void ccu2c_to_slice(Context *ctx, CellInfo *ccu, CellInfo *lc); diff --git a/ecp5/constids.inc b/ecp5/constids.inc index 250bc3fc..8a3179b6 100644 --- a/ecp5/constids.inc +++ b/ecp5/constids.inc @@ -1115,7 +1115,6 @@ X(SEL2) X(SEL1) X(SEL0) X(CDIV1) -X(CDIVX) X(DP16KD_REGMODE_A_NOREG_REGMODE_B_NOREG) X(DP16KD_REGMODE_A_NOREG_REGMODE_B_OUTREG) @@ -1142,3 +1141,144 @@ X(PAD) X(PADDI) X(PADDO) X(PADDT) + +X(IOLOGIC) +X(SIOLOGIC) +X(DI) +X(IOLDO) +X(IOLDOD) +X(IOLDOI) +X(IOLTO) +X(INDD) +X(LOADN) +X(MOVE) +X(DIRECTION) +X(TSDATA0) +X(TXDATA0) +X(TXDATA1) +X(RXDATA0) +X(RXDATA1) +X(INFF) +X(CFLAG) +X(ECLK) +X(TSDATA1) +X(TXDATA2) +X(TXDATA3) +X(RXDATA2) +X(RXDATA3) +X(TXDATA4) +X(TXDATA5) +X(TXDATA6) +X(RXDATA4) +X(RXDATA5) +X(RXDATA6) +X(DQSR90) +X(DQSW270) +X(DQSW) +X(RDPNTR0) +X(RDPNTR1) +X(RDPNTR2) +X(WRPNTR0) +X(WRPNTR1) +X(WRPNTR2) + +X(GSR) + +X(JTAGG) +X(TCK) +X(TMS) +X(TDI) +X(JTDO2) +X(JTDO1) +X(TDO) +X(JTDI) +X(JTCK) +X(JRTI2) +X(JRTI1) +X(JSHIFT) +X(JUPDATE) +X(JRSTN) +X(JCE2) +X(JCE1) + +X(OSCG) +X(OSC) +X(SEDSTDBY) + +X(SEDGA) +X(SEDENABLE) +X(SEDSTART) +X(SEDFRCERR) +X(SEDDONE) +X(SEDINPROG) +X(SEDERR) + +X(DTR) +X(STARTPULSE) +X(DTROUT0) +X(DTROUT1) +X(DTROUT2) +X(DTROUT3) +X(DTROUT4) +X(DTROUT5) +X(DTROUT6) +X(DTROUT7) + +X(USRMCLK) + +X(CLKDIVF) +X(ALIGNWD) +X(CDIVX) + +X(ECLKSYNCB) +X(ECLKI) +X(STOP) +X(ECLKO) + +X(DLLDELD) +X(A) +X(DDRDEL) +X(Z) + +X(DDRDLL) +X(UDDCNTLN) +X(FREEZE) +X(DIVOSC) +X(DCNTL0) +X(DCNTL1) +X(DCNTL2) +X(DCNTL3) +X(DCNTL4) +X(DCNTL5) +X(DCNTL6) +X(DCNTL7) + +X(DQSBUFM) +X(DQSI) +X(READ1) +X(READ0) +X(READCLKSEL2) +X(READCLKSEL1) +X(READCLKSEL0) +X(DYNDELAY0) +X(DYNDELAY1) +X(DYNDELAY2) +X(DYNDELAY3) +X(DYNDELAY4) +X(DYNDELAY5) +X(DYNDELAY6) +X(DYNDELAY7) +X(PAUSE) +X(RDLOADN) +X(RDMOVE) +X(RDDIRECTION) +X(WRLOADN) +X(WRMOVE) +X(WRDIRECTION) +X(DATAVALID) +X(BURSTDET) +X(RDCFLAG) +X(WRCFLAG) +X(SCLK) + +X(TRELLIS_ECLKBUF)
\ No newline at end of file diff --git a/ecp5/docs/primitives.md b/ecp5/docs/primitives.md new file mode 100644 index 00000000..aa37f3e5 --- /dev/null +++ b/ecp5/docs/primitives.md @@ -0,0 +1,47 @@ +# nextpnr-ecp5 Primitive Support List + +nextpnr-ecp5 currently supports the following primitives: + + - **ALU54B** (limited support, must be manually placed) + - **CCU2C** + - **CLKDIVF** + - **DCUA** + - **DDRDLLA** + - **DELAYF** + - **DELAYG** + - **DP16KD** + - **DQSBUFM** + - **DTR** + - **ECLKSYNCB** + - **EHXPLLL** + - **EXTREFB** + - **GSR** + - **IDDR71B** + - **IDDRX1F** + - **IDDRX2DQA** + - **IDDRX2F** + - **IOLOGIC** + - **JTAGG** (untested) + - **L6MUX21** + - **LUT4** + - **MULT18X18D** (cascade functionality not supported) + - **ODDR71B** + - **ODDRX1F** + - **ODDRX2DQA** + - **ODDRX2DQSB** + - **ODDRX2F** + - **OSCG** + - **OSHX2A** + - **PCSCLKDIV** + - **PFUMX** + - **SEDGA** (untested) + - **SIOLOGIC** + - **TRELLIS_DPR16X4** + - **TRELLIS_ECLKBUF** + - **TRELLIS_FF** + - **TRELLIS_IO** + - **TRELLIS_SLICE** + - **TSHX2DQA** + - **TSHX2DQSA** + - **USRMCLK** (untested) + diff --git a/ecp5/family.cmake b/ecp5/family.cmake index 1aae2bea..ca7dc9e9 100644 --- a/ecp5/family.cmake +++ b/ecp5/family.cmake @@ -1,70 +1,78 @@ +if (NOT EXTERNAL_CHIPDB) + set(devices 25k 45k 85k) -set(devices 25k 45k 85k) - -if (NOT DEFINED TRELLIS_ROOT) - message(FATAL_ERROR "you must define TRELLIS_ROOT using -DTRELLIS_ROOT=/path/to/prjtrellis for ECP5 support") -endif() + if (NOT DEFINED TRELLIS_ROOT) + message(STATUS "TRELLIS_ROOT not defined using -DTRELLIS_ROOT=/path/to/prjtrellis. Default to /usr/local/share/trellis") + set(TRELLIS_ROOT "/usr/local/share/trellis") + endif() + if (NOT DEFINED PYTRELLIS_LIBDIR) + find_library(PYTRELLIS pytrellis.so + PATHS ${TRELLIS_ROOT}/libtrellis + PATH_SUFFIXES trellis + DOC "Location of pytrellis library") -file( GLOB found_pytrellis ${TRELLIS_ROOT}/libtrellis/pytrellis.*) + if ("${PYTRELLIS}" STREQUAL "PYTRELLIS-NOTFOUND") + message(FATAL_ERROR "Failed to locate pytrellis library!") + endif() -if ("${found_pytrellis}" STREQUAL "") - message(FATAL_ERROR "failed to find pytrellis library in ${TRELLIS_ROOT}/libtrellis/") -endif() + get_filename_component(PYTRELLIS_LIBDIR ${PYTRELLIS} DIRECTORY) + endif() -set(DB_PY ${CMAKE_CURRENT_SOURCE_DIR}/ecp5/trellis_import.py) + set(DB_PY ${CMAKE_CURRENT_SOURCE_DIR}/ecp5/trellis_import.py) -file(MAKE_DIRECTORY ecp5/chipdbs/) -add_library(ecp5_chipdb OBJECT ecp5/chipdbs/) -target_compile_definitions(ecp5_chipdb PRIVATE NEXTPNR_NAMESPACE=nextpnr_${family}) -target_include_directories(ecp5_chipdb PRIVATE ${family}/) + file(MAKE_DIRECTORY ecp5/chipdbs/) + add_library(ecp5_chipdb OBJECT ecp5/chipdbs/) + target_compile_definitions(ecp5_chipdb PRIVATE NEXTPNR_NAMESPACE=nextpnr_${family}) + target_include_directories(ecp5_chipdb PRIVATE ${family}/) -if (WIN32) -set(ENV_CMD ${CMAKE_COMMAND} -E env "PYTHONPATH=\"${TRELLIS_ROOT}/libtrellis\;${TRELLIS_ROOT}/util/common\;${TRELLIS_ROOT}/timing/util\"") -else() -set(ENV_CMD ${CMAKE_COMMAND} -E env "PYTHONPATH=${TRELLIS_ROOT}/libtrellis:${TRELLIS_ROOT}/util/common:${TRELLIS_ROOT}/timing/util") -endif() + if (CMAKE_HOST_WIN32) + set(ENV_CMD ${CMAKE_COMMAND} -E env "PYTHONPATH=\"${PYTRELLIS_LIBDIR}\;${TRELLIS_ROOT}/util/common\;${TRELLIS_ROOT}/timing/util\"") + else() + set(ENV_CMD ${CMAKE_COMMAND} -E env "PYTHONPATH=${PYTRELLIS_LIBDIR}\:${TRELLIS_ROOT}/util/common:${TRELLIS_ROOT}/timing/util") + endif() -if (MSVC) - target_sources(ecp5_chipdb PRIVATE ${CMAKE_CURRENT_SOURCE_DIR}/ecp5/resource/embed.cc) - set_source_files_properties(${CMAKE_CURRENT_SOURCE_DIR}/ecp5/resources/chipdb.rc PROPERTIES LANGUAGE RC) - foreach (dev ${devices}) - set(DEV_CC_DB ${CMAKE_CURRENT_SOURCE_DIR}/ecp5/chipdbs/chipdb-${dev}.bin) - set(DEV_CC_BBA_DB ${CMAKE_CURRENT_SOURCE_DIR}/ecp5/chipdbs/chipdb-${dev}.bba) - set(DEV_CONSTIDS_INC ${CMAKE_CURRENT_SOURCE_DIR}/ecp5/constids.inc) - add_custom_command(OUTPUT ${DEV_CC_BBA_DB} - COMMAND ${ENV_CMD} python3 ${DB_PY} -p ${DEV_CONSTIDS_INC} ${dev} > ${DEV_CC_BBA_DB} + if (MSVC) + target_sources(ecp5_chipdb PRIVATE ${CMAKE_CURRENT_SOURCE_DIR}/ecp5/resource/embed.cc) + set_source_files_properties(${CMAKE_CURRENT_SOURCE_DIR}/ecp5/resources/chipdb.rc PROPERTIES LANGUAGE RC) + foreach (dev ${devices}) + set(DEV_CC_DB ${CMAKE_CURRENT_SOURCE_DIR}/ecp5/chipdbs/chipdb-${dev}.bin) + set(DEV_CC_BBA_DB ${CMAKE_CURRENT_SOURCE_DIR}/ecp5/chipdbs/chipdb-${dev}.bba) + set(DEV_CONSTIDS_INC ${CMAKE_CURRENT_SOURCE_DIR}/ecp5/constids.inc) + add_custom_command(OUTPUT ${DEV_CC_BBA_DB} + COMMAND ${ENV_CMD} python3 ${DB_PY} -p ${DEV_CONSTIDS_INC} ${dev} > ${DEV_CC_BBA_DB} DEPENDS ${DB_PY} ) - add_custom_command(OUTPUT ${DEV_CC_DB} + add_custom_command(OUTPUT ${DEV_CC_DB} COMMAND bbasm ${DEV_CC_BBA_DB} ${DEV_CC_DB} DEPENDS bbasm ${DEV_CC_BBA_DB} ) - target_sources(ecp5_chipdb PRIVATE ${DEV_CC_DB}) - set_source_files_properties(${DEV_CC_DB} PROPERTIES HEADER_FILE_ONLY TRUE) - foreach (target ${family_targets}) - target_sources(${target} PRIVATE $<TARGET_OBJECTS:ecp5_chipdb> ${CMAKE_CURRENT_SOURCE_DIR}/ecp5/resource/chipdb.rc) - endforeach (target) - endforeach (dev) -else() - target_compile_options(ecp5_chipdb PRIVATE -g0 -O0 -w) - foreach (dev ${devices}) - set(DEV_CC_DB ${CMAKE_CURRENT_SOURCE_DIR}/ecp5/chipdbs/chipdb-${dev}.cc) - set(DEV_CC_BBA_DB ${CMAKE_CURRENT_SOURCE_DIR}/ecp5/chipdbs/chipdb-${dev}.bba) - set(DEV_CONSTIDS_INC ${CMAKE_CURRENT_SOURCE_DIR}/ecp5/constids.inc) - add_custom_command(OUTPUT ${DEV_CC_BBA_DB} - COMMAND ${ENV_CMD} python3 ${DB_PY} -p ${DEV_CONSTIDS_INC} ${dev} > ${DEV_CC_BBA_DB}.new + target_sources(ecp5_chipdb PRIVATE ${DEV_CC_DB}) + set_source_files_properties(${DEV_CC_DB} PROPERTIES HEADER_FILE_ONLY TRUE) + foreach (target ${family_targets}) + target_sources(${target} PRIVATE $<TARGET_OBJECTS:ecp5_chipdb> ${CMAKE_CURRENT_SOURCE_DIR}/ecp5/resource/chipdb.rc) + endforeach (target) + endforeach (dev) + else() + target_compile_options(ecp5_chipdb PRIVATE -g0 -O0 -w) + foreach (dev ${devices}) + set(DEV_CC_DB ${CMAKE_CURRENT_SOURCE_DIR}/ecp5/chipdbs/chipdb-${dev}.cc) + set(DEV_CC_BBA_DB ${CMAKE_CURRENT_SOURCE_DIR}/ecp5/chipdbs/chipdb-${dev}.bba) + set(DEV_CONSTIDS_INC ${CMAKE_CURRENT_SOURCE_DIR}/ecp5/constids.inc) + add_custom_command(OUTPUT ${DEV_CC_BBA_DB} + COMMAND ${ENV_CMD} python3 ${DB_PY} -p ${DEV_CONSTIDS_INC} ${dev} > ${DEV_CC_BBA_DB}.new COMMAND mv ${DEV_CC_BBA_DB}.new ${DEV_CC_BBA_DB} DEPENDS ${DB_PY} ) - add_custom_command(OUTPUT ${DEV_CC_DB} + add_custom_command(OUTPUT ${DEV_CC_DB} COMMAND bbasm --c ${DEV_CC_BBA_DB} ${DEV_CC_DB}.new COMMAND mv ${DEV_CC_DB}.new ${DEV_CC_DB} DEPENDS bbasm ${DEV_CC_BBA_DB} ) - target_sources(ecp5_chipdb PRIVATE ${DEV_CC_DB}) - foreach (target ${family_targets}) - target_sources(${target} PRIVATE $<TARGET_OBJECTS:ecp5_chipdb>) - endforeach (target) - endforeach (dev) + target_sources(ecp5_chipdb PRIVATE ${DEV_CC_DB}) + foreach (target ${family_targets}) + target_sources(${target} PRIVATE $<TARGET_OBJECTS:ecp5_chipdb>) + endforeach (target) + endforeach (dev) + endif() endif() diff --git a/ecp5/globals.cc b/ecp5/globals.cc index ddaae5e5..fae2c683 100644 --- a/ecp5/globals.cc +++ b/ecp5/globals.cc @@ -58,6 +58,8 @@ class Ecp5GlobalRouter if (user.cell->type == id_DCUA && (user.port == id_CH0_FF_RXI_CLK || user.port == id_CH1_FF_RXI_CLK || user.port == id_CH0_FF_TXI_CLK || user.port == id_CH1_FF_TXI_CLK)) return true; + if ((user.cell->type == id_IOLOGIC || user.cell->type == id_SIOLOGIC) && user.port == id_CLK) + return true; return false; } @@ -446,6 +448,8 @@ class Ecp5GlobalRouter if (i < 8) fab_globals.insert(i); } + std::vector<std::pair<PortRef *, int>> toroute; + std::unordered_map<int, NetInfo *> clocks; for (auto cell : sorted(ctx->cells)) { CellInfo *ci = cell.second; if (ci->type == id_DCCA) { @@ -470,15 +474,18 @@ class Ecp5GlobalRouter NPNR_ASSERT(routed); // WCK must have routing priority - auto sorted_users = clock->users; - std::sort(sorted_users.begin(), sorted_users.end(), [this](const PortRef &a, const PortRef &b) { - return global_route_priority(a) < global_route_priority(b); - }); - for (const auto &user : sorted_users) { - route_logic_tile_global(clock, glbid, user); - } + for (auto &user : clock->users) + toroute.emplace_back(&user, glbid); + clocks[glbid] = clock; } } + std::sort(toroute.begin(), toroute.end(), + [this](const std::pair<PortRef *, int> &a, const std::pair<PortRef *, int> &b) { + return global_route_priority(*a.first) < global_route_priority(*b.first); + }); + for (const auto &user : toroute) { + route_logic_tile_global(clocks.at(user.second), user.second, *user.first); + } } }; void promote_ecp5_globals(Context *ctx) { Ecp5GlobalRouter(ctx).promote_globals(); } diff --git a/ecp5/lpf.cc b/ecp5/lpf.cc index 4bde660e..4ac70fc9 100644 --- a/ecp5/lpf.cc +++ b/ecp5/lpf.cc @@ -17,6 +17,7 @@ * */ +#include <boost/algorithm/string.hpp> #include <sstream> #include "log.h" @@ -25,7 +26,7 @@ NEXTPNR_NAMESPACE_BEGIN bool Arch::applyLPF(std::string filename, std::istream &in) { auto isempty = [](const std::string &str) { - return std::all_of(str.begin(), str.end(), [](char c) { return isblank(c); }); + return std::all_of(str.begin(), str.end(), [](char c) { return isblank(c) || c == '\r' || c == '\n'; }); }; auto strip_quotes = [](const std::string &str) { if (str.at(0) == '"') { @@ -41,7 +42,9 @@ bool Arch::applyLPF(std::string filename, std::istream &in) log_error("failed to open LPF file\n"); std::string line; std::string linebuf; + int lineno = 0; while (std::getline(in, line)) { + ++lineno; size_t cstart = line.find('#'); if (cstart != std::string::npos) line = line.substr(0, cstart); @@ -60,29 +63,63 @@ bool Arch::applyLPF(std::string filename, std::istream &in) words.push_back(tmp); if (words.size() >= 0) { std::string verb = words.at(0); - if (verb == "BLOCK" || verb == "SYSCONFIG" || verb == "FREQUENCY") { - log_warning(" ignoring unsupported LPF command '%s'\n", command.c_str()); + if (verb == "BLOCK" || verb == "SYSCONFIG") { + if (words.size() != 2 || (words.at(1) != "ASYNCPATHS" && words.at(1) != "RESETPATHS")) + log_warning(" ignoring unsupported LPF command '%s' (on line %d)\n", command.c_str(), + lineno); + } else if (verb == "FREQUENCY") { + if (words.size() < 2) + log_error("expected object type after FREQUENCY (on line %d)\n", lineno); + std::string etype = words.at(1); + if (etype == "PORT" || etype == "NET") { + if (words.size() < 4) + log_error("expected frequency value and unit after 'FREQUENCY %s' (on line %d)\n", + etype.c_str(), lineno); + std::string target = strip_quotes(words.at(2)); + float freq = std::stof(words.at(3)); + std::string unit = words.at(4); + boost::algorithm::to_upper(unit); + if (unit == "MHZ") + ; + else if (unit == "KHZ") + freq /= 1.0e3; + else if (unit == "HZ") + freq /= 1.0e6; + else + log_error("unsupported frequency unit '%s' (on line %d)\n", unit.c_str(), lineno); + addClock(id(target), freq); + } else { + log_warning(" ignoring unsupported LPF command '%s %s' (on line %d)\n", command.c_str(), + etype.c_str(), lineno); + } } else if (verb == "LOCATE") { - NPNR_ASSERT(words.at(1) == "COMP"); + if (words.size() < 5) + log_error("expected syntax 'LOCATE COMP <port name> SITE <pin>' (on line %d)\n", lineno); + if (words.at(1) != "COMP") + log_error("expected 'COMP' after 'LOCATE' (on line %d)\n", lineno); std::string cell = strip_quotes(words.at(2)); - NPNR_ASSERT(words.at(3) == "SITE"); + if (words.at(3) != "SITE") + log_error("expected 'SITE' after 'LOCATE COMP %s' (on line %d)\n", cell.c_str(), lineno); auto fnd_cell = cells.find(id(cell)); - if (fnd_cell == cells.end()) { - log_warning("unmatched LPF 'LOCATE COMP' '%s'\n", cell.c_str()); - } else { + if (fnd_cell != cells.end()) { fnd_cell->second->attrs[id("LOC")] = strip_quotes(words.at(4)); } } else if (verb == "IOBUF") { - NPNR_ASSERT(words.at(1) == "PORT"); + if (words.size() < 3) + log_error("expected syntax 'IOBUF PORT <port name> <attr>=<value>...' (on line %d)\n", + lineno); + if (words.at(1) != "PORT") + log_error("expected 'PORT' after 'IOBUF' (on line %d)\n", lineno); std::string cell = strip_quotes(words.at(2)); auto fnd_cell = cells.find(id(cell)); - if (fnd_cell == cells.end()) { - log_warning("unmatched LPF 'IOBUF PORT' '%s'\n", cell.c_str()); - } else { + if (fnd_cell != cells.end()) { for (size_t i = 3; i < words.size(); i++) { std::string setting = words.at(i); size_t eqpos = setting.find('='); - NPNR_ASSERT(eqpos != std::string::npos); + if (eqpos == std::string::npos) + log_error( + "expected syntax 'IOBUF PORT <port name> <attr>=<value>...' (on line %d)\n", + lineno); std::string key = setting.substr(0, eqpos), value = setting.substr(eqpos + 1); fnd_cell->second->attrs[id(key)] = value; } diff --git a/ecp5/main.cc b/ecp5/main.cc index 12afb09d..bb18aa58 100644 --- a/ecp5/main.cc +++ b/ecp5/main.cc @@ -25,6 +25,7 @@ #include "design_utils.h" #include "log.h" #include "timing.h" +#include "util.h" USING_NEXTPNR_NAMESPACE @@ -61,10 +62,14 @@ po::options_description ECP5CommandHandler::getArchOptions() specific.add_options()("package", po::value<std::string>(), "select device package (defaults to CABGA381)"); specific.add_options()("speed", po::value<int>(), "select device speedgrade (6, 7 or 8)"); - specific.add_options()("basecfg", po::value<std::string>(), "base chip configuration in Trellis text format"); + specific.add_options()("basecfg", po::value<std::string>(), + "base chip configuration in Trellis text format (deprecated)"); + specific.add_options()("override-basecfg", po::value<std::string>(), + "base chip configuration in Trellis text format"); specific.add_options()("textcfg", po::value<std::string>(), "textual configuration in Trellis format to write"); specific.add_options()("lpf", po::value<std::vector<std::string>>(), "LPF pin constraint file(s)"); + specific.add_options()("lpf-allow-unconstrained", "don't require LPF file(s) to constrain all IO"); return specific; } @@ -77,8 +82,14 @@ void ECP5CommandHandler::validate() void ECP5CommandHandler::customBitstream(Context *ctx) { std::string basecfg; - if (vm.count("basecfg")) + if (vm.count("basecfg")) { + log_warning("--basecfg is deprecated.\nIf you are using a default baseconfig (from prjtrellis/misc/basecfgs), " + "these are now embedded in nextpnr - please remove --basecfg.\nIf you are using a non-standard " + "baseconfig in a special application, switch to using --override-basecfg.\n"); basecfg = vm["basecfg"].as<std::string>(); + } else if (vm.count("override-basecfg")) { + basecfg = vm["basecfg"].as<std::string>(); + } std::string textcfg; if (vm.count("textcfg")) @@ -138,8 +149,8 @@ std::unique_ptr<Context> ECP5CommandHandler::createContext() chipArgs.speed = ArchArgs::SPEED_6; } } - - return std::unique_ptr<Context>(new Context(chipArgs)); + auto ctx = std::unique_ptr<Context>(new Context(chipArgs)); + return ctx; } void ECP5CommandHandler::customAfterLoad(Context *ctx) @@ -148,7 +159,26 @@ void ECP5CommandHandler::customAfterLoad(Context *ctx) std::vector<std::string> files = vm["lpf"].as<std::vector<std::string>>(); for (const auto &filename : files) { std::ifstream in(filename); - ctx->applyLPF(filename, in); + if (!in) + log_error("failed to open LPF file '%s'\n", filename.c_str()); + if (!ctx->applyLPF(filename, in)) + log_error("failed to parse LPF file '%s'\n", filename.c_str()); + } + + for (auto cell : sorted(ctx->cells)) { + CellInfo *ci = cell.second; + if (ci->type == ctx->id("$nextpnr_ibuf") || ci->type == ctx->id("$nextpnr_obuf") || + ci->type == ctx->id("$nextpnr_iobuf")) { + if (!ci->attrs.count(ctx->id("LOC"))) { + if (vm.count("lpf-allow-unconstrained")) + log_warning("IO '%s' is unconstrained in LPF and will be automatically placed\n", + cell.first.c_str(ctx)); + else + log_error("IO '%s' is unconstrained in LPF (override this error with " + "--lpf-allow-unconstrained)\n", + cell.first.c_str(ctx)); + } + } } } } diff --git a/ecp5/pack.cc b/ecp5/pack.cc index ca329530..7f00de1f 100644 --- a/ecp5/pack.cc +++ b/ecp5/pack.cc @@ -20,12 +20,14 @@ #include <algorithm> #include <boost/optional.hpp> #include <iterator> +#include <queue> #include <unordered_set> #include "cells.h" #include "chain_utils.h" #include "design_utils.h" #include "globals.h" #include "log.h" +#include "timing.h" #include "util.h" NEXTPNR_NAMESPACE_BEGIN @@ -163,6 +165,7 @@ class Ecp5Packer CellInfo *ci = cell.second; if (is_lut(ctx, ci) && procdLuts.find(cell.first) == procdLuts.end()) { NetInfo *znet = ci->ports.at(ctx->id("Z")).net; + std::vector<NetInfo *> inpnets; if (znet != nullptr) { for (auto user : znet->users) { if (is_lut(ctx, user.cell) && user.cell != ci && @@ -227,12 +230,67 @@ class Ecp5Packer } } } + + // Pack LUTs feeding the same CCU2, RAM or DFF into a SLICE + if (znet != nullptr && znet->users.size() < 10) { + for (auto user : znet->users) { + if (is_lc(ctx, user.cell) || user.cell->type == ctx->id("DP16KD") || is_ff(ctx, user.cell)) { + for (auto port : user.cell->ports) { + if (port.second.type != PORT_IN || port.second.net == nullptr || + port.second.net == znet) + continue; + if (port.second.net->users.size() > 10) + continue; + CellInfo *drv = port.second.net->driver.cell; + if (drv == nullptr) + continue; + if (is_lut(ctx, drv) && !procdLuts.count(drv->name) && + can_pack_lutff(ci->name, drv->name)) { + procdLuts.insert(ci->name); + procdLuts.insert(drv->name); + lutPairs[ci->name] = drv->name; + goto paired_inlut; + } + } + } + } + } + + // Pack LUTs sharing an input with a simple fanout-based heuristic + for (const char *inp : {"A", "B", "C", "D"}) { + NetInfo *innet = ci->ports.at(ctx->id(inp)).net; + if (innet != nullptr && innet->users.size() < 5 && innet->users.size() > 1) + inpnets.push_back(innet); + } + std::sort(inpnets.begin(), inpnets.end(), + [&](const NetInfo *a, const NetInfo *b) { return a->users.size() < b->users.size(); }); + for (auto inet : inpnets) { + for (auto &user : inet->users) { + if (user.cell == nullptr || user.cell == ci || !is_lut(ctx, user.cell)) + continue; + if (procdLuts.count(user.cell->name)) + continue; + if (can_pack_lutff(ci->name, user.cell->name)) { + procdLuts.insert(ci->name); + procdLuts.insert(user.cell->name); + lutPairs[ci->name] = user.cell->name; + goto paired_inlut; + } + } + } + if (false) { paired_inlut: continue; } } } + if (ctx->debug) { + log_info("Singleton LUTs (packer QoR debug): \n"); + for (auto cell : sorted(ctx->cells)) + if (is_lut(ctx, cell.second) && !procdLuts.count(cell.first)) + log_info(" %s\n", cell.first.c_str(ctx)); + } } // Return true if an port is a top level port that provides its own IOBUF @@ -299,7 +357,16 @@ class Ecp5Packer // iobuf log_info("%s feeds TRELLIS_IO %s, removing %s %s.\n", ci->name.c_str(ctx), trio->name.c_str(ctx), ci->type.c_str(ctx), ci->name.c_str(ctx)); + NetInfo *net = trio->ports.at(ctx->id("B")).net; + if (((ci->type == ctx->id("$nextpnr_ibuf") || ci->type == ctx->id("$nextpnr_iobuf")) && + net->users.size() > 1) || + (ci->type == ctx->id("$nextpnr_obuf") && + (net->users.size() > 2 || net->driver.cell != nullptr)) || + (ci->type == ctx->id("$nextpnr_iobuf") && ci->ports.at(ctx->id("I")).net != nullptr && + ci->ports.at(ctx->id("I")).net->driver.cell != nullptr)) + log_error("Pin B of %s '%s' connected to more than a single top level IO.\n", + trio->type.c_str(ctx), trio->name.c_str(ctx)); if (net != nullptr) { ctx->nets.erase(net->name); trio->ports.at(ctx->id("B")).net = nullptr; @@ -930,11 +997,11 @@ class Ecp5Packer if (is_lut(ctx, ci)) { std::unique_ptr<CellInfo> slice = create_ecp5_cell(ctx, ctx->id("TRELLIS_SLICE"), ci->name.str(ctx) + "_SLICE"); - lut_to_slice(ctx, ci, slice.get(), 0); + lut_to_slice(ctx, ci, slice.get(), 1); auto ff = lutffPairs.find(ci->name); if (ff != lutffPairs.end()) { - ff_to_slice(ctx, ctx->cells.at(ff->second).get(), slice.get(), 0, true); + ff_to_slice(ctx, ctx->cells.at(ff->second).get(), slice.get(), 1, true); packed_cells.insert(ff->second); fflutPairs.erase(ff->second); lutffPairs.erase(ci->name); @@ -1323,6 +1390,19 @@ class Ecp5Packer } } + // Miscellaneous packer tasks + void pack_misc() + { + for (auto cell : sorted(ctx->cells)) { + CellInfo *ci = cell.second; + if (ci->type == id_USRMCLK) { + rename_port(ctx, ci, ctx->id("USRMCLKI"), id_PADDO); + rename_port(ctx, ci, ctx->id("USRMCLKTS"), id_PADDT); + rename_port(ctx, ci, ctx->id("USRMCLKO"), id_PADDI); + } + } + } + // Preplace PLL void preplace_plls() { @@ -1377,13 +1457,934 @@ class Ecp5Packer } } + // Check if two nets have identical constant drivers + bool equal_constant(NetInfo *a, NetInfo *b) + { + if (a->driver.cell == nullptr || b->driver.cell == nullptr) + return (a->driver.cell == nullptr && b->driver.cell == nullptr); + if (a->driver.cell->type != ctx->id("GND") && a->driver.cell->type != ctx->id("VCC")) + return false; + return a->driver.cell->type == b->driver.cell->type; + } + + struct EdgeClockInfo + { + CellInfo *buffer = nullptr; + NetInfo *unbuf = nullptr; + NetInfo *buf = nullptr; + }; + + std::map<std::pair<int, int>, EdgeClockInfo> eclks; + + void make_eclk(PortInfo &usr_port, CellInfo *usr_cell, BelId usr_bel, int bank) + { + NetInfo *ecknet = usr_port.net; + if (ecknet == nullptr) + log_error("Input '%s' of cell '%s' cannot be disconnected\n", usr_port.name.c_str(ctx), + usr_cell->name.c_str(ctx)); + int found_eclk = -1, free_eclk = -1; + for (int i = 0; i < 2; i++) { + if (eclks.count(std::make_pair(bank, i))) { + if (eclks.at(std::make_pair(bank, i)).unbuf == ecknet) { + found_eclk = i; + break; + } + } else if (free_eclk == -1) { + free_eclk = i; + } + } + if (found_eclk == -1) { + if (free_eclk == -1) { + log_error("Unable to promote edge clock '%s' for bank %d. 2/2 edge clocks already used by '%s' and " + "'%s'.\n", + ecknet->name.c_str(ctx), bank, eclks.at(std::make_pair(bank, 0)).unbuf->name.c_str(ctx), + eclks.at(std::make_pair(bank, 1)).unbuf->name.c_str(ctx)); + } else { + log_info("Promoted '%s' to bank %d ECLK%d.\n", ecknet->name.c_str(ctx), bank, free_eclk); + auto &eclk = eclks[std::make_pair(bank, free_eclk)]; + eclk.unbuf = ecknet; + IdString eckname = ctx->id(ecknet->name.str(ctx) + "$eclk" + std::to_string(bank) + "_" + + std::to_string(free_eclk)); + + std::unique_ptr<NetInfo> promoted_ecknet(new NetInfo); + promoted_ecknet->name = eckname; + promoted_ecknet->is_global = true; // Prevents router etc touching this special net + eclk.buf = promoted_ecknet.get(); + NPNR_ASSERT(!ctx->nets.count(eckname)); + ctx->nets[eckname] = std::move(promoted_ecknet); + + // Insert TRELLIS_ECLKBUF to isolate edge clock from general routing + std::unique_ptr<CellInfo> eclkbuf = + create_ecp5_cell(ctx, id_TRELLIS_ECLKBUF, eckname.str(ctx) + "$buffer"); + BelId target_bel; + // Find the correct Bel for the ECLKBUF + IdString eclkname = ctx->id("G_BANK" + std::to_string(bank) + "ECLK" + std::to_string(free_eclk)); + for (auto bel : ctx->getBels()) { + if (ctx->getBelType(bel) != id_TRELLIS_ECLKBUF) + continue; + if (ctx->getWireBasename(ctx->getBelPinWire(bel, id_ECLKO)) != eclkname) + continue; + target_bel = bel; + break; + } + NPNR_ASSERT(target_bel != BelId()); + + eclkbuf->attrs[ctx->id("BEL")] = ctx->getBelName(target_bel).str(ctx); + + connect_port(ctx, ecknet, eclkbuf.get(), id_ECLKI); + connect_port(ctx, eclk.buf, eclkbuf.get(), id_ECLKO); + found_eclk = free_eclk; + eclk.buffer = eclkbuf.get(); + new_cells.push_back(std::move(eclkbuf)); + } + } + + auto &eclk = eclks[std::make_pair(bank, found_eclk)]; + disconnect_port(ctx, usr_cell, usr_port.name); + usr_port.net = nullptr; + connect_port(ctx, eclk.buf, usr_cell, usr_port.name); + + // Simple ECLK router + WireId userWire = ctx->getBelPinWire(usr_bel, usr_port.name); + IdString bnke_name = ctx->id("BNK_ECLK" + std::to_string(found_eclk)); + IdString global_name = ctx->id("G_BANK" + std::to_string(bank) + "ECLK" + std::to_string(found_eclk)); + + std::queue<WireId> upstream; + std::unordered_map<WireId, PipId> backtrace; + upstream.push(userWire); + WireId next; + while (true) { + if (upstream.empty() || upstream.size() > 30000) + log_error("failed to route bank %d ECLK%d to %s.%s\n", bank, found_eclk, + ctx->getBelName(usr_bel).c_str(ctx), usr_port.name.c_str(ctx)); + next = upstream.front(); + upstream.pop(); + if (ctx->debug) + log_info(" visited %s\n", ctx->getWireName(next).c_str(ctx)); + IdString basename = ctx->getWireBasename(next); + if (basename == bnke_name || basename == global_name) { + break; + } + if (ctx->checkWireAvail(next)) { + for (auto pip : ctx->getPipsUphill(next)) { + WireId src = ctx->getPipSrcWire(pip); + backtrace[src] = pip; + upstream.push(src); + } + } + } + // Set all the pips we found along the way + WireId cursor = next; + while (true) { + auto fnd = backtrace.find(cursor); + if (fnd == backtrace.end()) + break; + ctx->bindPip(fnd->second, eclk.buf, STRENGTH_LOCKED); + cursor = ctx->getPipDstWire(fnd->second); + } + } + + void tie_zero(CellInfo *ci, IdString port) + { + + if (!ci->ports.count(port)) { + ci->ports[port].name = port; + ci->ports[port].type = PORT_IN; + } + + std::unique_ptr<CellInfo> zero_cell{new CellInfo}; + std::unique_ptr<NetInfo> zero_net{new NetInfo}; + IdString name = ctx->id(ci->name.str(ctx) + "$zero$" + port.str(ctx)); + zero_cell->type = ctx->id("GND"); + zero_cell->name = name; + zero_net->name = name; + zero_cell->ports[ctx->id("GND")].type = PORT_OUT; + connect_port(ctx, zero_net.get(), zero_cell.get(), ctx->id("GND")); + connect_port(ctx, zero_net.get(), ci, port); + ctx->nets[name] = std::move(zero_net); + new_cells.push_back(std::move(zero_cell)); + } + + std::unordered_map<IdString, std::pair<bool, int>> dqsbuf_dqsg; + // Pack DQSBUFs + void pack_dqsbuf() + { + for (auto cell : sorted(ctx->cells)) { + CellInfo *ci = cell.second; + if (ci->type == id_DQSBUFM) { + CellInfo *pio = net_driven_by(ctx, ci->ports.at(ctx->id("DQSI")).net, is_trellis_io, id_O); + if (pio == nullptr || ci->ports.at(ctx->id("DQSI")).net->users.size() > 1) + log_error("DQSBUFM '%s' DQSI input must be connected only to a top level input\n", + ci->name.c_str(ctx)); + if (!pio->attrs.count(ctx->id("BEL"))) + log_error("DQSBUFM can only be used with a pin-constrained PIO connected to its DQSI input" + "(while processing '%s').\n", + ci->name.c_str(ctx)); + BelId pio_bel = ctx->getBelByName(ctx->id(pio->attrs.at(ctx->id("BEL")))); + NPNR_ASSERT(pio_bel != BelId()); + Loc pio_loc = ctx->getBelLocation(pio_bel); + if (pio_loc.z != 0) + log_error("PIO '%s' does not appear to be a DQS site (expecting an 'A' pin).\n", + ctx->getBelName(pio_bel).c_str(ctx)); + pio_loc.z = 8; + BelId dqsbuf = ctx->getBelByLocation(pio_loc); + if (dqsbuf == BelId() || ctx->getBelType(dqsbuf) != id_DQSBUFM) + log_error("PIO '%s' does not appear to be a DQS site (didn't find a DQSBUFM).\n", + ctx->getBelName(pio_bel).c_str(ctx)); + ci->attrs[ctx->id("BEL")] = ctx->getBelName(dqsbuf).str(ctx); + bool got_dqsg = ctx->getPIODQSGroup(pio_bel, dqsbuf_dqsg[ci->name].first, dqsbuf_dqsg[ci->name].second); + NPNR_ASSERT(got_dqsg); + log_info("Constrained DQSBUFM '%s' to %cDQS%d\n", ci->name.c_str(ctx), + dqsbuf_dqsg[ci->name].first ? 'R' : 'L', dqsbuf_dqsg[ci->name].second); + + // Set all special ports, if used as 'globals' that the router won't touch + for (auto port : {id_DQSR90, id_RDPNTR0, id_RDPNTR1, id_RDPNTR2, id_WRPNTR0, id_WRPNTR1, id_WRPNTR2, + id_DQSW270, id_DQSW}) { + if (!ci->ports.count(port)) + continue; + NetInfo *pn = ci->ports.at(port).net; + if (pn == nullptr) + continue; + for (auto &usr : pn->users) { + if (usr.port != port || + (usr.cell->type != ctx->id("ODDRX2DQA") && usr.cell->type != ctx->id("ODDRX2DQSB") && + usr.cell->type != ctx->id("TSHX2DQSA") && usr.cell->type != ctx->id("IDDRX2DQA") && + usr.cell->type != ctx->id("TSHX2DQA") && usr.cell->type != id_IOLOGIC)) + log_error("Port '%s' of DQSBUFM '%s' cannot drive port '%s' of cell '%s'.\n", + port.c_str(ctx), ci->name.c_str(ctx), usr.port.c_str(ctx), + usr.cell->name.c_str(ctx)); + } + pn->is_global = true; + } + + for (auto zport : + {id_RDMOVE, id_RDDIRECTION, id_WRMOVE, id_WRDIRECTION, id_READ0, id_READ1, id_READCLKSEL0, + id_READCLKSEL1, id_READCLKSEL2, id_DYNDELAY0, id_DYNDELAY1, id_DYNDELAY2, id_DYNDELAY3, + id_DYNDELAY4, id_DYNDELAY5, id_DYNDELAY6, id_DYNDELAY7}) { + if (net_or_nullptr(ci, zport) == nullptr) + tie_zero(ci, zport); + } + } + } + } + + int lookup_delay(const std::string &del_mode) + { + if (del_mode == "USER_DEFINED") + return 0; + else if (del_mode == "DQS_ALIGNED_X2") + return 6; + else if (del_mode == "DQS_CMD_CLK") + return 9; + else if (del_mode == "ECLK_ALIGNED") + return 21; + else if (del_mode == "ECLK_CENTERED") + return 11; + else if (del_mode == "ECLKBRIDGE_ALIGNED") + return 39; + else if (del_mode == "ECLKBRIDGE_CENTERED") + return 29; + else if (del_mode == "SCLK_ALIGNED") + return 50; + else if (del_mode == "SCLK_CENTERED") + return 39; + else if (del_mode == "SCLK_ZEROHOLD") + return 59; + else + log_error("Unsupported DEL_MODE '%s'\n", del_mode.c_str()); + } + + // Pack IOLOGIC + void pack_iologic() + { + std::unordered_map<IdString, CellInfo *> pio_iologic; + + auto set_iologic_sclk = [&](CellInfo *iol, CellInfo *prim, IdString port, bool input) { + NetInfo *sclk = nullptr; + if (prim->ports.count(port)) + sclk = prim->ports[port].net; + if (sclk == nullptr) { + iol->params[input ? ctx->id("CLKIMUX") : ctx->id("CLKOMUX")] = "0"; + } else { + iol->params[input ? ctx->id("CLKIMUX") : ctx->id("CLKOMUX")] = "CLK"; + if (iol->ports[id_CLK].net != nullptr) { + if (iol->ports[id_CLK].net != sclk && !equal_constant(iol->ports[id_CLK].net, sclk)) + log_error("IOLOGIC '%s' has conflicting clocks '%s' and '%s'\n", iol->name.c_str(ctx), + iol->ports[id_CLK].net->name.c_str(ctx), sclk->name.c_str(ctx)); + } else { + connect_port(ctx, sclk, iol, id_CLK); + } + } + if (prim->ports.count(port)) + disconnect_port(ctx, prim, port); + }; + + auto set_iologic_eclk = [&](CellInfo *iol, CellInfo *prim, IdString port) { + NetInfo *eclk = nullptr; + if (prim->ports.count(port)) + eclk = prim->ports[port].net; + if (eclk == nullptr) + log_error("%s '%s' cannot have disconnected ECLK", prim->type.c_str(ctx), prim->name.c_str(ctx)); + + if (iol->ports[id_ECLK].net != nullptr) { + if (iol->ports[id_ECLK].net != eclk) + log_error("IOLOGIC '%s' has conflicting ECLKs '%s' and '%s'\n", iol->name.c_str(ctx), + iol->ports[id_ECLK].net->name.c_str(ctx), eclk->name.c_str(ctx)); + } else { + connect_port(ctx, eclk, iol, id_ECLK); + } + if (prim->ports.count(port)) + disconnect_port(ctx, prim, port); + }; + + auto set_iologic_lsr = [&](CellInfo *iol, CellInfo *prim, IdString port, bool input) { + NetInfo *lsr = nullptr; + if (prim->ports.count(port)) + lsr = prim->ports[port].net; + if (lsr == nullptr) { + iol->params[input ? ctx->id("LSRIMUX") : ctx->id("LSROMUX")] = "0"; + } else { + iol->params[input ? ctx->id("LSRIMUX") : ctx->id("LSROMUX")] = "LSRMUX"; + if (iol->ports[id_LSR].net != nullptr && !equal_constant(iol->ports[id_LSR].net, lsr)) { + if (iol->ports[id_LSR].net != lsr) + log_error("IOLOGIC '%s' has conflicting LSR signals '%s' and '%s'\n", iol->name.c_str(ctx), + iol->ports[id_LSR].net->name.c_str(ctx), lsr->name.c_str(ctx)); + } else if (iol->ports[id_LSR].net == nullptr) { + connect_port(ctx, lsr, iol, id_LSR); + } + } + if (prim->ports.count(port)) + disconnect_port(ctx, prim, port); + }; + + auto set_iologic_mode = [&](CellInfo *iol, std::string mode) { + auto &curr_mode = iol->params[ctx->id("MODE")]; + if (curr_mode != "NONE" && curr_mode != "IREG_OREG" && curr_mode != mode) + log_error("IOLOGIC '%s' has conflicting modes '%s' and '%s'\n", iol->name.c_str(ctx), curr_mode.c_str(), + mode.c_str()); + if (iol->type == id_SIOLOGIC && mode != "IREG_OREG" && mode != "IDDRX1_ODDRX1" && mode != "NONE") + log_error("IOLOGIC '%s' is set to mode '%s', but this is only supported for left and right IO\n", + iol->name.c_str(ctx), mode.c_str()); + curr_mode = mode; + }; + + auto get_pio_bel = [&](CellInfo *pio, CellInfo *curr) { + if (!pio->attrs.count(ctx->id("BEL"))) + log_error("IOLOGIC functionality (DDR, DELAY, DQS, etc) can only be used with pin-constrained PIO " + "(while processing '%s').\n", + curr->name.c_str(ctx)); + BelId bel = ctx->getBelByName(ctx->id(pio->attrs.at(ctx->id("BEL")))); + NPNR_ASSERT(bel != BelId()); + return bel; + }; + + auto create_pio_iologic = [&](CellInfo *pio, CellInfo *curr) { + BelId bel = get_pio_bel(pio, curr); + log_info("IOLOGIC component %s connected to PIO Bel %s\n", curr->name.c_str(ctx), + ctx->getBelName(bel).c_str(ctx)); + Loc loc = ctx->getBelLocation(bel); + bool s = false; + if (loc.y == 0 || loc.y == (ctx->chip_info->height - 1)) + s = true; + std::unique_ptr<CellInfo> iol = + create_ecp5_cell(ctx, s ? id_SIOLOGIC : id_IOLOGIC, pio->name.str(ctx) + "$IOL"); + + loc.z += s ? 2 : 4; + iol->attrs[ctx->id("BEL")] = ctx->getBelName(ctx->getBelByLocation(loc)).str(ctx); + + CellInfo *iol_ptr = iol.get(); + pio_iologic[pio->name] = iol_ptr; + new_cells.push_back(std::move(iol)); + return iol_ptr; + }; + + auto process_dqs_port = [&](CellInfo *prim, CellInfo *pio, CellInfo *iol, IdString port) { + NetInfo *sig = nullptr; + if (prim->ports.count(port)) + sig = prim->ports[port].net; + if (sig == nullptr || sig->driver.cell == nullptr) + log_error("Port %s of cell '%s' cannot be disconnected, it must be driven by a DQSBUFM\n", + port.c_str(ctx), prim->name.c_str(ctx)); + if (iol->ports.at(port).net != nullptr) { + if (iol->ports.at(port).net != sig) { + log_error("IOLOGIC '%s' has conflicting %s signals '%s' and '%s'\n", iol->name.c_str(ctx), + port.c_str(ctx), iol->ports[port].net->name.c_str(ctx), sig->name.c_str(ctx)); + } + disconnect_port(ctx, prim, port); + } else { + bool dqsr; + int dqsgroup; + bool has_dqs = ctx->getPIODQSGroup(get_pio_bel(pio, prim), dqsr, dqsgroup); + if (!has_dqs) + log_error("Primitive '%s' cannot be connected to top level port '%s' as the associated pin is not " + "in any DQS group", + prim->name.c_str(ctx), pio->name.c_str(ctx)); + if (sig->driver.cell->type != id_DQSBUFM || sig->driver.port != port) + log_error("Port %s of cell '%s' must be driven by port %s of a DQSBUFM", port.c_str(ctx), + prim->name.c_str(ctx), port.c_str(ctx)); + auto &driver_group = dqsbuf_dqsg.at(sig->driver.cell->name); + if (driver_group.first != dqsr || driver_group.second != dqsgroup) + log_error("DQS group mismatch, port %s of '%s' in group %cDQ%d is driven by DQSBUFM '%s' in group " + "%cDQ%d\n", + port.c_str(ctx), prim->name.c_str(ctx), dqsr ? 'R' : 'L', dqsgroup, + sig->driver.cell->name.c_str(ctx), driver_group.first ? 'R' : 'L', driver_group.second); + replace_port(prim, port, iol, port); + } + }; + + for (auto cell : sorted(ctx->cells)) { + CellInfo *ci = cell.second; + if (ci->type == ctx->id("DELAYF") || ci->type == ctx->id("DELAYG")) { + CellInfo *i_pio = net_driven_by(ctx, ci->ports.at(ctx->id("A")).net, is_trellis_io, id_O); + CellInfo *o_pio = net_only_drives(ctx, ci->ports.at(ctx->id("Z")).net, is_trellis_io, id_I, true); + CellInfo *iol = nullptr; + if (i_pio != nullptr && ci->ports.at(ctx->id("A")).net->users.size() == 1) { + iol = create_pio_iologic(i_pio, ci); + set_iologic_mode(iol, "IREG_OREG"); + bool drives_iologic = false; + for (auto user : ci->ports.at(ctx->id("Z")).net->users) + if (is_iologic_input_cell(ctx, user.cell) && user.port == ctx->id("D")) + drives_iologic = true; + if (drives_iologic) { + // Reconnect to PIO which the packer expects later on + NetInfo *input_net = ci->ports.at(ctx->id("A")).net, *dly_net = ci->ports.at(ctx->id("Z")).net; + disconnect_port(ctx, i_pio, id_O); + i_pio->ports.at(id_O).net = nullptr; + disconnect_port(ctx, ci, id_A); + ci->ports.at(id_A).net = nullptr; + disconnect_port(ctx, ci, id_Z); + ci->ports.at(id_Z).net = nullptr; + connect_port(ctx, dly_net, i_pio, id_O); + connect_port(ctx, input_net, iol, id_INDD); + connect_port(ctx, input_net, iol, id_DI); + } else { + replace_port(ci, id_A, iol, id_PADDI); + replace_port(ci, id_Z, iol, id_INDD); + } + packed_cells.insert(cell.first); + } else if (o_pio != nullptr) { + iol = create_pio_iologic(o_pio, ci); + iol->params[ctx->id("DELAY.OUTDEL")] = "ENABLED"; + bool driven_by_iol = false; + NetInfo *input_net = ci->ports.at(ctx->id("A")).net, *dly_net = ci->ports.at(ctx->id("Z")).net; + if (input_net->driver.cell != nullptr && is_iologic_output_cell(ctx, input_net->driver.cell) && + input_net->driver.port == ctx->id("Q")) + driven_by_iol = true; + if (driven_by_iol) { + disconnect_port(ctx, o_pio, id_I); + o_pio->ports.at(id_I).net = nullptr; + disconnect_port(ctx, ci, id_A); + ci->ports.at(id_A).net = nullptr; + disconnect_port(ctx, ci, id_Z); + ci->ports.at(id_Z).net = nullptr; + connect_port(ctx, input_net, o_pio, id_I); + ctx->nets.erase(dly_net->name); + } else { + replace_port(ci, ctx->id("A"), iol, id_TXDATA0); + replace_port(ci, ctx->id("Z"), iol, id_IOLDO); + if (!o_pio->ports.count(id_IOLDO)) { + o_pio->ports[id_IOLDO].name = id_IOLDO; + o_pio->ports[id_IOLDO].type = PORT_IN; + } + replace_port(o_pio, id_I, o_pio, id_IOLDO); + } + packed_cells.insert(cell.first); + } else { + log_error("%s '%s' must be connected directly to top level input or output\n", ci->type.c_str(ctx), + ci->name.c_str(ctx)); + } + iol->params[ctx->id("DELAY.DEL_VALUE")] = + std::to_string(lookup_delay(str_or_default(ci->params, ctx->id("DEL_MODE"), "USER_DEFINED"))); + if (ci->params.count(ctx->id("DEL_VALUE")) && + ci->params.at(ctx->id("DEL_VALUE")).substr(0, 5) != "DELAY") + iol->params[ctx->id("DELAY.DEL_VALUE")] = ci->params.at(ctx->id("DEL_VALUE")); + if (ci->ports.count(id_LOADN)) + replace_port(ci, id_LOADN, iol, id_LOADN); + else + tie_zero(ci, id_LOADN); + if (ci->ports.count(id_MOVE)) + replace_port(ci, id_MOVE, iol, id_MOVE); + else + tie_zero(ci, id_MOVE); + if (ci->ports.count(id_DIRECTION)) + replace_port(ci, id_DIRECTION, iol, id_DIRECTION); + else + tie_zero(ci, id_DIRECTION); + if (ci->ports.count(id_CFLAG)) + replace_port(ci, id_CFLAG, iol, id_CFLAG); + } + } + + for (auto cell : sorted(ctx->cells)) { + CellInfo *ci = cell.second; + if (ci->type == ctx->id("IDDRX1F")) { + CellInfo *pio = net_driven_by(ctx, ci->ports.at(ctx->id("D")).net, is_trellis_io, id_O); + if (pio == nullptr || ci->ports.at(ctx->id("D")).net->users.size() > 1) + log_error("IDDRX1F '%s' D input must be connected only to a top level input\n", + ci->name.c_str(ctx)); + CellInfo *iol; + if (pio_iologic.count(pio->name)) + iol = pio_iologic.at(pio->name); + else + iol = create_pio_iologic(pio, ci); + set_iologic_mode(iol, "IDDRX1_ODDRX1"); + replace_port(ci, ctx->id("D"), iol, id_PADDI); + set_iologic_sclk(iol, ci, ctx->id("SCLK"), true); + set_iologic_lsr(iol, ci, ctx->id("RST"), true); + replace_port(ci, ctx->id("Q0"), iol, id_RXDATA0); + replace_port(ci, ctx->id("Q1"), iol, id_RXDATA1); + iol->params[ctx->id("GSR")] = str_or_default(ci->params, ctx->id("GSR"), "DISABLED"); + packed_cells.insert(cell.first); + } else if (ci->type == ctx->id("ODDRX1F")) { + CellInfo *pio = net_only_drives(ctx, ci->ports.at(ctx->id("Q")).net, is_trellis_io, id_I, true); + if (pio == nullptr) + log_error("ODDRX1F '%s' Q output must be connected only to a top level output\n", + ci->name.c_str(ctx)); + CellInfo *iol; + if (pio_iologic.count(pio->name)) + iol = pio_iologic.at(pio->name); + else + iol = create_pio_iologic(pio, ci); + set_iologic_mode(iol, "IDDRX1_ODDRX1"); + replace_port(ci, ctx->id("Q"), iol, id_IOLDO); + if (!pio->ports.count(id_IOLDO)) { + pio->ports[id_IOLDO].name = id_IOLDO; + pio->ports[id_IOLDO].type = PORT_IN; + } + replace_port(pio, id_I, pio, id_IOLDO); + pio->params[ctx->id("DATAMUX_ODDR")] = "IOLDO"; + set_iologic_sclk(iol, ci, ctx->id("SCLK"), false); + set_iologic_lsr(iol, ci, ctx->id("RST"), false); + replace_port(ci, ctx->id("D0"), iol, id_TXDATA0); + replace_port(ci, ctx->id("D1"), iol, id_TXDATA1); + iol->params[ctx->id("GSR")] = str_or_default(ci->params, ctx->id("GSR"), "DISABLED"); + packed_cells.insert(cell.first); + } else if (ci->type == ctx->id("ODDRX2F")) { + CellInfo *pio = net_only_drives(ctx, ci->ports.at(ctx->id("Q")).net, is_trellis_io, id_I, true); + if (pio == nullptr) + log_error("ODDRX2F '%s' Q output must be connected only to a top level output\n", + ci->name.c_str(ctx)); + CellInfo *iol; + if (pio_iologic.count(pio->name)) + iol = pio_iologic.at(pio->name); + else + iol = create_pio_iologic(pio, ci); + set_iologic_mode(iol, "ODDRXN"); + replace_port(ci, ctx->id("Q"), iol, id_IOLDO); + if (!pio->ports.count(id_IOLDO)) { + pio->ports[id_IOLDO].name = id_IOLDO; + pio->ports[id_IOLDO].type = PORT_IN; + } + replace_port(pio, id_I, pio, id_IOLDO); + set_iologic_sclk(iol, ci, ctx->id("SCLK"), false); + set_iologic_sclk(iol, ci, ctx->id("SCLK"), true); + set_iologic_eclk(iol, ci, id_ECLK); + set_iologic_lsr(iol, ci, ctx->id("RST"), false); + set_iologic_lsr(iol, ci, ctx->id("RST"), true); + replace_port(ci, ctx->id("D0"), iol, id_TXDATA0); + replace_port(ci, ctx->id("D1"), iol, id_TXDATA1); + replace_port(ci, ctx->id("D2"), iol, id_TXDATA2); + replace_port(ci, ctx->id("D3"), iol, id_TXDATA3); + iol->params[ctx->id("GSR")] = str_or_default(ci->params, ctx->id("GSR"), "DISABLED"); + iol->params[ctx->id("ODDRXN.MODE")] = "ODDRX2"; + pio->params[ctx->id("DATAMUX_ODDR")] = "IOLDO"; + packed_cells.insert(cell.first); + } else if (ci->type == ctx->id("IDDRX2F")) { + CellInfo *pio = net_driven_by(ctx, ci->ports.at(ctx->id("D")).net, is_trellis_io, id_O); + if (pio == nullptr || ci->ports.at(ctx->id("D")).net->users.size() > 1) + log_error("IDDRX2F '%s' D input must be connected only to a top level input\n", + ci->name.c_str(ctx)); + CellInfo *iol; + if (pio_iologic.count(pio->name)) + iol = pio_iologic.at(pio->name); + else + iol = create_pio_iologic(pio, ci); + set_iologic_mode(iol, "IDDRXN"); + replace_port(ci, ctx->id("D"), iol, id_PADDI); + set_iologic_sclk(iol, ci, ctx->id("SCLK"), true); + set_iologic_eclk(iol, ci, id_ECLK); + set_iologic_lsr(iol, ci, ctx->id("RST"), true); + replace_port(ci, ctx->id("Q0"), iol, id_RXDATA0); + replace_port(ci, ctx->id("Q1"), iol, id_RXDATA1); + replace_port(ci, ctx->id("Q2"), iol, id_RXDATA2); + replace_port(ci, ctx->id("Q3"), iol, id_RXDATA3); + iol->params[ctx->id("GSR")] = str_or_default(ci->params, ctx->id("GSR"), "DISABLED"); + iol->params[ctx->id("IDDRXN.MODE")] = "IDDRX2"; + packed_cells.insert(cell.first); + } else if (ci->type == ctx->id("OSHX2A")) { + CellInfo *pio = net_only_drives(ctx, ci->ports.at(ctx->id("Q")).net, is_trellis_io, id_I, true); + if (pio == nullptr) + log_error("OSHX2A '%s' Q output must be connected only to a top level output\n", + ci->name.c_str(ctx)); + CellInfo *iol; + if (pio_iologic.count(pio->name)) + iol = pio_iologic.at(pio->name); + else + iol = create_pio_iologic(pio, ci); + set_iologic_mode(iol, "MIDDRX_MODDRX"); + replace_port(ci, ctx->id("Q"), iol, id_IOLDO); + if (!pio->ports.count(id_IOLDO)) { + pio->ports[id_IOLDO].name = id_IOLDO; + pio->ports[id_IOLDO].type = PORT_IN; + } + replace_port(pio, id_I, pio, id_IOLDO); + set_iologic_sclk(iol, ci, ctx->id("SCLK"), false); + set_iologic_eclk(iol, ci, id_ECLK); + set_iologic_lsr(iol, ci, ctx->id("RST"), false); + set_iologic_lsr(iol, ci, ctx->id("RST"), true); + replace_port(ci, ctx->id("D0"), iol, id_TXDATA0); + replace_port(ci, ctx->id("D1"), iol, id_TXDATA2); + iol->params[ctx->id("GSR")] = str_or_default(ci->params, ctx->id("GSR"), "DISABLED"); + iol->params[ctx->id("MODDRX.MODE")] = "MOSHX2"; + pio->params[ctx->id("DATAMUX_MDDR")] = "IOLDO"; + packed_cells.insert(cell.first); + } else if (ci->type == ctx->id("ODDRX2DQA") || ci->type == ctx->id("ODDRX2DQSB")) { + CellInfo *pio = net_only_drives(ctx, ci->ports.at(ctx->id("Q")).net, is_trellis_io, id_I, true); + if (pio == nullptr) + log_error("%s '%s' Q output must be connected only to a top level output\n", ci->type.c_str(ctx), + ci->name.c_str(ctx)); + CellInfo *iol; + if (pio_iologic.count(pio->name)) + iol = pio_iologic.at(pio->name); + else + iol = create_pio_iologic(pio, ci); + set_iologic_mode(iol, "MIDDRX_MODDRX"); + replace_port(ci, ctx->id("Q"), iol, id_IOLDO); + if (!pio->ports.count(id_IOLDO)) { + pio->ports[id_IOLDO].name = id_IOLDO; + pio->ports[id_IOLDO].type = PORT_IN; + } + replace_port(pio, id_I, pio, id_IOLDO); + set_iologic_sclk(iol, ci, ctx->id("SCLK"), false); + set_iologic_eclk(iol, ci, id_ECLK); + set_iologic_lsr(iol, ci, ctx->id("RST"), false); + set_iologic_lsr(iol, ci, ctx->id("RST"), true); + replace_port(ci, ctx->id("D0"), iol, id_TXDATA0); + replace_port(ci, ctx->id("D1"), iol, id_TXDATA1); + replace_port(ci, ctx->id("D2"), iol, id_TXDATA2); + replace_port(ci, ctx->id("D3"), iol, id_TXDATA3); + iol->params[ctx->id("GSR")] = str_or_default(ci->params, ctx->id("GSR"), "DISABLED"); + iol->params[ctx->id("MODDRX.MODE")] = "MODDRX2"; + iol->params[ctx->id("MIDDRX_MODDRX.WRCLKMUX")] = ci->type == ctx->id("ODDRX2DQSB") ? "DQSW" : "DQSW270"; + process_dqs_port(ci, pio, iol, ci->type == ctx->id("ODDRX2DQSB") ? id_DQSW : id_DQSW270); + pio->params[ctx->id("DATAMUX_MDDR")] = "IOLDO"; + packed_cells.insert(cell.first); + } else if (ci->type == ctx->id("IDDRX2DQA")) { + CellInfo *pio = net_driven_by(ctx, ci->ports.at(ctx->id("D")).net, is_trellis_io, id_O); + if (pio == nullptr || ci->ports.at(ctx->id("D")).net->users.size() > 1) + log_error("IDDRX2DQA '%s' D input must be connected only to a top level input\n", + ci->name.c_str(ctx)); + CellInfo *iol; + if (pio_iologic.count(pio->name)) + iol = pio_iologic.at(pio->name); + else + iol = create_pio_iologic(pio, ci); + set_iologic_mode(iol, "MIDDRX_MODDRX"); + replace_port(ci, ctx->id("D"), iol, id_PADDI); + set_iologic_sclk(iol, ci, ctx->id("SCLK"), true); + set_iologic_eclk(iol, ci, id_ECLK); + set_iologic_lsr(iol, ci, ctx->id("RST"), true); + replace_port(ci, ctx->id("Q0"), iol, id_RXDATA0); + replace_port(ci, ctx->id("Q1"), iol, id_RXDATA1); + replace_port(ci, ctx->id("Q2"), iol, id_RXDATA2); + replace_port(ci, ctx->id("Q3"), iol, id_RXDATA3); + replace_port(ci, ctx->id("QWL"), iol, id_INFF); + iol->params[ctx->id("GSR")] = str_or_default(ci->params, ctx->id("GSR"), "DISABLED"); + iol->params[ctx->id("MIDDRX.MODE")] = "MIDDRX2"; + process_dqs_port(ci, pio, iol, id_DQSR90); + process_dqs_port(ci, pio, iol, id_RDPNTR2); + process_dqs_port(ci, pio, iol, id_RDPNTR1); + process_dqs_port(ci, pio, iol, id_RDPNTR0); + process_dqs_port(ci, pio, iol, id_WRPNTR2); + process_dqs_port(ci, pio, iol, id_WRPNTR1); + process_dqs_port(ci, pio, iol, id_WRPNTR0); + packed_cells.insert(cell.first); + } else if (ci->type == ctx->id("TSHX2DQA") || ci->type == ctx->id("TSHX2DQSA")) { + CellInfo *pio = net_only_drives(ctx, ci->ports.at(ctx->id("Q")).net, is_trellis_io, id_T, true); + if (pio == nullptr) + log_error("%s '%s' Q output must be connected only to a top level tristate\n", ci->type.c_str(ctx), + ci->name.c_str(ctx)); + CellInfo *iol; + if (pio_iologic.count(pio->name)) + iol = pio_iologic.at(pio->name); + else + iol = create_pio_iologic(pio, ci); + set_iologic_mode(iol, "MIDDRX_MODDRX"); + replace_port(ci, ctx->id("Q"), iol, id_IOLTO); + if (!pio->ports.count(id_IOLTO)) { + pio->ports[id_IOLTO].name = id_IOLTO; + pio->ports[id_IOLTO].type = PORT_IN; + } + replace_port(pio, id_T, pio, id_IOLTO); + set_iologic_sclk(iol, ci, ctx->id("SCLK"), false); + set_iologic_eclk(iol, ci, id_ECLK); + set_iologic_lsr(iol, ci, ctx->id("RST"), false); + replace_port(ci, ctx->id("T0"), iol, id_TSDATA0); + replace_port(ci, ctx->id("T1"), iol, id_TSDATA1); + process_dqs_port(ci, pio, iol, ci->type == ctx->id("TSHX2DQSA") ? id_DQSW : id_DQSW270); + iol->params[ctx->id("GSR")] = str_or_default(ci->params, ctx->id("GSR"), "DISABLED"); + iol->params[ctx->id("MTDDRX.MODE")] = "MTSHX2"; + iol->params[ctx->id("MTDDRX.REGSET")] = "SET"; + iol->params[ctx->id("MTDDRX.DQSW_INVERT")] = ci->type == ctx->id("TSHX2DQSA") ? "ENABLED" : "DISABLED"; + iol->params[ctx->id("MIDDRX_MODDRX.WRCLKMUX")] = ci->type == ctx->id("TSHX2DQSA") ? "DQSW" : "DQSW270"; + iol->params[ctx->id("IOLTOMUX")] = "TDDR"; + packed_cells.insert(cell.first); + } + } + flush_cells(); + // Promote/route edge clocks + for (auto cell : sorted(ctx->cells)) { + CellInfo *ci = cell.second; + if (ci->type == id_IOLOGIC || ci->type == id_DQSBUFM) { + if (!ci->ports.count(id_ECLK) || ci->ports.at(id_ECLK).net == nullptr) + continue; + BelId bel = ctx->getBelByName(ctx->id(str_or_default(ci->attrs, ctx->id("BEL")))); + NPNR_ASSERT(bel != BelId()); + Loc pioLoc = ctx->getBelLocation(bel); + if (ci->type == id_DQSBUFM) + pioLoc.z -= 8; + else + pioLoc.z -= 4; + BelId pioBel = ctx->getBelByLocation(pioLoc); + NPNR_ASSERT(pioBel != BelId()); + int bank = ctx->getPioBelBank(pioBel); + make_eclk(ci->ports.at(id_ECLK), ci, bel, bank); + } + } + flush_cells(); + // Constrain ECLK-related cells + for (auto cell : sorted(ctx->cells)) { + CellInfo *ci = cell.second; + if (ci->type == id_CLKDIVF) { + const NetInfo *clki = net_or_nullptr(ci, id_CLKI); + for (auto &eclk : eclks) { + if (eclk.second.unbuf == clki) { + for (auto bel : ctx->getBels()) { + if (ctx->getBelType(bel) != id_CLKDIVF) + continue; + Loc loc = ctx->getBelLocation(bel); + // CLKDIVF for bank 6/7 on the left; for bank 2/3 on the right + if (loc.x < 10 && eclk.first.first != 6 && eclk.first.first != 7) + continue; + // z-index of CLKDIVF must match index of ECLK + if (loc.z != eclk.first.second) + continue; + ci->attrs[ctx->id("BEL")] = ctx->getBelName(bel).str(ctx); + make_eclk(ci->ports.at(id_CLKI), ci, bel, eclk.first.first); + goto clkdiv_done; + } + } + } + clkdiv_done: + continue; + } else if (ci->type == id_ECLKSYNCB) { + const NetInfo *eclko = net_or_nullptr(ci, id_ECLKO); + if (eclko == nullptr) + log_error("ECLKSYNCB '%s' has disconnected port ECLKO\n", ci->name.c_str(ctx)); + for (auto user : eclko->users) { + if (user.cell->type == id_TRELLIS_ECLKBUF) { + Loc eckbuf_loc = + ctx->getBelLocation(ctx->getBelByName(ctx->id(user.cell->attrs.at(ctx->id("BEL"))))); + for (auto bel : ctx->getBels()) { + if (ctx->getBelType(bel) != id_ECLKSYNCB) + continue; + Loc loc = ctx->getBelLocation(bel); + if (loc.x == eckbuf_loc.x && loc.y == eckbuf_loc.y && loc.z == eckbuf_loc.z - 2) { + ci->attrs[ctx->id("BEL")] = ctx->getBelName(bel).str(ctx); + goto eclksync_done; + } + } + } + } + eclksync_done: + continue; + } else if (ci->type == ctx->id("DDRDLLA")) { + ci->type = id_DDRDLL; // transform from Verilog to Bel name + const NetInfo *clk = net_or_nullptr(ci, id_CLK); + if (clk == nullptr) + log_error("DDRDLLA '%s' has disconnected port CLK\n", ci->name.c_str(ctx)); + for (auto &eclk : eclks) { + if (eclk.second.unbuf == clk) { + for (auto bel : ctx->getBels()) { + if (ctx->getBelType(bel) != id_DDRDLL) + continue; + Loc loc = ctx->getBelLocation(bel); + int ddrdll_bank = -1; + if (loc.x < 15 && loc.y < 15) + ddrdll_bank = 7; + else if (loc.x < 15 && loc.y > 15) + ddrdll_bank = 6; + else if (loc.x > 15 && loc.y < 15) + ddrdll_bank = 2; + else if (loc.x > 15 && loc.y > 15) + ddrdll_bank = 3; + if (eclk.first.first != ddrdll_bank) + continue; + ci->attrs[ctx->id("BEL")] = ctx->getBelName(bel).str(ctx); + make_eclk(ci->ports.at(id_CLK), ci, bel, eclk.first.first); + goto ddrdll_done; + } + } + } + ddrdll_done: + continue; + } + } + + flush_cells(); + }; + + void generate_constraints() + { + log_info("Generating derived timing constraints...\n"); + auto MHz = [&](delay_t a) { return 1000.0 / ctx->getDelayNS(a); }; + + auto equals_epsilon = [](delay_t a, delay_t b) { return (std::abs(a - b) / std::max(double(b), 1.0)) < 1e-3; }; + + std::unordered_set<IdString> user_constrained, changed_nets; + for (auto &net : ctx->nets) { + if (net.second->clkconstr != nullptr) + user_constrained.insert(net.first); + changed_nets.insert(net.first); + } + auto get_period = [&](CellInfo *ci, IdString port, delay_t &period) { + if (!ci->ports.count(port)) + return false; + NetInfo *from = ci->ports.at(port).net; + if (from == nullptr || from->clkconstr == nullptr) + return false; + period = from->clkconstr->period.min_delay; + return true; + }; + + auto set_period = [&](CellInfo *ci, IdString port, delay_t period) { + if (!ci->ports.count(port)) + return; + NetInfo *to = ci->ports.at(port).net; + if (to == nullptr) + return; + if (to->clkconstr != nullptr) { + if (!equals_epsilon(to->clkconstr->period.min_delay, period) && user_constrained.count(to->name)) + log_warning( + " Overriding derived constraint of %.1f MHz on net %s with user-specified constraint of " + "%.1f MHz.\n", + MHz(to->clkconstr->period.min_delay), to->name.c_str(ctx), MHz(period)); + return; + } + to->clkconstr = std::unique_ptr<ClockConstraint>(new ClockConstraint()); + to->clkconstr->low.min_delay = period / 2; + to->clkconstr->low.max_delay = period / 2; + to->clkconstr->high.min_delay = period / 2; + to->clkconstr->high.max_delay = period / 2; + to->clkconstr->period.min_delay = period; + to->clkconstr->period.max_delay = period; + log_info(" Derived frequency constraint of %.1f MHz for net %s\n", MHz(to->clkconstr->period.min_delay), + to->name.c_str(ctx)); + changed_nets.insert(to->name); + }; + + auto copy_constraint = [&](CellInfo *ci, IdString fromPort, IdString toPort, double ratio = 1.0) { + if (!ci->ports.count(fromPort) || !ci->ports.count(toPort)) + return; + NetInfo *from = ci->ports.at(fromPort).net, *to = ci->ports.at(toPort).net; + if (from == nullptr || from->clkconstr == nullptr || to == nullptr) + return; + if (to->clkconstr != nullptr) { + if (!equals_epsilon(to->clkconstr->period.min_delay, + delay_t(from->clkconstr->period.min_delay / ratio)) && + user_constrained.count(to->name)) + log_warning( + " Overriding derived constraint of %.1f MHz on net %s with user-specified constraint of " + "%.1f MHz.\n", + MHz(to->clkconstr->period.min_delay), to->name.c_str(ctx), + MHz(delay_t(from->clkconstr->period.min_delay / ratio))); + return; + } + to->clkconstr = std::unique_ptr<ClockConstraint>(new ClockConstraint()); + to->clkconstr->low = ctx->getDelayFromNS(ctx->getDelayNS(from->clkconstr->low.min_delay) / ratio); + to->clkconstr->high = ctx->getDelayFromNS(ctx->getDelayNS(from->clkconstr->high.min_delay) / ratio); + to->clkconstr->period = ctx->getDelayFromNS(ctx->getDelayNS(from->clkconstr->period.min_delay) / ratio); + log_info(" Derived frequency constraint of %.1f MHz for net %s\n", MHz(to->clkconstr->period.min_delay), + to->name.c_str(ctx)); + changed_nets.insert(to->name); + }; + + // Run in a loop while constraints are changing to deal with dependencies + // Iteration limit avoids hanging in crazy loopback situation (self-fed PLLs or dividers, etc) + int iter = 0; + const int itermax = 5000; + while (!changed_nets.empty() && iter < itermax) { + ++iter; + std::unordered_set<IdString> changed_cells; + for (auto net : changed_nets) + for (auto &user : ctx->nets.at(net)->users) + if (user.port == id_CLKI || user.port == id_ECLKI) + changed_cells.insert(user.cell->name); + changed_nets.clear(); + for (auto cell : sorted(changed_cells)) { + CellInfo *ci = ctx->cells.at(cell).get(); + if (ci->type == id_CLKDIVF) { + std::string div = str_or_default(ci->params, ctx->id("DIV"), "2.0"); + double ratio; + if (div == "2.0") + ratio = 1 / 2.0; + else if (div == "3.5") + ratio = 1 / 3.5; + else + log_error("Unsupported divider ratio '%s' on CLKDIVF '%s'\n", div.c_str(), ci->name.c_str(ctx)); + copy_constraint(ci, id_CLKI, id_CDIVX, ratio); + } else if (ci->type == id_ECLKSYNCB || ci->type == id_TRELLIS_ECLKBUF) { + copy_constraint(ci, id_ECLKI, id_ECLKO, 1); + } else if (ci->type == id_EHXPLLL) { + delay_t period_in; + if (!get_period(ci, id_CLKI, period_in)) + continue; + log_info(" Input frequency of PLL '%s' is constrained to %.1f MHz\n", ci->name.c_str(ctx), + MHz(period_in)); + double period_in_div = period_in * int_or_default(ci->params, ctx->id("CLKI_DIV"), 1); + std::string path = str_or_default(ci->params, ctx->id("FEEDBK_PATH"), "CLKOP"); + int feedback_div = int_or_default(ci->params, ctx->id("CLKFB_DIV"), 1); + if (path == "CLKOP" || path == "INT_OP") + feedback_div *= int_or_default(ci->params, ctx->id("CLKOP_DIV"), 1); + else if (path == "CLKOS" || path == "INT_OS") + feedback_div *= int_or_default(ci->params, ctx->id("CLKOS_DIV"), 1); + else if (path == "CLKOS2" || path == "INT_OS2") + feedback_div *= int_or_default(ci->params, ctx->id("CLKOS2_DIV"), 1); + else if (path == "CLKOS3" || path == "INT_OS3") + feedback_div *= int_or_default(ci->params, ctx->id("CLKOS3_DIV"), 1); + else { + log_info(" Unable to determine output frequencies for PLL '%s' with FEEDBK_PATH=%s\n", + ci->name.c_str(ctx), path.c_str()); + continue; + } + double vco_period = period_in_div / feedback_div; + double vco_freq = MHz(vco_period); + if (vco_freq < 400 || vco_freq > 800) + log_info(" Derived VCO frequency %.1f MHz of PLL '%s' is out of legal range [400MHz, " + "800MHz]\n", + vco_freq, ci->name.c_str(ctx)); + set_period(ci, id_CLKOP, vco_period * int_or_default(ci->params, ctx->id("CLKOP_DIV"), 1)); + set_period(ci, id_CLKOS, vco_period * int_or_default(ci->params, ctx->id("CLKOS_DIV"), 1)); + set_period(ci, id_CLKOS2, vco_period * int_or_default(ci->params, ctx->id("CLKOS2_DIV"), 1)); + set_period(ci, id_CLKOS3, vco_period * int_or_default(ci->params, ctx->id("CLKOS3_DIV"), 1)); + } else if (ci->type == id_OSCG) { + int div = int_or_default(ci->params, ctx->id("DIV"), 128); + set_period(ci, id_OSC, delay_t((1.0e6 / (2.0 * 155)) * div)); + } + } + } + } + public: void pack() { pack_io(); + pack_dqsbuf(); + pack_iologic(); pack_ebr(); pack_dsps(); pack_dcus(); + pack_misc(); preplace_plls(); pack_constants(); pack_dram(); @@ -1394,6 +2395,7 @@ class Ecp5Packer pack_lut_pairs(); pack_remaining_luts(); pack_remaining_ffs(); + generate_constraints(); promote_ecp5_globals(ctx); ctx->check(); } @@ -1458,6 +2460,9 @@ void Arch::assignArchInfo() ci->sliceInfo.clkmux = id(str_or_default(ci->params, id_CLKMUX, "CLK")); ci->sliceInfo.lsrmux = id(str_or_default(ci->params, id_LSRMUX, "LSR")); ci->sliceInfo.srmode = id(str_or_default(ci->params, id_SRMODE, "LSR_OVER_CE")); + ci->sliceInfo.is_carry = str_or_default(ci->params, id("MODE"), "LOGIC") == "CCU2"; + ci->sliceInfo.sd0 = int_or_default(ci->params, id("REG0_SD"), 0); + ci->sliceInfo.sd1 = int_or_default(ci->params, id("REG1_SD"), 0); ci->sliceInfo.has_l6mux = false; if (ci->ports.count(id_FXA) && ci->ports[id_FXA].net != nullptr && ci->ports[id_FXA].net->driver.port == id_OFX0) diff --git a/ecp5/trellis_import.py b/ecp5/trellis_import.py index cdd3bd06..610bd331 100755 --- a/ecp5/trellis_import.py +++ b/ecp5/trellis_import.py @@ -119,9 +119,20 @@ def process_pio_db(ddrg, device): pinfunc = metaitem["function"] else: pinfunc = None + dqs = -1 + if "dqs" in metaitem: + tdqs = metaitem["dqs"] + if tdqs[0] == "L": + dqs = 0 + elif tdqs[0] == "R": + dqs = 2048 + suffix_size = 0 + while tdqs[-(suffix_size+1)].isdigit(): + suffix_size += 1 + dqs |= int(tdqs[-suffix_size:]) bel_idx = get_bel_index(ddrg, loc, pio) if bel_idx is not None: - pindata.append((loc, bel_idx, bank, pinfunc)) + pindata.append((loc, bel_idx, bank, pinfunc, dqs)) global_data = {} quadrants = ["UL", "UR", "LL", "LR"] @@ -142,7 +153,7 @@ speed_grade_names = ["6", "7", "8", "8_5G"] speed_grade_cells = {} speed_grade_pips = {} -pip_class_to_idx = {"default": 0} +pip_class_to_idx = {"default": 0, "zero": 1} timing_port_xform = { "RAD0": "D0", @@ -188,7 +199,7 @@ def process_timing_data(): pip_class_delays = [] for i in range(len(pip_class_to_idx)): pip_class_delays.append((50, 50, 0, 0)) - + pip_class_delays[pip_class_to_idx["zero"]] = (0, 0, 0, 0) with open(timing_dbs.interconnect_db_path("ECP5", grade)) as f: interconn_data = json.load(f) for pipclass, pipdata in sorted(interconn_data.items()): @@ -208,6 +219,12 @@ def process_timing_data(): def get_pip_class(wire_from, wire_to): + + if "FCO" in wire_from or "FCI" in wire_to: + return pip_class_to_idx["zero"] + if "F5" in wire_from or "FX" in wire_from or "FXA" in wire_to or "FXB" in wire_to: + return pip_class_to_idx["zero"] + class_name = pip_classes.get_pip_class(wire_from, wire_to) if class_name is None or class_name not in pip_class_to_idx: class_name = "default" @@ -360,7 +377,7 @@ def write_database(dev_name, chip, ddrg, endianness): bba.l("pio_info", "PIOInfoPOD") for pin in pindata: - loc, bel_idx, bank, func = pin + loc, bel_idx, bank, func, dqs = pin write_loc(loc, "abs_loc") bba.u32(bel_idx, "bel_index") if func is not None: @@ -368,7 +385,7 @@ def write_database(dev_name, chip, ddrg, endianness): else: bba.r(None, "function_name") bba.u16(bank, "bank") - bba.u16(0, "padding") + bba.u16(dqs, "dqsgroup") bba.l("tiletype_names", "RelPtr<char>") for tt, idx in sorted(tiletype_names.items(), key=lambda x: x[1]): diff --git a/generic/arch.cc b/generic/arch.cc index 77417d27..5617fa63 100644 --- a/generic/arch.cc +++ b/generic/arch.cc @@ -17,10 +17,12 @@ * */ +#include <iostream> #include <math.h> #include "nextpnr.h" #include "placer1.h" #include "router1.h" +#include "util.h" NEXTPNR_NAMESPACE_BEGIN @@ -190,9 +192,53 @@ void Arch::setPipAttr(IdString pip, IdString key, const std::string &value) { pi void Arch::setBelAttr(IdString bel, IdString key, const std::string &value) { bels.at(bel).attrs[key] = value; } +void Arch::setLutK(int K) { args.K = K; } + +void Arch::setDelayScaling(double scale, double offset) +{ + args.delayScale = scale; + args.delayOffset = offset; +} + +void Arch::addCellTimingClock(IdString cell, IdString port) { cellTiming[cell].portClasses[port] = TMG_CLOCK_INPUT; } + +void Arch::addCellTimingDelay(IdString cell, IdString fromPort, IdString toPort, DelayInfo delay) +{ + if (get_or_default(cellTiming[cell].portClasses, fromPort, TMG_IGNORE) == TMG_IGNORE) + cellTiming[cell].portClasses[fromPort] = TMG_COMB_INPUT; + if (get_or_default(cellTiming[cell].portClasses, toPort, TMG_IGNORE) == TMG_IGNORE) + cellTiming[cell].portClasses[toPort] = TMG_COMB_OUTPUT; + cellTiming[cell].combDelays[CellDelayKey{fromPort, toPort}] = delay; +} + +void Arch::addCellTimingSetupHold(IdString cell, IdString port, IdString clock, DelayInfo setup, DelayInfo hold) +{ + TimingClockingInfo ci; + ci.clock_port = clock; + ci.edge = RISING_EDGE; + ci.setup = setup; + ci.hold = hold; + cellTiming[cell].clockingInfo[port].push_back(ci); + cellTiming[cell].portClasses[port] = TMG_REGISTER_INPUT; +} + +void Arch::addCellTimingClockToOut(IdString cell, IdString port, IdString clock, DelayInfo clktoq) +{ + TimingClockingInfo ci; + ci.clock_port = clock; + ci.edge = RISING_EDGE; + ci.clockToQ = clktoq; + cellTiming[cell].clockingInfo[port].push_back(ci); + cellTiming[cell].portClasses[port] = TMG_REGISTER_OUTPUT; +} + // --------------------------------------------------------------- -Arch::Arch(ArchArgs args) : chipName("generic"), args(args) {} +Arch::Arch(ArchArgs args) : chipName("generic"), args(args) +{ + // Dummy for empty decals + decal_graphics[IdString()]; +} void IdString::initialize_arch(const BaseCtx *ctx) {} @@ -259,7 +305,13 @@ IdString Arch::getBelType(BelId bel) const { return bels.at(bel).type; } const std::map<IdString, std::string> &Arch::getBelAttrs(BelId bel) const { return bels.at(bel).attrs; } -WireId Arch::getBelPinWire(BelId bel, IdString pin) const { return bels.at(bel).pins.at(pin).wire; } +WireId Arch::getBelPinWire(BelId bel, IdString pin) const +{ + const auto &bdata = bels.at(bel); + if (!bdata.pins.count(pin)) + log_error("bel '%s' has no pin '%s'\n", bel.c_str(this), pin.c_str(this)); + return bdata.pins.at(pin).wire; +} PortType Arch::getBelPinType(BelId bel, IdString pin) const { return bels.at(bel).pins.at(pin).type; } @@ -421,7 +473,7 @@ delay_t Arch::estimateDelay(WireId src, WireId dst) const const WireInfo &d = wires.at(dst); int dx = abs(s.x - d.x); int dy = abs(s.y - d.y); - return (dx + dy) * grid_distance_to_delay; + return (dx + dy) * args.delayScale + args.delayOffset; } delay_t Arch::predictDelay(const NetInfo *net_info, const PortRef &sink) const @@ -430,22 +482,38 @@ delay_t Arch::predictDelay(const NetInfo *net_info, const PortRef &sink) const auto driver_loc = getBelLocation(driver.cell->bel); auto sink_loc = getBelLocation(sink.cell->bel); - int dx = abs(driver_loc.x - driver_loc.x); - int dy = abs(sink_loc.y - sink_loc.y); - return (dx + dy) * grid_distance_to_delay; + int dx = abs(sink_loc.x - driver_loc.x); + int dy = abs(sink_loc.y - driver_loc.y); + return (dx + dy) * args.delayScale + args.delayOffset; } bool Arch::getBudgetOverride(const NetInfo *net_info, const PortRef &sink, delay_t &budget) const { return false; } // --------------------------------------------------------------- -bool Arch::place() { return placer1(getCtx(), Placer1Cfg(getCtx())); } +bool Arch::place() +{ + std::string placer = str_or_default(settings, id("placer"), defaultPlacer); + // FIXME: No HeAP because it needs a list of IO buffers + if (placer == "sa") { + return placer1(getCtx(), Placer1Cfg(getCtx())); + } else { + log_error("Generic architecture does not support placer '%s'\n", placer.c_str()); + } +} bool Arch::route() { return router1(getCtx(), Router1Cfg(getCtx())); } // --------------------------------------------------------------- -const std::vector<GraphicElement> &Arch::getDecalGraphics(DecalId decal) const { return decal_graphics.at(decal); } +const std::vector<GraphicElement> &Arch::getDecalGraphics(DecalId decal) const +{ + if (!decal_graphics.count(decal)) { + std::cerr << "No decal named " << decal.str(this) << std::endl; + log_error("No decal named %s!\n", decal.c_str(this)); + } + return decal_graphics.at(decal); +} DecalXY Arch::getBelDecal(BelId bel) const { return bels.at(bel).decalxy; } @@ -459,21 +527,103 @@ DecalXY Arch::getGroupDecal(GroupId group) const { return groups.at(group).decal bool Arch::getCellDelay(const CellInfo *cell, IdString fromPort, IdString toPort, DelayInfo &delay) const { - return false; + if (!cellTiming.count(cell->name)) + return false; + const auto &tmg = cellTiming.at(cell->name); + auto fnd = tmg.combDelays.find(CellDelayKey{fromPort, toPort}); + if (fnd != tmg.combDelays.end()) { + delay = fnd->second; + return true; + } else { + return false; + } } // Get the port class, also setting clockPort if applicable TimingPortClass Arch::getPortTimingClass(const CellInfo *cell, IdString port, int &clockInfoCount) const { - return TMG_IGNORE; + if (!cellTiming.count(cell->name)) + return TMG_IGNORE; + const auto &tmg = cellTiming.at(cell->name); + if (tmg.clockingInfo.count(port)) + clockInfoCount = int(tmg.clockingInfo.at(port).size()); + else + clockInfoCount = 0; + return get_or_default(tmg.portClasses, port, TMG_IGNORE); } TimingClockingInfo Arch::getPortClockingInfo(const CellInfo *cell, IdString port, int index) const { - NPNR_ASSERT_FALSE("no clocking info for generic"); + NPNR_ASSERT(cellTiming.count(cell->name)); + const auto &tmg = cellTiming.at(cell->name); + NPNR_ASSERT(tmg.clockingInfo.count(port)); + return tmg.clockingInfo.at(port).at(index); +} + +bool Arch::isValidBelForCell(CellInfo *cell, BelId bel) const +{ + std::vector<const CellInfo *> cells; + cells.push_back(cell); + Loc loc = getBelLocation(bel); + for (auto tbel : getBelsByTile(loc.x, loc.y)) { + if (tbel == bel) + continue; + CellInfo *bound = getBoundBelCell(tbel); + if (bound != nullptr) + cells.push_back(bound); + } + return cellsCompatible(cells.data(), int(cells.size())); +} + +bool Arch::isBelLocationValid(BelId bel) const +{ + std::vector<const CellInfo *> cells; + Loc loc = getBelLocation(bel); + for (auto tbel : getBelsByTile(loc.x, loc.y)) { + CellInfo *bound = getBoundBelCell(tbel); + if (bound != nullptr) + cells.push_back(bound); + } + return cellsCompatible(cells.data(), int(cells.size())); +} + +const std::string Arch::defaultPlacer = "sa"; +const std::vector<std::string> Arch::availablePlacers = {"sa"}; + +void Arch::assignArchInfo() +{ + for (auto &cell : getCtx()->cells) { + CellInfo *ci = cell.second.get(); + if (ci->type == id("GENERIC_SLICE")) { + ci->is_slice = true; + ci->slice_clk = get_net_or_empty(ci, id("CLK")); + } else { + ci->is_slice = false; + } + ci->user_group = int_or_default(ci->attrs, id("PACK_GROUP"), -1); + } } -bool Arch::isValidBelForCell(CellInfo *cell, BelId bel) const { return true; } -bool Arch::isBelLocationValid(BelId bel) const { return true; } +bool Arch::cellsCompatible(const CellInfo **cells, int count) const +{ + const NetInfo *clk = nullptr; + int group = -1; + for (int i = 0; i < count; i++) { + const CellInfo *ci = cells[i]; + if (ci->is_slice && ci->slice_clk != nullptr) { + if (clk == nullptr) + clk = ci->slice_clk; + else if (clk != ci->slice_clk) + return false; + } + if (ci->user_group != -1) { + if (group == -1) + group = ci->user_group; + else if (group != ci->user_group) + return false; + } + } + return true; +} NEXTPNR_NAMESPACE_END diff --git a/generic/arch.h b/generic/arch.h index dc4258cc..e9d3593c 100644 --- a/generic/arch.h +++ b/generic/arch.h @@ -25,6 +25,11 @@ NEXTPNR_NAMESPACE_BEGIN struct ArchArgs { + // Number of LUT inputs + int K = 4; + // y = mx + c relationship between distance and delay for interconnect + // delay estimates + double delayScale = 0.1, delayOffset = 0; }; struct WireInfo; @@ -81,6 +86,33 @@ struct GroupInfo DecalXY decalxy; }; +struct CellDelayKey +{ + IdString from, to; + inline bool operator==(const CellDelayKey &other) const { return from == other.from && to == other.to; } +}; + +NEXTPNR_NAMESPACE_END +namespace std { +template <> struct hash<NEXTPNR_NAMESPACE_PREFIX CellDelayKey> +{ + std::size_t operator()(const NEXTPNR_NAMESPACE_PREFIX CellDelayKey &dk) const noexcept + { + std::size_t seed = std::hash<NEXTPNR_NAMESPACE_PREFIX IdString>()(dk.from); + seed ^= std::hash<NEXTPNR_NAMESPACE_PREFIX IdString>()(dk.to) + 0x9e3779b9 + (seed << 6) + (seed >> 2); + return seed; + } +}; +} // namespace std +NEXTPNR_NAMESPACE_BEGIN + +struct CellTiming +{ + std::unordered_map<IdString, TimingPortClass> portClasses; + std::unordered_map<CellDelayKey, DelayInfo> combDelays; + std::unordered_map<IdString, std::vector<TimingClockingInfo>> clockingInfo; +}; + struct Arch : BaseCtx { std::string chipName; @@ -101,7 +133,7 @@ struct Arch : BaseCtx std::vector<std::vector<int>> tileBelDimZ; std::vector<std::vector<int>> tilePipDimZ; - float grid_distance_to_delay; + std::unordered_map<IdString, CellTiming> cellTiming; void addWire(IdString name, IdString type, int x, int y); void addPip(IdString name, IdString type, IdString srcWire, IdString dstWire, DelayInfo delay, Loc loc); @@ -127,6 +159,14 @@ struct Arch : BaseCtx void setPipAttr(IdString pip, IdString key, const std::string &value); void setBelAttr(IdString bel, IdString key, const std::string &value); + void setLutK(int K); + void setDelayScaling(double scale, double offset); + + void addCellTimingClock(IdString cell, IdString port); + void addCellTimingDelay(IdString cell, IdString fromPort, IdString toPort, DelayInfo delay); + void addCellTimingSetupHold(IdString cell, IdString port, IdString clock, DelayInfo setup, DelayInfo hold); + void addCellTimingClockToOut(IdString cell, IdString port, IdString clock, DelayInfo clktoq); + // --------------------------------------------------------------- // Common Arch API. Every arch must provide the following methods. @@ -208,8 +248,8 @@ struct Arch : BaseCtx delay_t estimateDelay(WireId src, WireId dst) const; delay_t predictDelay(const NetInfo *net_info, const PortRef &sink) const; - delay_t getDelayEpsilon() const { return 0.01; } - delay_t getRipupDelayPenalty() const { return 1.0; } + delay_t getDelayEpsilon() const { return 0.001; } + delay_t getRipupDelayPenalty() const { return 0.015; } float getDelayNS(delay_t v) const { return v; } DelayInfo getDelayFromNS(float ns) const @@ -222,7 +262,7 @@ struct Arch : BaseCtx uint32_t getDelayChecksum(delay_t v) const { return 0; } bool getBudgetOverride(const NetInfo *net_info, const PortRef &sink, delay_t &budget) const; - bool pack() { return true; } + bool pack(); bool place(); bool route(); @@ -240,6 +280,14 @@ struct Arch : BaseCtx bool isValidBelForCell(CellInfo *cell, BelId bel) const; bool isBelLocationValid(BelId bel) const; + + static const std::string defaultPlacer; + static const std::vector<std::string> availablePlacers; + + // --------------------------------------------------------------- + // Internal usage + void assignArchInfo(); + bool cellsCompatible(const CellInfo **cells, int count) const; }; NEXTPNR_NAMESPACE_END diff --git a/generic/arch_pybindings.cc b/generic/arch_pybindings.cc index 186b2c13..8526e409 100644 --- a/generic/arch_pybindings.cc +++ b/generic/arch_pybindings.cc @@ -23,18 +23,215 @@ #include "arch_pybindings.h" #include "nextpnr.h" #include "pybindings.h" +#include "pywrappers.h" NEXTPNR_NAMESPACE_BEGIN +namespace PythonConversion { +template <> struct string_converter<const IdString &> +{ + const IdString &from_str(Context *ctx, std::string name) { NPNR_ASSERT_FALSE("unsupported"); } + + std::string to_str(Context *ctx, const IdString &id) { return id.str(ctx); } +}; +} // namespace PythonConversion void arch_wrap_python() { using namespace PythonConversion; + auto arch_cls = class_<Arch, Arch *, bases<BaseCtx>, boost::noncopyable>("Arch", init<ArchArgs>()); + + auto dxy_cls = class_<ContextualWrapper<DecalXY>>("DecalXY_", no_init); + readwrite_wrapper<DecalXY, decltype(&DecalXY::decal), &DecalXY::decal, conv_to_str<DecalId>, + conv_from_str<DecalId>>::def_wrap(dxy_cls, "decal"); + readwrite_wrapper<DecalXY, decltype(&DecalXY::x), &DecalXY::x, pass_through<float>, pass_through<float>>::def_wrap( + dxy_cls, "x"); + readwrite_wrapper<DecalXY, decltype(&DecalXY::y), &DecalXY::y, pass_through<float>, pass_through<float>>::def_wrap( + dxy_cls, "y"); + auto ctx_cls = class_<Context, Context *, bases<Arch>, boost::noncopyable>("Context", no_init) .def("checksum", &Context::checksum) .def("pack", &Context::pack) .def("place", &Context::place) .def("route", &Context::route); + + class_<BelPin>("BelPin").def_readwrite("bel", &BelPin::bel).def_readwrite("pin", &BelPin::pin); + + class_<DelayInfo>("DelayInfo").def("maxDelay", &DelayInfo::maxDelay).def("minDelay", &DelayInfo::minDelay); + + fn_wrapper_1a<Context, decltype(&Context::getBelType), &Context::getBelType, conv_to_str<IdString>, + conv_from_str<BelId>>::def_wrap(ctx_cls, "getBelType"); + fn_wrapper_1a<Context, decltype(&Context::checkBelAvail), &Context::checkBelAvail, pass_through<bool>, + conv_from_str<BelId>>::def_wrap(ctx_cls, "checkBelAvail"); + fn_wrapper_1a<Context, decltype(&Context::getBelChecksum), &Context::getBelChecksum, pass_through<uint32_t>, + conv_from_str<BelId>>::def_wrap(ctx_cls, "getBelChecksum"); + fn_wrapper_3a_v<Context, decltype(&Context::bindBel), &Context::bindBel, conv_from_str<BelId>, + addr_and_unwrap<CellInfo>, pass_through<PlaceStrength>>::def_wrap(ctx_cls, "bindBel"); + fn_wrapper_1a_v<Context, decltype(&Context::unbindBel), &Context::unbindBel, conv_from_str<BelId>>::def_wrap( + ctx_cls, "unbindBel"); + fn_wrapper_1a<Context, decltype(&Context::getBoundBelCell), &Context::getBoundBelCell, deref_and_wrap<CellInfo>, + conv_from_str<BelId>>::def_wrap(ctx_cls, "getBoundBelCell"); + fn_wrapper_1a<Context, decltype(&Context::getConflictingBelCell), &Context::getConflictingBelCell, + deref_and_wrap<CellInfo>, conv_from_str<BelId>>::def_wrap(ctx_cls, "getConflictingBelCell"); + fn_wrapper_0a<Context, decltype(&Context::getBels), &Context::getBels, + wrap_context<const std::vector<BelId> &>>::def_wrap(ctx_cls, "getBels"); + + fn_wrapper_2a<Context, decltype(&Context::getBelPinWire), &Context::getBelPinWire, conv_to_str<WireId>, + conv_from_str<BelId>, conv_from_str<IdString>>::def_wrap(ctx_cls, "getBelPinWire"); + fn_wrapper_1a<Context, decltype(&Context::getWireBelPins), &Context::getWireBelPins, + wrap_context<const std::vector<BelPin> &>, conv_from_str<WireId>>::def_wrap(ctx_cls, + "getWireBelPins"); + + fn_wrapper_1a<Context, decltype(&Context::getWireChecksum), &Context::getWireChecksum, pass_through<uint32_t>, + conv_from_str<WireId>>::def_wrap(ctx_cls, "getWireChecksum"); + fn_wrapper_3a_v<Context, decltype(&Context::bindWire), &Context::bindWire, conv_from_str<WireId>, + addr_and_unwrap<NetInfo>, pass_through<PlaceStrength>>::def_wrap(ctx_cls, "bindWire"); + fn_wrapper_1a_v<Context, decltype(&Context::unbindWire), &Context::unbindWire, conv_from_str<WireId>>::def_wrap( + ctx_cls, "unbindWire"); + fn_wrapper_1a<Context, decltype(&Context::checkWireAvail), &Context::checkWireAvail, pass_through<bool>, + conv_from_str<WireId>>::def_wrap(ctx_cls, "checkWireAvail"); + fn_wrapper_1a<Context, decltype(&Context::getBoundWireNet), &Context::getBoundWireNet, deref_and_wrap<NetInfo>, + conv_from_str<WireId>>::def_wrap(ctx_cls, "getBoundWireNet"); + fn_wrapper_1a<Context, decltype(&Context::getConflictingWireNet), &Context::getConflictingWireNet, + deref_and_wrap<NetInfo>, conv_from_str<WireId>>::def_wrap(ctx_cls, "getConflictingWireNet"); + + fn_wrapper_0a<Context, decltype(&Context::getWires), &Context::getWires, + wrap_context<const std::vector<WireId> &>>::def_wrap(ctx_cls, "getWires"); + + fn_wrapper_0a<Context, decltype(&Context::getPips), &Context::getPips, + wrap_context<const std::vector<PipId> &>>::def_wrap(ctx_cls, "getPips"); + fn_wrapper_1a<Context, decltype(&Context::getPipChecksum), &Context::getPipChecksum, pass_through<uint32_t>, + conv_from_str<PipId>>::def_wrap(ctx_cls, "getPipChecksum"); + fn_wrapper_3a_v<Context, decltype(&Context::bindPip), &Context::bindPip, conv_from_str<PipId>, + addr_and_unwrap<NetInfo>, pass_through<PlaceStrength>>::def_wrap(ctx_cls, "bindPip"); + fn_wrapper_1a_v<Context, decltype(&Context::unbindPip), &Context::unbindPip, conv_from_str<PipId>>::def_wrap( + ctx_cls, "unbindPip"); + fn_wrapper_1a<Context, decltype(&Context::checkPipAvail), &Context::checkPipAvail, pass_through<bool>, + conv_from_str<PipId>>::def_wrap(ctx_cls, "checkPipAvail"); + fn_wrapper_1a<Context, decltype(&Context::getBoundPipNet), &Context::getBoundPipNet, deref_and_wrap<NetInfo>, + conv_from_str<PipId>>::def_wrap(ctx_cls, "getBoundPipNet"); + fn_wrapper_1a<Context, decltype(&Context::getConflictingPipNet), &Context::getConflictingPipNet, + deref_and_wrap<NetInfo>, conv_from_str<PipId>>::def_wrap(ctx_cls, "getConflictingPipNet"); + + fn_wrapper_1a<Context, decltype(&Context::getPipsDownhill), &Context::getPipsDownhill, + wrap_context<const std::vector<PipId> &>, conv_from_str<WireId>>::def_wrap(ctx_cls, + "getPipsDownhill"); + fn_wrapper_1a<Context, decltype(&Context::getPipsUphill), &Context::getPipsUphill, + wrap_context<const std::vector<PipId> &>, conv_from_str<WireId>>::def_wrap(ctx_cls, "getPipsUphill"); + fn_wrapper_1a<Context, decltype(&Context::getWireAliases), &Context::getWireAliases, + wrap_context<const std::vector<PipId> &>, conv_from_str<WireId>>::def_wrap(ctx_cls, "getWireAliases"); + + fn_wrapper_1a<Context, decltype(&Context::getPipSrcWire), &Context::getPipSrcWire, conv_to_str<WireId>, + conv_from_str<PipId>>::def_wrap(ctx_cls, "getPipSrcWire"); + fn_wrapper_1a<Context, decltype(&Context::getPipDstWire), &Context::getPipDstWire, conv_to_str<WireId>, + conv_from_str<PipId>>::def_wrap(ctx_cls, "getPipDstWire"); + fn_wrapper_1a<Context, decltype(&Context::getPipDelay), &Context::getPipDelay, pass_through<DelayInfo>, + conv_from_str<PipId>>::def_wrap(ctx_cls, "getPipDelay"); + + fn_wrapper_1a<Context, decltype(&Context::getDelayFromNS), &Context::getDelayFromNS, pass_through<DelayInfo>, + pass_through<double>>::def_wrap(ctx_cls, "getDelayFromNS"); + + fn_wrapper_0a<Context, decltype(&Context::getChipName), &Context::getChipName, pass_through<std::string>>::def_wrap( + ctx_cls, "getChipName"); + fn_wrapper_0a<Context, decltype(&Context::archId), &Context::archId, conv_to_str<IdString>>::def_wrap(ctx_cls, + "archId"); + + fn_wrapper_3a<Context, decltype(&Context::constructDecalXY), &Context::constructDecalXY, wrap_context<DecalXY>, + conv_from_str<DecalId>, pass_through<float>, pass_through<float>>::def_wrap(ctx_cls, "DecalXY"); + + typedef std::unordered_map<IdString, std::unique_ptr<CellInfo>> CellMap; + typedef std::unordered_map<IdString, std::unique_ptr<NetInfo>> NetMap; + + readonly_wrapper<Context, decltype(&Context::cells), &Context::cells, wrap_context<CellMap &>>::def_wrap(ctx_cls, + "cells"); + readonly_wrapper<Context, decltype(&Context::nets), &Context::nets, wrap_context<NetMap &>>::def_wrap(ctx_cls, + "nets"); + + fn_wrapper_2a_v<Context, decltype(&Context::addClock), &Context::addClock, conv_from_str<IdString>, + pass_through<float>>::def_wrap(ctx_cls, "addClock"); + + // Generic arch construction API + fn_wrapper_4a_v<Context, decltype(&Context::addWire), &Context::addWire, conv_from_str<IdString>, + conv_from_str<IdString>, pass_through<int>, pass_through<int>>::def_wrap(ctx_cls, "addWire", + (arg("name"), "type", "x", + "y")); + fn_wrapper_6a_v<Context, decltype(&Context::addPip), &Context::addPip, conv_from_str<IdString>, + conv_from_str<IdString>, conv_from_str<IdString>, conv_from_str<IdString>, pass_through<DelayInfo>, + pass_through<Loc>>::def_wrap(ctx_cls, "addPip", + (arg("name"), "type", "srcWire", "dstWire", "delay", "loc")); + fn_wrapper_5a_v<Context, decltype(&Context::addAlias), &Context::addAlias, conv_from_str<IdString>, + conv_from_str<IdString>, conv_from_str<IdString>, conv_from_str<IdString>, + pass_through<DelayInfo>>::def_wrap(ctx_cls, "addAlias", + (arg("name"), "type", "srcWire", "dstWire", "delay")); + + fn_wrapper_4a_v<Context, decltype(&Context::addBel), &Context::addBel, conv_from_str<IdString>, + conv_from_str<IdString>, pass_through<Loc>, pass_through<bool>>::def_wrap(ctx_cls, "addBel", + (arg("name"), "type", + "loc", "gb")); + fn_wrapper_3a_v<Context, decltype(&Context::addBelInput), &Context::addBelInput, conv_from_str<IdString>, + conv_from_str<IdString>, conv_from_str<IdString>>::def_wrap(ctx_cls, "addBelInput", + (arg("bel"), "name", "wire")); + fn_wrapper_3a_v<Context, decltype(&Context::addBelOutput), &Context::addBelOutput, conv_from_str<IdString>, + conv_from_str<IdString>, conv_from_str<IdString>>::def_wrap(ctx_cls, "addBelOutput", + (arg("bel"), "name", "wire")); + fn_wrapper_3a_v<Context, decltype(&Context::addBelInout), &Context::addBelInout, conv_from_str<IdString>, + conv_from_str<IdString>, conv_from_str<IdString>>::def_wrap(ctx_cls, "addBelInout", + (arg("bel"), "name", "wire")); + + fn_wrapper_2a_v<Context, decltype(&Context::addGroupBel), &Context::addGroupBel, conv_from_str<IdString>, + conv_from_str<IdString>>::def_wrap(ctx_cls, "addGroupBel", (arg("group"), "bel")); + fn_wrapper_2a_v<Context, decltype(&Context::addGroupWire), &Context::addGroupWire, conv_from_str<IdString>, + conv_from_str<IdString>>::def_wrap(ctx_cls, "addGroupWire", (arg("group"), "wire")); + fn_wrapper_2a_v<Context, decltype(&Context::addGroupPip), &Context::addGroupPip, conv_from_str<IdString>, + conv_from_str<IdString>>::def_wrap(ctx_cls, "addGroupPip", (arg("group"), "pip")); + fn_wrapper_2a_v<Context, decltype(&Context::addGroupGroup), &Context::addGroupPip, conv_from_str<IdString>, + conv_from_str<IdString>>::def_wrap(ctx_cls, "addGroupGroup", (arg("group"), "grp")); + + fn_wrapper_2a_v<Context, decltype(&Context::addDecalGraphic), &Context::addDecalGraphic, conv_from_str<DecalId>, + pass_through<GraphicElement>>::def_wrap(ctx_cls, "addDecalGraphic", (arg("decal"), "graphic")); + fn_wrapper_2a_v<Context, decltype(&Context::setWireDecal), &Context::setWireDecal, conv_from_str<DecalId>, + unwrap_context<DecalXY>>::def_wrap(ctx_cls, "setWireDecal", (arg("wire"), "decalxy")); + fn_wrapper_2a_v<Context, decltype(&Context::setPipDecal), &Context::setPipDecal, conv_from_str<DecalId>, + unwrap_context<DecalXY>>::def_wrap(ctx_cls, "setPipDecal", (arg("pip"), "decalxy")); + fn_wrapper_2a_v<Context, decltype(&Context::setBelDecal), &Context::setBelDecal, conv_from_str<DecalId>, + unwrap_context<DecalXY>>::def_wrap(ctx_cls, "setBelDecal", (arg("bel"), "decalxy")); + fn_wrapper_2a_v<Context, decltype(&Context::setGroupDecal), &Context::setGroupDecal, conv_from_str<DecalId>, + unwrap_context<DecalXY>>::def_wrap(ctx_cls, "setGroupDecal", (arg("group"), "decalxy")); + + fn_wrapper_3a_v<Context, decltype(&Context::setWireAttr), &Context::setWireAttr, conv_from_str<DecalId>, + conv_from_str<IdString>, pass_through<std::string>>::def_wrap(ctx_cls, "setWireAttr", + (arg("wire"), "key", "value")); + fn_wrapper_3a_v<Context, decltype(&Context::setBelAttr), &Context::setBelAttr, conv_from_str<DecalId>, + conv_from_str<IdString>, pass_through<std::string>>::def_wrap(ctx_cls, "setBelAttr", + (arg("bel"), "key", "value")); + fn_wrapper_3a_v<Context, decltype(&Context::setPipAttr), &Context::setPipAttr, conv_from_str<DecalId>, + conv_from_str<IdString>, pass_through<std::string>>::def_wrap(ctx_cls, "setPipAttr", + (arg("pip"), "key", "value")); + + fn_wrapper_1a_v<Context, decltype(&Context::setLutK), &Context::setLutK, pass_through<int>>::def_wrap( + ctx_cls, "setLutK", arg("K")); + fn_wrapper_2a_v<Context, decltype(&Context::setDelayScaling), &Context::setDelayScaling, pass_through<double>, + pass_through<double>>::def_wrap(ctx_cls, "setDelayScaling", (arg("scale"), "offset")); + + fn_wrapper_2a_v<Context, decltype(&Context::addCellTimingClock), &Context::addCellTimingClock, + conv_from_str<IdString>, conv_from_str<IdString>>::def_wrap(ctx_cls, "addCellTimingClock", + (arg("cell"), "port")); + fn_wrapper_4a_v<Context, decltype(&Context::addCellTimingDelay), &Context::addCellTimingDelay, + conv_from_str<IdString>, conv_from_str<IdString>, conv_from_str<IdString>, + pass_through<DelayInfo>>::def_wrap(ctx_cls, "addCellTimingDelay", + (arg("cell"), "fromPort", "toPort", "delay")); + fn_wrapper_5a_v<Context, decltype(&Context::addCellTimingSetupHold), &Context::addCellTimingSetupHold, + conv_from_str<IdString>, conv_from_str<IdString>, conv_from_str<IdString>, pass_through<DelayInfo>, + pass_through<DelayInfo>>::def_wrap(ctx_cls, "addCellTimingSetupHold", + (arg("cell"), "port", "clock", "setup", "hold")); + fn_wrapper_4a_v<Context, decltype(&Context::addCellTimingClockToOut), &Context::addCellTimingClockToOut, + conv_from_str<IdString>, conv_from_str<IdString>, conv_from_str<IdString>, + pass_through<DelayInfo>>::def_wrap(ctx_cls, "addCellTimingClockToOut", + (arg("cell"), "port", "clock", "clktoq")); + + WRAP_MAP_UPTR(CellMap, "IdCellMap"); + WRAP_MAP_UPTR(NetMap, "IdNetMap"); + WRAP_VECTOR(const std::vector<IdString>, conv_to_str<IdString>); } NEXTPNR_NAMESPACE_END diff --git a/generic/archdefs.h b/generic/archdefs.h index 2452aa17..978c9c9b 100644 --- a/generic/archdefs.h +++ b/generic/archdefs.h @@ -55,8 +55,18 @@ typedef IdString DecalId; struct ArchNetInfo { }; + +struct NetInfo; + struct ArchCellInfo { + // Custom grouping set via "PACK_GROUP" attribute. All cells with the same group + // value may share a tile (-1 = don't care, default if not set) + int user_group; + // Is a slice type primitive + bool is_slice; + // Only packing rule for slice type primitives is a single clock per tile + const NetInfo *slice_clk; }; NEXTPNR_NAMESPACE_END diff --git a/generic/cells.cc b/generic/cells.cc new file mode 100644 index 00000000..14b368b2 --- /dev/null +++ b/generic/cells.cc @@ -0,0 +1,139 @@ +/* + * nextpnr -- Next Generation Place and Route + * + * Copyright (C) 2019 David Shah <david@symbioticeda.com> + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +#include "cells.h" +#include "design_utils.h" +#include "log.h" +#include "util.h" + +NEXTPNR_NAMESPACE_BEGIN + +void add_port(const Context *ctx, CellInfo *cell, std::string name, PortType dir) +{ + IdString id = ctx->id(name); + NPNR_ASSERT(cell->ports.count(id) == 0); + cell->ports[id] = PortInfo{id, nullptr, dir}; +} + +std::unique_ptr<CellInfo> create_generic_cell(Context *ctx, IdString type, std::string name) +{ + static int auto_idx = 0; + std::unique_ptr<CellInfo> new_cell = std::unique_ptr<CellInfo>(new CellInfo()); + if (name.empty()) { + new_cell->name = ctx->id("$nextpnr_" + type.str(ctx) + "_" + std::to_string(auto_idx++)); + } else { + new_cell->name = ctx->id(name); + } + new_cell->type = type; + if (type == ctx->id("GENERIC_SLICE")) { + new_cell->params[ctx->id("K")] = std::to_string(ctx->args.K); + new_cell->params[ctx->id("INIT")] = "0"; + new_cell->params[ctx->id("FF_USED")] = "0"; + + for (int i = 0; i < ctx->args.K; i++) + add_port(ctx, new_cell.get(), "I[" + std::to_string(i) + "]", PORT_IN); + + add_port(ctx, new_cell.get(), "CLK", PORT_IN); + + add_port(ctx, new_cell.get(), "Q", PORT_OUT); + } else if (type == ctx->id("GENERIC_IOB")) { + new_cell->params[ctx->id("INPUT_USED")] = "0"; + new_cell->params[ctx->id("OUTPUT_USED")] = "0"; + new_cell->params[ctx->id("ENABLE_USED")] = "0"; + + add_port(ctx, new_cell.get(), "PAD", PORT_INOUT); + add_port(ctx, new_cell.get(), "I", PORT_IN); + add_port(ctx, new_cell.get(), "EN", PORT_IN); + add_port(ctx, new_cell.get(), "O", PORT_OUT); + } else { + log_error("unable to create generic cell of type %s", type.c_str(ctx)); + } + return new_cell; +} + +void lut_to_lc(const Context *ctx, CellInfo *lut, CellInfo *lc, bool no_dff) +{ + lc->params[ctx->id("INIT")] = lut->params[ctx->id("INIT")]; + + int lut_k = int_or_default(lut->params, ctx->id("K"), 4); + NPNR_ASSERT(lut_k <= ctx->args.K); + + for (int i = 0; i < lut_k; i++) { + IdString port = ctx->id("I[" + std::to_string(i) + "]"); + replace_port(lut, port, lc, port); + } + + if (no_dff) { + replace_port(lut, ctx->id("Q"), lc, ctx->id("Q")); + lc->params[ctx->id("FF_USED")] = "0"; + } +} + +void dff_to_lc(const Context *ctx, CellInfo *dff, CellInfo *lc, bool pass_thru_lut) +{ + lc->params[ctx->id("FF_USED")] = "1"; + replace_port(dff, ctx->id("CLK"), lc, ctx->id("CLK")); + + if (pass_thru_lut) { + lc->params[ctx->id("INIT")] = "2"; + replace_port(dff, ctx->id("D"), lc, ctx->id("I[0]")); + } + + replace_port(dff, ctx->id("Q"), lc, ctx->id("Q")); +} + +void nxio_to_iob(Context *ctx, CellInfo *nxio, CellInfo *iob, std::unordered_set<IdString> &todelete_cells) +{ + if (nxio->type == ctx->id("$nextpnr_ibuf")) { + iob->params[ctx->id("INPUT_USED")] = "1"; + replace_port(nxio, ctx->id("O"), iob, ctx->id("O")); + } else if (nxio->type == ctx->id("$nextpnr_obuf")) { + iob->params[ctx->id("OUTPUT_USED")] = "1"; + replace_port(nxio, ctx->id("I"), iob, ctx->id("I")); + } else if (nxio->type == ctx->id("$nextpnr_iobuf")) { + // N.B. tristate will be dealt with below + iob->params[ctx->id("INPUT_USED")] = "1"; + iob->params[ctx->id("OUTPUT_USED")] = "1"; + replace_port(nxio, ctx->id("I"), iob, ctx->id("I")); + replace_port(nxio, ctx->id("O"), iob, ctx->id("O")); + } else { + NPNR_ASSERT(false); + } + NetInfo *donet = iob->ports.at(ctx->id("I")).net; + CellInfo *tbuf = net_driven_by( + ctx, donet, [](const Context *ctx, const CellInfo *cell) { return cell->type == ctx->id("$_TBUF_"); }, + ctx->id("Y")); + if (tbuf) { + iob->params[ctx->id("ENABLE_USED")] = "1"; + replace_port(tbuf, ctx->id("A"), iob, ctx->id("I")); + replace_port(tbuf, ctx->id("E"), iob, ctx->id("EN")); + + if (donet->users.size() > 1) { + for (auto user : donet->users) + log_info(" remaining tristate user: %s.%s\n", user.cell->name.c_str(ctx), user.port.c_str(ctx)); + log_error("unsupported tristate IO pattern for IO buffer '%s', " + "instantiate GENERIC_IOB manually to ensure correct behaviour\n", + nxio->name.c_str(ctx)); + } + ctx->nets.erase(donet->name); + todelete_cells.insert(tbuf->name); + } +} + +NEXTPNR_NAMESPACE_END diff --git a/generic/cells.h b/generic/cells.h new file mode 100644 index 00000000..646d738d --- /dev/null +++ b/generic/cells.h @@ -0,0 +1,55 @@ +/* + * nextpnr -- Next Generation Place and Route + * + * Copyright (C) 2019 David Shah <david@symbioticeda.com> + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +#include "nextpnr.h" + +#ifndef GENERIC_CELLS_H +#define GENERIC_CELLS_H + +NEXTPNR_NAMESPACE_BEGIN + +// Create a generic arch cell and return it +// Name will be automatically assigned if not specified +std::unique_ptr<CellInfo> create_generic_cell(Context *ctx, IdString type, std::string name = ""); + +// Return true if a cell is a LUT +inline bool is_lut(const BaseCtx *ctx, const CellInfo *cell) { return cell->type == ctx->id("LUT"); } + +// Return true if a cell is a flipflop +inline bool is_ff(const BaseCtx *ctx, const CellInfo *cell) { return cell->type == ctx->id("DFF"); } + +inline bool is_lc(const BaseCtx *ctx, const CellInfo *cell) { return cell->type == ctx->id("GENERIC_SLICE"); } + +// Convert a LUT primitive to (part of) an GENERIC_SLICE, swapping ports +// as needed. Set no_dff if a DFF is not being used, so that the output +// can be reconnected +void lut_to_lc(const Context *ctx, CellInfo *lut, CellInfo *lc, bool no_dff = true); + +// Convert a DFF primitive to (part of) an GENERIC_SLICE, setting parameters +// and reconnecting signals as necessary. If pass_thru_lut is True, the LUT will +// be configured as pass through and D connected to I0, otherwise D will be +// ignored +void dff_to_lc(const Context *ctx, CellInfo *dff, CellInfo *lc, bool pass_thru_lut = false); + +// Convert a nextpnr IO buffer to a GENERIC_IOB +void nxio_to_iob(Context *ctx, CellInfo *nxio, CellInfo *sbio, std::unordered_set<IdString> &todelete_cells); + +NEXTPNR_NAMESPACE_END + +#endif diff --git a/generic/examples/.gitignore b/generic/examples/.gitignore new file mode 100644 index 00000000..38e95de5 --- /dev/null +++ b/generic/examples/.gitignore @@ -0,0 +1,3 @@ +blinky.fasm +__pycache__ +*.pyc diff --git a/generic/examples/README.md b/generic/examples/README.md new file mode 100644 index 00000000..9fd106d9 --- /dev/null +++ b/generic/examples/README.md @@ -0,0 +1,14 @@ +# Generic Architecture Example + +This contains a simple, artificial, example of the nextpnr generic API. + + - simple.py procedurally generates a simple FPGA architecture with IO at the edges, + logic slices in all other tiles, and interconnect only between adjacent tiles + + - simple_timing.py annotates cells with timing data (this is a separate script that must be run after packing) + + - write_fasm.py uses the nextpnr Python API to write a FASM file for a design + + - bitstream.py uses write_fasm.py to create a FASM ("FPGA assembly") file for the place-and-routed design + + - Run simple.sh to build an example design on the FPGA above
\ No newline at end of file diff --git a/generic/examples/__init__.py b/generic/examples/__init__.py new file mode 100644 index 00000000..e69de29b --- /dev/null +++ b/generic/examples/__init__.py diff --git a/generic/examples/bitstream.py b/generic/examples/bitstream.py new file mode 100644 index 00000000..1ab94f0c --- /dev/null +++ b/generic/examples/bitstream.py @@ -0,0 +1,17 @@ +from write_fasm import * +from simple_config import K + +# Need to tell FASM generator how to write parameters +# (celltype, parameter) -> ParameterConfig +param_map = { + ("GENERIC_SLICE", "K"): ParameterConfig(write=False), + ("GENERIC_SLICE", "INIT"): ParameterConfig(write=True, numeric=True, width=2**K), + ("GENERIC_SLICE", "FF_USED"): ParameterConfig(write=True, numeric=True, width=1), + + ("GENERIC_IOB", "INPUT_USED"): ParameterConfig(write=True, numeric=True, width=1), + ("GENERIC_IOB", "OUTPUT_USED"): ParameterConfig(write=True, numeric=True, width=1), + ("GENERIC_IOB", "ENABLE_USED"): ParameterConfig(write=True, numeric=True, width=1), +} + +with open("blinky.fasm", "w") as f: + write_fasm(ctx, param_map, f)
\ No newline at end of file diff --git a/generic/examples/blinky.v b/generic/examples/blinky.v new file mode 100644 index 00000000..b7cb1b86 --- /dev/null +++ b/generic/examples/blinky.v @@ -0,0 +1,9 @@ +module top(input clk, output reg [7:0] leds); + +reg [25:0] ctr; +always @(posedge clk) + ctr <= ctr + 1'b1; + +assign leds = ctr[25:18]; + +endmodule
\ No newline at end of file diff --git a/generic/examples/simple.py b/generic/examples/simple.py new file mode 100644 index 00000000..9339b68a --- /dev/null +++ b/generic/examples/simple.py @@ -0,0 +1,72 @@ +from simple_config import * + +def is_io(x, y): + return x == 0 or x == X-1 or y == 0 or y == Y-1 + +for x in range(X): + for y in range(Y): + # Bel port wires + for z in range(N): + ctx.addWire(name="X%dY%dZ%d_CLK" % (x, y, z), type="BEL_CLK", x=x, y=y) + ctx.addWire(name="X%dY%dZ%d_Q" % (x, y, z), type="BEL_Q", x=x, y=y) + for i in range(K): + ctx.addWire(name="X%dY%dZ%d_I%d" % (x, y, z, i), type="BEL_I", x=x, y=y) + # Local wires + for l in range(Wl): + ctx.addWire(name="X%dY%d_LOCAL%d" % (x, y, l), type="LOCAL", x=x, y=y) + # Create bels + if is_io(x, y): + if x == y: + continue + for z in range(2): + ctx.addBel(name="X%dY%d_IO%d" % (x, y, z), type="GENERIC_IOB", loc=Loc(x, y, z), gb=False) + ctx.addBelInput(bel="X%dY%d_IO%d" % (x, y, z), name="I", wire="X%dY%dZ%d_I0" % (x, y, z)) + ctx.addBelInput(bel="X%dY%d_IO%d" % (x, y, z), name="EN", wire="X%dY%dZ%d_I1" % (x, y, z)) + ctx.addBelOutput(bel="X%dY%d_IO%d" % (x, y, z), name="O", wire="X%dY%dZ%d_Q" % (x, y, z)) + else: + for z in range(N): + ctx.addBel(name="X%dY%d_SLICE%d" % (x, y, z), type="GENERIC_SLICE", loc=Loc(x, y, z), gb=False) + ctx.addBelInput(bel="X%dY%d_SLICE%d" % (x, y, z), name="CLK", wire="X%dY%dZ%d_CLK" % (x, y, z)) + for k in range(K): + ctx.addBelInput(bel="X%dY%d_SLICE%d" % (x, y, z), name="I[%d]" % k, wire="X%dY%dZ%d_I%d" % (x, y, z, k)) + ctx.addBelOutput(bel="X%dY%d_SLICE%d" % (x, y, z), name="Q", wire="X%dY%dZ%d_Q" % (x, y, z)) + +for x in range(X): + for y in range(Y): + # Pips driving bel input wires + # Bel input wires are driven by every Si'th local with an offset + def create_input_pips(dst, offset, skip): + for i in range(offset % skip, Wl, skip): + src = "X%dY%d_LOCAL%d" % (x, y, i) + ctx.addPip(name="X%dY%d.%s.%s" % (x, y, src, dst), type="BEL_INPUT", + srcWire=src, dstWire=dst, delay=ctx.getDelayFromNS(0.05), loc=Loc(x, y, 0)) + for z in range(N): + create_input_pips("X%dY%dZ%d_CLK" % (x, y, z), 0, Si) + for k in range(K): + create_input_pips("X%dY%dZ%d_I%d" % (x, y, z, k), k % Si, Si) + + # Pips from bel outputs to locals + def create_output_pips(dst, offset, skip): + for i in range(offset % skip, N, skip): + src = "X%dY%dZ%d_Q" % (x, y, i) + ctx.addPip(name="X%dY%d.%s.%s" % (x, y, src, dst), type="BEL_OUTPUT", + srcWire=src, dstWire=dst, delay=ctx.getDelayFromNS(0.05), loc=Loc(x, y, 0)) + # Pips from neighbour locals to locals + def create_neighbour_pips(dst, nx, ny, offset, skip): + if nx < 0 or nx >= X or ny < 0 or ny >= Y: + return + for i in range(offset % skip, Wl, skip): + src = "X%dY%d_LOCAL%d" % (nx, ny, i) + ctx.addPip(name="X%dY%d.%s.%s" % (x, y, src, dst), type="NEIGHBOUR", + srcWire=src, dstWire=dst, delay=ctx.getDelayFromNS(0.05), loc=Loc(x, y, 0)) + for l in range(Wl): + dst = "X%dY%d_LOCAL%d" % (x, y, l) + create_output_pips(dst, l % Sq, Sq) + create_neighbour_pips(dst, x-1, y-1, (l + 1) % Sl, Sl) + create_neighbour_pips(dst, x-1, y, (l + 2) % Sl, Sl) + create_neighbour_pips(dst, x-1, y+1, (l + 2) % Sl, Sl) + create_neighbour_pips(dst, x, y-1, (l + 3) % Sl, Sl) + create_neighbour_pips(dst, x, y+1, (l + 4) % Sl, Sl) + create_neighbour_pips(dst, x+1, y-1, (l + 5) % Sl, Sl) + create_neighbour_pips(dst, x+1, y, (l + 6) % Sl, Sl) + create_neighbour_pips(dst, x+1, y+1, (l + 7) % Sl, Sl)
\ No newline at end of file diff --git a/generic/examples/simple.sh b/generic/examples/simple.sh new file mode 100755 index 00000000..8ae903f9 --- /dev/null +++ b/generic/examples/simple.sh @@ -0,0 +1,4 @@ +#!/usr/bin/env bash +set -ex +yosys -p "tcl ../synth/synth_generic.tcl 4 blinky.json" blinky.v +${NEXTPNR:-../../nextpnr-generic} --pre-pack simple.py --pre-place simple_timing.py --json blinky.json --post-route bitstream.py diff --git a/generic/examples/simple_config.py b/generic/examples/simple_config.py new file mode 100644 index 00000000..dfb38f1c --- /dev/null +++ b/generic/examples/simple_config.py @@ -0,0 +1,15 @@ +# Grid size including IOBs at edges +X = 12 +Y = 12 +# SLICEs per tile +N = 8 +# LUT input count +K = 4 +# Number of local wires +Wl = N*(K+1) + 8 +# 1/Fc for bel input wire pips +Si = 4 +# 1/Fc for Q to local wire pips +Sq = 4 +# ~1/Fc local to neighbour local wire pips +Sl = 8
\ No newline at end of file diff --git a/generic/examples/simple_timing.py b/generic/examples/simple_timing.py new file mode 100644 index 00000000..a955c8d7 --- /dev/null +++ b/generic/examples/simple_timing.py @@ -0,0 +1,15 @@ +for cname, cell in ctx.cells: + if cell.type != "GENERIC_SLICE": + continue + if cname in ("$PACKER_GND", "$PACKER_VCC"): + continue + K = int(cell.params["K"]) + if cell.params["FF_USED"] == "1": + ctx.addCellTimingClock(cell=cname, port="CLK") + for i in range(K): + ctx.addCellTimingSetupHold(cell=cname, port="I[%d]" % i, clock="CLK", + setup=ctx.getDelayFromNS(0.2), hold=ctx.getDelayFromNS(0)) + ctx.addCellTimingClockToOut(cell=cname, port="Q", clock="CLK", clktoq=ctx.getDelayFromNS(0.2)) + else: + for i in range(K): + ctx.addCellTimingDelay(cell=cname, fromPort="I[%d]" % i, toPort="Q", delay=ctx.getDelayFromNS(0.2))
\ No newline at end of file diff --git a/generic/examples/write_fasm.py b/generic/examples/write_fasm.py new file mode 100644 index 00000000..1f279b63 --- /dev/null +++ b/generic/examples/write_fasm.py @@ -0,0 +1,52 @@ +from collections import namedtuple + +""" + write: set to True to enable writing this parameter to FASM + + numeric: set to True to write this parameter as a bit array (width>1) or + single bit (width==1) named after the parameter. Otherwise this + parameter will be written as `name.value` + + width: width of numeric parameter (ignored for non-numeric parameters) + + alias: an alternative name for this parameter (parameter name used if alias + is None) +""" +ParameterConfig = namedtuple('ParameterConfig', 'write numeric width alias') + +# FIXME use defaults= once Python 3.7 is standard +ParameterConfig.__new__.__defaults__ = (False, True, 1, None) + + +""" +Write a design as FASM + + ctx: nextpnr context + paramCfg: map from (celltype, parametername) -> ParameterConfig describing how to write parameters + f: output file +""" +def write_fasm(ctx, paramCfg, f): + for nname, net in sorted(ctx.nets, key=lambda x: str(x[1].name)): + print("# Net %s" % nname, file=f) + for wire, pip in sorted(net.wires, key=lambda x: str(x[1])): + if pip.pip != "": + print("%s" % pip.pip, file=f) + print("", file=f) + for cname, cell in sorted(ctx.cells, key=lambda x: str(x[1].name)): + print("# Cell %s at %s" % (cname, cell.bel), file=f) + for param, val in sorted(cell.params, key=lambda x: str(x)): + cfg = paramCfg[(cell.type, param)] + if not cfg.write: + continue + fasm_name = cfg.alias if cfg.alias is not None else param + if cfg.numeric: + if cfg.width == 1: + if int(val) != 0: + print("%s.%s" % (cell.bel, fasm_name), file=f) + else: + # Parameters with width >32 are direct binary, otherwise denary + binval = val if cfg.width > 32 else "{:0{}b}".format(int(val), cfg.width) + print("%s.%s[%d:0] = %d'b%s" % (cell.bel, fasm_name, cfg.width-1, cfg.width, binval), file=f) + else: + print("%s.%s.%s" % (cell.bel, fasm_name, val), file=f) + print("", file=f)
\ No newline at end of file diff --git a/generic/main.cc b/generic/main.cc index 08b0b348..c203f35c 100644 --- a/generic/main.cc +++ b/generic/main.cc @@ -49,7 +49,7 @@ po::options_description GenericCommandHandler::getArchOptions() return specific; } -void GenericCommandHandler::customBitstream(Context *ctx) { log_error("Here is when bitstream gets created"); } +void GenericCommandHandler::customBitstream(Context *ctx) {} std::unique_ptr<Context> GenericCommandHandler::createContext() { diff --git a/generic/pack.cc b/generic/pack.cc new file mode 100644 index 00000000..26ae9182 --- /dev/null +++ b/generic/pack.cc @@ -0,0 +1,293 @@ +/* + * nextpnr -- Next Generation Place and Route + * + * Copyright (C) 2018-19 David Shah <david@symbioticeda.com> + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +#include <algorithm> +#include <iterator> +#include <unordered_set> +#include "cells.h" +#include "design_utils.h" +#include "log.h" +#include "util.h" + +NEXTPNR_NAMESPACE_BEGIN + +// Pack LUTs and LUT-FF pairs +static void pack_lut_lutffs(Context *ctx) +{ + log_info("Packing LUT-FFs..\n"); + + std::unordered_set<IdString> packed_cells; + std::vector<std::unique_ptr<CellInfo>> new_cells; + for (auto cell : sorted(ctx->cells)) { + CellInfo *ci = cell.second; + if (ctx->verbose) + log_info("cell '%s' is of type '%s'\n", ci->name.c_str(ctx), ci->type.c_str(ctx)); + if (is_lut(ctx, ci)) { + std::unique_ptr<CellInfo> packed = + create_generic_cell(ctx, ctx->id("GENERIC_SLICE"), ci->name.str(ctx) + "_LC"); + std::copy(ci->attrs.begin(), ci->attrs.end(), std::inserter(packed->attrs, packed->attrs.begin())); + packed_cells.insert(ci->name); + if (ctx->verbose) + log_info("packed cell %s into %s\n", ci->name.c_str(ctx), packed->name.c_str(ctx)); + // See if we can pack into a DFF + // TODO: LUT cascade + NetInfo *o = ci->ports.at(ctx->id("Q")).net; + CellInfo *dff = net_only_drives(ctx, o, is_ff, ctx->id("D"), true); + auto lut_bel = ci->attrs.find(ctx->id("BEL")); + bool packed_dff = false; + if (dff) { + if (ctx->verbose) + log_info("found attached dff %s\n", dff->name.c_str(ctx)); + auto dff_bel = dff->attrs.find(ctx->id("BEL")); + if (lut_bel != ci->attrs.end() && dff_bel != dff->attrs.end() && lut_bel->second != dff_bel->second) { + // Locations don't match, can't pack + } else { + lut_to_lc(ctx, ci, packed.get(), false); + dff_to_lc(ctx, dff, packed.get(), false); + ctx->nets.erase(o->name); + if (dff_bel != dff->attrs.end()) + packed->attrs[ctx->id("BEL")] = dff_bel->second; + packed_cells.insert(dff->name); + if (ctx->verbose) + log_info("packed cell %s into %s\n", dff->name.c_str(ctx), packed->name.c_str(ctx)); + packed_dff = true; + } + } + if (!packed_dff) { + lut_to_lc(ctx, ci, packed.get(), true); + } + new_cells.push_back(std::move(packed)); + } + } + for (auto pcell : packed_cells) { + ctx->cells.erase(pcell); + } + for (auto &ncell : new_cells) { + ctx->cells[ncell->name] = std::move(ncell); + } +} + +// Pack FFs not packed as LUTFFs +static void pack_nonlut_ffs(Context *ctx) +{ + log_info("Packing non-LUT FFs..\n"); + + std::unordered_set<IdString> packed_cells; + std::vector<std::unique_ptr<CellInfo>> new_cells; + + for (auto cell : sorted(ctx->cells)) { + CellInfo *ci = cell.second; + if (is_ff(ctx, ci)) { + std::unique_ptr<CellInfo> packed = + create_generic_cell(ctx, ctx->id("GENERIC_SLICE"), ci->name.str(ctx) + "_DFFLC"); + std::copy(ci->attrs.begin(), ci->attrs.end(), std::inserter(packed->attrs, packed->attrs.begin())); + if (ctx->verbose) + log_info("packed cell %s into %s\n", ci->name.c_str(ctx), packed->name.c_str(ctx)); + packed_cells.insert(ci->name); + dff_to_lc(ctx, ci, packed.get(), true); + new_cells.push_back(std::move(packed)); + } + } + for (auto pcell : packed_cells) { + ctx->cells.erase(pcell); + } + for (auto &ncell : new_cells) { + ctx->cells[ncell->name] = std::move(ncell); + } +} + +static bool net_is_constant(const Context *ctx, NetInfo *net, bool &value) +{ + if (net == nullptr) + return false; + if (net->name == ctx->id("$PACKER_GND_NET") || net->name == ctx->id("$PACKER_VCC_NET")) { + value = (net->name == ctx->id("$PACKER_VCC_NET")); + return true; + } else { + return false; + } +} + +// Merge a net into a constant net +static void set_net_constant(const Context *ctx, NetInfo *orig, NetInfo *constnet, bool constval) +{ + orig->driver.cell = nullptr; + for (auto user : orig->users) { + if (user.cell != nullptr) { + CellInfo *uc = user.cell; + if (ctx->verbose) + log_info("%s user %s\n", orig->name.c_str(ctx), uc->name.c_str(ctx)); + if ((is_lut(ctx, uc) || is_lc(ctx, uc)) && (user.port.str(ctx).at(0) == 'I') && !constval) { + uc->ports[user.port].net = nullptr; + } else { + uc->ports[user.port].net = constnet; + constnet->users.push_back(user); + } + } + } + orig->users.clear(); +} + +// Pack constants (simple implementation) +static void pack_constants(Context *ctx) +{ + log_info("Packing constants..\n"); + + std::unique_ptr<CellInfo> gnd_cell = create_generic_cell(ctx, ctx->id("GENERIC_SLICE"), "$PACKER_GND"); + gnd_cell->params[ctx->id("INIT")] = "0"; + std::unique_ptr<NetInfo> gnd_net = std::unique_ptr<NetInfo>(new NetInfo); + gnd_net->name = ctx->id("$PACKER_GND_NET"); + gnd_net->driver.cell = gnd_cell.get(); + gnd_net->driver.port = ctx->id("Q"); + gnd_cell->ports.at(ctx->id("Q")).net = gnd_net.get(); + + std::unique_ptr<CellInfo> vcc_cell = create_generic_cell(ctx, ctx->id("GENERIC_SLICE"), "$PACKER_VCC"); + vcc_cell->params[ctx->id("INIT")] = "1"; + std::unique_ptr<NetInfo> vcc_net = std::unique_ptr<NetInfo>(new NetInfo); + vcc_net->name = ctx->id("$PACKER_VCC_NET"); + vcc_net->driver.cell = vcc_cell.get(); + vcc_net->driver.port = ctx->id("Q"); + vcc_cell->ports.at(ctx->id("Q")).net = vcc_net.get(); + + std::vector<IdString> dead_nets; + + bool gnd_used = false; + + for (auto net : sorted(ctx->nets)) { + NetInfo *ni = net.second; + if (ni->driver.cell != nullptr && ni->driver.cell->type == ctx->id("GND")) { + IdString drv_cell = ni->driver.cell->name; + set_net_constant(ctx, ni, gnd_net.get(), false); + gnd_used = true; + dead_nets.push_back(net.first); + ctx->cells.erase(drv_cell); + } else if (ni->driver.cell != nullptr && ni->driver.cell->type == ctx->id("VCC")) { + IdString drv_cell = ni->driver.cell->name; + set_net_constant(ctx, ni, vcc_net.get(), true); + dead_nets.push_back(net.first); + ctx->cells.erase(drv_cell); + } + } + + if (gnd_used) { + ctx->cells[gnd_cell->name] = std::move(gnd_cell); + ctx->nets[gnd_net->name] = std::move(gnd_net); + } + // Vcc cell always inserted for now, as it may be needed during carry legalisation (TODO: trim later if actually + // never used?) + ctx->cells[vcc_cell->name] = std::move(vcc_cell); + ctx->nets[vcc_net->name] = std::move(vcc_net); + + for (auto dn : dead_nets) { + ctx->nets.erase(dn); + } +} + +static bool is_nextpnr_iob(Context *ctx, CellInfo *cell) +{ + return cell->type == ctx->id("$nextpnr_ibuf") || cell->type == ctx->id("$nextpnr_obuf") || + cell->type == ctx->id("$nextpnr_iobuf"); +} + +static bool is_generic_iob(const Context *ctx, const CellInfo *cell) { return cell->type == ctx->id("GENERIC_IOB"); } + +// Pack IO buffers +static void pack_io(Context *ctx) +{ + std::unordered_set<IdString> packed_cells; + std::unordered_set<IdString> delete_nets; + + std::vector<std::unique_ptr<CellInfo>> new_cells; + log_info("Packing IOs..\n"); + + for (auto cell : sorted(ctx->cells)) { + CellInfo *ci = cell.second; + if (is_nextpnr_iob(ctx, ci)) { + CellInfo *iob = nullptr; + if (ci->type == ctx->id("$nextpnr_ibuf") || ci->type == ctx->id("$nextpnr_iobuf")) { + iob = net_only_drives(ctx, ci->ports.at(ctx->id("O")).net, is_generic_iob, ctx->id("PAD"), true, ci); + + } else if (ci->type == ctx->id("$nextpnr_obuf")) { + NetInfo *net = ci->ports.at(ctx->id("I")).net; + iob = net_only_drives(ctx, net, is_generic_iob, ctx->id("PAD"), true, ci); + } + if (iob != nullptr) { + // Trivial case, GENERIC_IOB used. Just destroy the net and the + // iobuf + log_info("%s feeds GENERIC_IOB %s, removing %s %s.\n", ci->name.c_str(ctx), iob->name.c_str(ctx), + ci->type.c_str(ctx), ci->name.c_str(ctx)); + NetInfo *net = iob->ports.at(ctx->id("PAD")).net; + if (((ci->type == ctx->id("$nextpnr_ibuf") || ci->type == ctx->id("$nextpnr_iobuf")) && + net->users.size() > 1) || + (ci->type == ctx->id("$nextpnr_obuf") && (net->users.size() > 2 || net->driver.cell != nullptr))) + log_error("PAD of %s '%s' connected to more than a single top level IO.\n", iob->type.c_str(ctx), + iob->name.c_str(ctx)); + + if (net != nullptr) { + delete_nets.insert(net->name); + iob->ports.at(ctx->id("PAD")).net = nullptr; + } + if (ci->type == ctx->id("$nextpnr_iobuf")) { + NetInfo *net2 = ci->ports.at(ctx->id("I")).net; + if (net2 != nullptr) { + delete_nets.insert(net2->name); + } + } + } else { + // Create a GENERIC_IOB buffer + std::unique_ptr<CellInfo> ice_cell = + create_generic_cell(ctx, ctx->id("GENERIC_IOB"), ci->name.str(ctx) + "$iob"); + nxio_to_iob(ctx, ci, ice_cell.get(), packed_cells); + new_cells.push_back(std::move(ice_cell)); + iob = new_cells.back().get(); + } + packed_cells.insert(ci->name); + std::copy(ci->attrs.begin(), ci->attrs.end(), std::inserter(iob->attrs, iob->attrs.begin())); + } + } + for (auto pcell : packed_cells) { + ctx->cells.erase(pcell); + } + for (auto dnet : delete_nets) { + ctx->nets.erase(dnet); + } + for (auto &ncell : new_cells) { + ctx->cells[ncell->name] = std::move(ncell); + } +} + +// Main pack function +bool Arch::pack() +{ + Context *ctx = getCtx(); + try { + log_break(); + pack_constants(ctx); + pack_io(ctx); + pack_lut_lutffs(ctx); + pack_nonlut_ffs(ctx); + ctx->assignArchInfo(); + log_info("Checksum: 0x%08x\n", ctx->checksum()); + return true; + } catch (log_execution_error_exception) { + return false; + } +} + +NEXTPNR_NAMESPACE_END diff --git a/generic/synth/cells_map.v b/generic/synth/cells_map.v new file mode 100644 index 00000000..a6027534 --- /dev/null +++ b/generic/synth/cells_map.v @@ -0,0 +1,10 @@ +module \$lut (A, Y); + parameter WIDTH = 0; + parameter LUT = 0; + input [WIDTH-1:0] A; + output Y; + + LUT #(.K(`LUT_K), .INIT(LUT)) _TECHMAP_REPLACE_ (.I(A), .Q(Y)); +endmodule + +module \$_DFF_P_ (input D, C, output Q); DFF _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C)); endmodule diff --git a/generic/synth/prims.v b/generic/synth/prims.v new file mode 100644 index 00000000..95fcfac7 --- /dev/null +++ b/generic/synth/prims.v @@ -0,0 +1,59 @@ +// LUT and DFF are combined to a GENERIC_SLICE + +module LUT #( + parameter K = 4, + parameter [2**K-1:0] INIT = 0, +) ( + input [K-1:0] I, + output Q +); + assign Q = INIT[I]; +endmodule + +module DFF ( + input CLK, D, + output reg Q +); + always @(posedge CLK) + Q <= D; +endmodule + +module GENERIC_SLICE #( + parameter K = 4, + parameter [2**K-1:0] INIT = 0, + parameter FF_USED = 1'b0 +) ( + input CLK, + input [K-1:0] I, + output Q +); + + wire lut_q; + LUT #(.K(K), .INIT(INIT)) lut_i(.I(I), .Q(lut_q)); + + generate if (FF_USED) + DFF dff_i(.CLK(CLK), .D(lut_q), .Q(Q)); + else + assign Q = lut_q; + endgenerate +endmodule + +module GENERIC_IOB #( + parameter INPUT_USED = 1'b0, + parameter OUTPUT_USED = 1'b0, + parameter ENABLE_USED = 1'b0 +) ( + inout PAD, + input I, EN, + output O +); + generate if (OUTPUT_USED && ENABLE_USED) + assign PAD = EN ? I : 1'bz; + else if (OUTPUT_USED) + assign PAD = I; + endgenerate + + generate if (INPUT_USED) + assign O = PAD; + endgenerate +endmodule
\ No newline at end of file diff --git a/generic/synth/synth_generic.tcl b/generic/synth/synth_generic.tcl new file mode 100644 index 00000000..e5d88e0d --- /dev/null +++ b/generic/synth/synth_generic.tcl @@ -0,0 +1,24 @@ +# Usage +# tcl synth_generic.tcl {K} {out.json} + +set LUT_K 4 +if {$argc > 0} { set LUT_K [lindex $argv 0] } +yosys read_verilog -lib [file dirname [file normalize $argv0]]/prims.v +yosys hierarchy -check +yosys proc +yosys flatten +yosys tribuf -logic +yosys deminout +yosys synth -run coarse +yosys memory_map +yosys opt -full +yosys techmap -map +/techmap.v +yosys opt -fast +yosys abc -lut $LUT_K -dress +yosys clean +yosys techmap -D LUT_K=$LUT_K -map [file dirname [file normalize $argv0]]/cells_map.v +yosys clean +yosys hierarchy -check +yosys stat + +if {$argc > 1} { yosys write_json [lindex $argv 1] } diff --git a/gui/application.cc b/gui/application.cc index 9229f1cd..0a82e40b 100644 --- a/gui/application.cc +++ b/gui/application.cc @@ -70,7 +70,7 @@ bool Application::notify(QObject *receiver, QEvent *event) bool retVal = true; try { retVal = QApplication::notify(receiver, event); - } catch (assertion_failure ex) { + } catch (const assertion_failure &ex) { QString msg; QTextStream out(&msg); out << ex.filename.c_str() << " at " << ex.line << "\n"; diff --git a/gui/base.qrc b/gui/base.qrc index 8f58f585..644b16a6 100644 --- a/gui/base.qrc +++ b/gui/base.qrc @@ -22,5 +22,6 @@ <file>resources/route.png</file> <file>resources/time_add.png</file> <file>resources/open_json.png</file> + <file>resources/py.png</file> </qresource> </RCC> diff --git a/gui/basewindow.cc b/gui/basewindow.cc index 49c2d8d5..346efb88 100644 --- a/gui/basewindow.cc +++ b/gui/basewindow.cc @@ -189,6 +189,12 @@ void BaseMainWindow::createMenusAndBars() actionRoute->setEnabled(false);
connect(actionRoute, &QAction::triggered, task, &TaskManager::route);
+ actionExecutePy = new QAction("Execute Python", this);
+ actionExecutePy->setIcon(QIcon(":/icons/resources/py.png"));
+ actionExecutePy->setStatusTip("Execute Python script");
+ actionExecutePy->setEnabled(true);
+ connect(actionExecutePy, &QAction::triggered, this, &BaseMainWindow::execute_python);
+
// Worker control toolbar actions
actionPlay = new QAction("Play", this);
actionPlay->setIcon(QIcon(":/icons/resources/control_play.png"));
@@ -249,6 +255,8 @@ void BaseMainWindow::createMenusAndBars() menuDesign->addAction(actionAssignBudget);
menuDesign->addAction(actionPlace);
menuDesign->addAction(actionRoute);
+ menuDesign->addSeparator();
+ menuDesign->addAction(actionExecutePy);
// Add Help menu actions
menuHelp->addAction(actionAbout);
@@ -268,6 +276,7 @@ void BaseMainWindow::createMenusAndBars() mainActionBar->addAction(actionAssignBudget);
mainActionBar->addAction(actionPlace);
mainActionBar->addAction(actionRoute);
+ mainActionBar->addAction(actionExecutePy);
// Add worker control toolbar
QToolBar *workerControlToolBar = new QToolBar("Worker");
@@ -412,6 +421,7 @@ void BaseMainWindow::disableActions() actionAssignBudget->setEnabled(false);
actionPlace->setEnabled(false);
actionRoute->setEnabled(false);
+ actionExecutePy->setEnabled(true);
actionPlay->setEnabled(false);
actionPause->setEnabled(false);
@@ -454,6 +464,14 @@ void BaseMainWindow::open_proj() }
}
+void BaseMainWindow::execute_python()
+{
+ QString fileName = QFileDialog::getOpenFileName(this, QString("Execute Python"), QString(), QString("*.py"));
+ if (!fileName.isEmpty()) {
+ console->execute_python(fileName.toStdString());
+ }
+}
+
void BaseMainWindow::notifyChangeContext() { Q_EMIT contextChanged(ctx.get()); }
void BaseMainWindow::save_proj()
{
diff --git a/gui/basewindow.h b/gui/basewindow.h index eb32033a..0b2d3fbc 100644 --- a/gui/basewindow.h +++ b/gui/basewindow.h @@ -78,6 +78,8 @@ class BaseMainWindow : public QMainWindow void budget();
void place();
+ void execute_python();
+
void pack_finished(bool status);
void budget_finish(bool status);
void place_finished(bool status);
@@ -122,6 +124,9 @@ class BaseMainWindow : public QMainWindow QAction *actionAssignBudget;
QAction *actionPlace;
QAction *actionRoute;
+
+ QAction *actionExecutePy;
+
QAction *actionPlay;
QAction *actionPause;
QAction *actionStop;
diff --git a/gui/designwidget.cc b/gui/designwidget.cc index 235dd2cb..1617340b 100644 --- a/gui/designwidget.cc +++ b/gui/designwidget.cc @@ -444,9 +444,9 @@ TreeModel::Model *DesignWidget::getTreeByElementType(ElementType type) return treeModel[1];
if (type == ElementType::PIP)
return treeModel[2];
- if (type == ElementType::NET)
- return treeModel[3];
if (type == ElementType::CELL)
+ return treeModel[3];
+ if (type == ElementType::NET)
return treeModel[4];
return nullptr;
}
@@ -460,9 +460,9 @@ int DesignWidget::getIndexByElementType(ElementType type) return 1;
if (type == ElementType::PIP)
return 2;
- if (type == ElementType::NET)
- return 3;
if (type == ElementType::CELL)
+ return 3;
+ if (type == ElementType::NET)
return 4;
if (type == ElementType::GROUP)
return 5;
@@ -706,8 +706,12 @@ void DesignWidget::onSelectionChanged(int num, const QItemSelection &, const QIt addProperty(topItem, QVariant::String, "Type", ctx->getPipType(pip).c_str(ctx));
addProperty(topItem, QVariant::Bool, "Available", ctx->checkPipAvail(pip));
addProperty(topItem, QVariant::String, "Bound Net", ctx->nameOf(ctx->getBoundPipNet(pip)), ElementType::NET);
- addProperty(topItem, QVariant::String, "Conflicting Wire",
- ctx->getWireName(ctx->getConflictingPipWire(pip)).c_str(ctx), ElementType::WIRE);
+ if (ctx->getConflictingPipWire(pip) != WireId()) {
+ addProperty(topItem, QVariant::String, "Conflicting Wire",
+ ctx->getWireName(ctx->getConflictingPipWire(pip)).c_str(ctx), ElementType::WIRE);
+ } else {
+ addProperty(topItem, QVariant::String, "Conflicting Wire", "", ElementType::NONE);
+ }
addProperty(topItem, QVariant::String, "Conflicting Net", ctx->nameOf(ctx->getConflictingPipNet(pip)),
ElementType::NET);
addProperty(topItem, QVariant::String, "Src Wire", ctx->getWireName(ctx->getPipSrcWire(pip)).c_str(ctx),
diff --git a/gui/fpgaviewwidget.cc b/gui/fpgaviewwidget.cc index e0a81486..f2929d6e 100644 --- a/gui/fpgaviewwidget.cc +++ b/gui/fpgaviewwidget.cc @@ -88,7 +88,7 @@ void FPGAViewWidget::newContext(Context *ctx) pokeRenderer(); } -QSize FPGAViewWidget::minimumSizeHint() const { return QSize(640, 480); } +QSize FPGAViewWidget::minimumSizeHint() const { return QSize(320, 200); } QSize FPGAViewWidget::sizeHint() const { return QSize(640, 480); } @@ -100,7 +100,7 @@ void FPGAViewWidget::initializeGL() initializeOpenGLFunctions(); QtImGui::initialize(this); glClearColor(colors_.background.red() / 255, colors_.background.green() / 255, colors_.background.blue() / 255, - 0.0); + 1.0); } float FPGAViewWidget::PickedElement::distance(Context *ctx, float wx, float wy) const @@ -630,12 +630,16 @@ void FPGAViewWidget::mousePressEvent(QMouseEvent *event) if (io.WantCaptureMouse) return; - if (event->buttons() & Qt::RightButton || event->buttons() & Qt::MidButton) { + bool shift = QApplication::keyboardModifiers().testFlag(Qt::ShiftModifier); + bool ctrl = QApplication::keyboardModifiers().testFlag(Qt::ControlModifier); + bool btn_right = event->buttons() & Qt::RightButton; + bool btn_mid = event->buttons() & Qt::MidButton; + bool btn_left = event->buttons() & Qt::LeftButton; + + if (btn_right || btn_mid || (btn_left && shift)) { lastDragPos_ = event->pos(); } - if (event->buttons() & Qt::LeftButton) { - bool ctrl = QApplication::keyboardModifiers().testFlag(Qt::ControlModifier); - + if (btn_left && !shift) { auto world = mouseToWorldCoordinates(event->x(), event->y()); auto closestOr = pickElement(world.x(), world.y()); if (!closestOr) { @@ -667,7 +671,12 @@ void FPGAViewWidget::mouseMoveEvent(QMouseEvent *event) if (io.WantCaptureMouse) return; - if (event->buttons() & Qt::RightButton || event->buttons() & Qt::MidButton) { + bool shift = QApplication::keyboardModifiers().testFlag(Qt::ShiftModifier); + bool btn_right = event->buttons() & Qt::RightButton; + bool btn_mid = event->buttons() & Qt::MidButton; + bool btn_left = event->buttons() & Qt::LeftButton; + + if (btn_right || btn_mid || (btn_left && shift)) { const int dx = event->x() - lastDragPos_.x(); const int dy = event->y() - lastDragPos_.y(); lastDragPos_ = event->pos(); diff --git a/gui/generic/mainwindow.cc b/gui/generic/mainwindow.cc index 12912cc9..54d1f2c8 100644 --- a/gui/generic/mainwindow.cc +++ b/gui/generic/mainwindow.cc @@ -19,6 +19,9 @@ #include "mainwindow.h"
+#include <QMessageBox>
+#include <cstdlib>
+
static void initMainResource() { Q_INIT_RESOURCE(nextpnr); }
NEXTPNR_NAMESPACE_BEGIN
@@ -26,14 +29,8 @@ NEXTPNR_NAMESPACE_BEGIN MainWindow::MainWindow(std::unique_ptr<Context> context, ArchArgs args, QWidget *parent)
: BaseMainWindow(std::move(context), args, parent)
{
- initMainResource();
-
- std::string title = "nextpnr-generic - [EMPTY]";
- setWindowTitle(title.c_str());
-
- connect(this, &BaseMainWindow::contextChanged, this, &MainWindow::newContext);
-
- createMenu();
+ QMessageBox::critical(0, "Error - FIXME", "No GUI support for nextpnr-generic");
+ std::exit(1);
}
MainWindow::~MainWindow() {}
diff --git a/gui/pyconsole.cc b/gui/pyconsole.cc index 0ee393ce..d015aea2 100644 --- a/gui/pyconsole.cc +++ b/gui/pyconsole.cc @@ -76,4 +76,21 @@ void PythonConsole::moveCursorToEnd() setTextCursor(cursor); } +void PythonConsole::execute_python(std::string filename) +{ + int errorCode = 0; + std::string res; + res = pyinterpreter_execute_file(filename.c_str(), &errorCode); + if (res.size()) { + if (errorCode) { + setTextColor(ERROR_COLOR); + } else { + setTextColor(OUTPUT_COLOR); + } + append(res.c_str()); + setTextColor(NORMAL_COLOR); + moveCursorToEnd(); + } +} + NEXTPNR_NAMESPACE_END diff --git a/gui/pyconsole.h b/gui/pyconsole.h index 9dbd3b95..977242f3 100644 --- a/gui/pyconsole.h +++ b/gui/pyconsole.h @@ -43,6 +43,7 @@ class PythonConsole : public QTextEdit, public ParseListener void displayString(QString text); void moveCursorToEnd(); virtual void parseEvent(const ParseMessage &message); + void execute_python(std::string filename); protected: static const QColor NORMAL_COLOR; diff --git a/gui/pythontab.cc b/gui/pythontab.cc index 80d731e9..c83f1ece 100644 --- a/gui/pythontab.cc +++ b/gui/pythontab.cc @@ -96,9 +96,10 @@ void PythonTab::newContext(Context *ctx) console->clear();
pyinterpreter_preinit();
- init_python("nextpnr", !initialized);
+ init_python("nextpnr", true);
pyinterpreter_initialize();
pyinterpreter_aquire();
+ init_python("nextpnr", false);
python_export_global("ctx", ctx);
pyinterpreter_release();
@@ -114,4 +115,6 @@ void PythonTab::clearBuffer() { console->clear(); } void PythonTab::info(std::string str) { console->displayString(str.c_str()); }
+void PythonTab::execute_python(std::string filename) { console->execute_python(filename); }
+
NEXTPNR_NAMESPACE_END
diff --git a/gui/pythontab.h b/gui/pythontab.h index 134874b6..860bf1c3 100644 --- a/gui/pythontab.h +++ b/gui/pythontab.h @@ -45,6 +45,7 @@ class PythonTab : public QWidget void newContext(Context *ctx);
void info(std::string str);
void clearBuffer();
+ void execute_python(std::string filename);
private:
PythonConsole *console;
diff --git a/gui/resources/py.png b/gui/resources/py.png Binary files differnew file mode 100644 index 00000000..9cc6e522 --- /dev/null +++ b/gui/resources/py.png diff --git a/gui/worker.cc b/gui/worker.cc index b009ecd3..900883d4 100644 --- a/gui/worker.cc +++ b/gui/worker.cc @@ -126,6 +126,7 @@ TaskManager::TaskManager() : toTerminate(false), toPause(false) TaskManager::~TaskManager() { + log_write_function = nullptr; if (workerThread.isRunning()) terminate_thread(); workerThread.quit(); diff --git a/ice40/arch.cc b/ice40/arch.cc index ada78020..d536ad35 100644 --- a/ice40/arch.cc +++ b/ice40/arch.cc @@ -19,15 +19,17 @@ */ #include <algorithm> +#include <boost/iostreams/device/mapped_file.hpp> #include <cmath> #include "cells.h" #include "gfx.h" #include "log.h" #include "nextpnr.h" #include "placer1.h" +#include "placer_heap.h" #include "router1.h" +#include "timing_opt.h" #include "util.h" - NEXTPNR_NAMESPACE_BEGIN // ----------------------------------------------------------------------- @@ -47,9 +49,39 @@ static const ChipInfoPOD *get_chip_info(const RelPtr<ChipInfoPOD> *ptr) { return void load_chipdb(); #endif +#if defined(EXTERNAL_CHIPDB_ROOT) +const char *chipdb_blob_384 = nullptr; +const char *chipdb_blob_1k = nullptr; +const char *chipdb_blob_5k = nullptr; +const char *chipdb_blob_u4k = nullptr; +const char *chipdb_blob_8k = nullptr; + +boost::iostreams::mapped_file_source blob_files[5]; + +const char *mmap_file(int index, const char *filename) +{ + try { + blob_files[index].open(filename); + if (!blob_files[index].is_open()) + log_error("Unable to read chipdb %s\n", filename); + return (const char *)blob_files[index].data(); + } catch (...) { + log_error("Unable to read chipdb %s\n", filename); + } +} + +void load_chipdb() +{ + chipdb_blob_384 = mmap_file(0, EXTERNAL_CHIPDB_ROOT "/ice40/chipdb-384.bin"); + chipdb_blob_1k = mmap_file(1, EXTERNAL_CHIPDB_ROOT "/ice40/chipdb-1k.bin"); + chipdb_blob_5k = mmap_file(2, EXTERNAL_CHIPDB_ROOT "/ice40/chipdb-5k.bin"); + chipdb_blob_u4k = mmap_file(3, EXTERNAL_CHIPDB_ROOT "/ice40/chipdb-u4k.bin"); + chipdb_blob_8k = mmap_file(4, EXTERNAL_CHIPDB_ROOT "/ice40/chipdb-8k.bin"); +} +#endif Arch::Arch(ArchArgs args) : args(args) { -#if defined(_MSC_VER) +#if defined(_MSC_VER) || defined(EXTERNAL_CHIPDB_ROOT) load_chipdb(); #endif @@ -70,6 +102,9 @@ Arch::Arch(ArchArgs args) : args(args) } else if (args.type == ArchArgs::UP5K) { fast_part = false; chip_info = get_chip_info(reinterpret_cast<const RelPtr<ChipInfoPOD> *>(chipdb_blob_5k)); + } else if (args.type == ArchArgs::U4K) { + fast_part = false; + chip_info = get_chip_info(reinterpret_cast<const RelPtr<ChipInfoPOD> *>(chipdb_blob_u4k)); } else if (args.type == ArchArgs::LP8K || args.type == ArchArgs::HX8K) { fast_part = args.type == ArchArgs::HX8K; chip_info = get_chip_info(reinterpret_cast<const RelPtr<ChipInfoPOD> *>(chipdb_blob_8k)); @@ -114,6 +149,8 @@ std::string Arch::getChipName() const return "Lattice HX1K"; } else if (args.type == ArchArgs::UP5K) { return "Lattice UP5K"; + } else if (args.type == ArchArgs::U4K) { + return "Lattice U4K"; } else if (args.type == ArchArgs::LP8K) { return "Lattice LP8K"; } else if (args.type == ArchArgs::HX8K) { @@ -136,6 +173,8 @@ IdString Arch::archArgsToId(ArchArgs args) const return id("hx1k"); if (args.type == ArchArgs::UP5K) return id("up5k"); + if (args.type == ArchArgs::U4K) + return id("u4k"); if (args.type == ArchArgs::LP8K) return id("lp8k"); if (args.type == ArchArgs::HX8K) @@ -593,26 +632,30 @@ std::vector<GroupId> Arch::getGroupGroups(GroupId group) const bool Arch::getBudgetOverride(const NetInfo *net_info, const PortRef &sink, delay_t &budget) const { const auto &driver = net_info->driver; - if (driver.port == id_COUT && sink.port == id_CIN) { - if (driver.cell->constr_abs_z && driver.cell->constr_z < 7) + if (driver.port == id_COUT) { + NPNR_ASSERT(sink.port == id_CIN || sink.port == id_I3); + NPNR_ASSERT(driver.cell->constr_abs_z); + bool cin = sink.port == id_CIN; + bool same_y = driver.cell->constr_z < 7; + if (cin && same_y) budget = 0; else { - NPNR_ASSERT(driver.cell->constr_z == 7); switch (args.type) { #ifndef ICE40_HX1K_ONLY case ArchArgs::HX8K: #endif case ArchArgs::HX1K: - budget = 190; + budget = cin ? 190 : (same_y ? 260 : 560); break; #ifndef ICE40_HX1K_ONLY case ArchArgs::LP384: case ArchArgs::LP1K: case ArchArgs::LP8K: - budget = 290; + budget = cin ? 290 : (same_y ? 380 : 670); break; case ArchArgs::UP5K: - budget = 560; + case ArchArgs::U4K: + budget = cin ? 560 : (same_y ? 660 : 1220); break; #endif default: @@ -626,7 +669,28 @@ bool Arch::getBudgetOverride(const NetInfo *net_info, const PortRef &sink, delay // ----------------------------------------------------------------------- -bool Arch::place() { return placer1(getCtx(), Placer1Cfg(getCtx())); } +bool Arch::place() +{ + std::string placer = str_or_default(settings, id("placer"), defaultPlacer); + if (placer == "heap") { + PlacerHeapCfg cfg(getCtx()); + cfg.ioBufTypes.insert(id_SB_IO); + if (!placer_heap(getCtx(), cfg)) + return false; + } else if (placer == "sa") { + if (!placer1(getCtx(), Placer1Cfg(getCtx()))) + return false; + } else { + log_error("iCE40 architecture does not support placer '%s'\n", placer.c_str()); + } + if (bool_or_default(settings, id("opt_timing"), false)) { + TimingOptCfg tocfg(getCtx()); + tocfg.cellTypes.insert(id_ICESTORM_LC); + return timing_opt(getCtx(), tocfg); + } else { + return true; + } +} bool Arch::route() { return router1(getCtx(), Router1Cfg(getCtx())); } @@ -855,6 +919,17 @@ std::vector<GraphicElement> Arch::getDecalGraphics(DecalId decal) const bool Arch::getCellDelay(const CellInfo *cell, IdString fromPort, IdString toPort, DelayInfo &delay) const { + if (cell->type == id_ICESTORM_LC && cell->lcInfo.dffEnable) { + if (toPort == id_O) + return false; + } else if (cell->type == id_ICESTORM_RAM || cell->type == id_ICESTORM_SPRAM) { + return false; + } + return getCellDelayInternal(cell, fromPort, toPort, delay); +} + +bool Arch::getCellDelayInternal(const CellInfo *cell, IdString fromPort, IdString toPort, DelayInfo &delay) const +{ for (int i = 0; i < chip_info->num_timing_cells; i++) { const auto &tc = chip_info->cell_timing[i]; if (tc.type == cell->type.index) { @@ -923,13 +998,37 @@ TimingPortClass Arch::getPortTimingClass(const CellInfo *cell, IdString port, in return TMG_REGISTER_INPUT; } } else if (cell->type == id_SB_IO) { - if (port == id_D_IN_0 || port == id_D_IN_1) + if (port == id_INPUT_CLK || port == id_OUTPUT_CLK) + return TMG_CLOCK_INPUT; + if (port == id_CLOCK_ENABLE) { + clockInfoCount = 2; + return TMG_REGISTER_INPUT; + } + if ((port == id_D_IN_0 && !(cell->ioInfo.pintype & 0x1)) || port == id_D_IN_1) { + clockInfoCount = 1; + return TMG_REGISTER_OUTPUT; + } else if (port == id_D_IN_0) { return TMG_STARTPOINT; - if (port == id_D_OUT_0 || port == id_D_OUT_1 || port == id_OUTPUT_ENABLE) - return TMG_ENDPOINT; + } + if (port == id_D_OUT_0 || port == id_D_OUT_1) { + if ((cell->ioInfo.pintype & 0xC) == 0x8) { + return TMG_ENDPOINT; + } else { + clockInfoCount = 1; + return TMG_REGISTER_INPUT; + } + } + if (port == id_OUTPUT_ENABLE) { + if ((cell->ioInfo.pintype & 0x18) == 0x18) { + return TMG_REGISTER_INPUT; + } else { + return TMG_ENDPOINT; + } + } + return TMG_IGNORE; } else if (cell->type == id_ICESTORM_PLL) { - if (port == id_PLLOUT_A || port == id_PLLOUT_B) + if (port == id_PLLOUT_A || port == id_PLLOUT_B || port == id_PLLOUT_A_GLOBAL || port == id_PLLOUT_B_GLOBAL) return TMG_GEN_CLOCK; return TMG_IGNORE; } else if (cell->type == id_ICESTORM_LFOSC) { @@ -942,7 +1041,7 @@ TimingPortClass Arch::getPortTimingClass(const CellInfo *cell, IdString port, in return TMG_IGNORE; } else if (cell->type == id_SB_GB) { if (port == id_GLOBAL_BUFFER_OUTPUT) - return TMG_COMB_OUTPUT; + return cell->gbInfo.forPadIn ? TMG_GEN_CLOCK : TMG_COMB_OUTPUT; return TMG_COMB_INPUT; } else if (cell->type == id_SB_WARMBOOT) { return TMG_ENDPOINT; @@ -954,6 +1053,16 @@ TimingPortClass Arch::getPortTimingClass(const CellInfo *cell, IdString port, in if (port == id_CLK || port == id_CLOCK) return TMG_CLOCK_INPUT; return TMG_IGNORE; + } else if (cell->type == id_SB_I2C || cell->type == id_SB_SPI) { + if (port == this->id("SBCLKI")) + return TMG_CLOCK_INPUT; + + clockInfoCount = 1; + + if (cell->ports.at(port).type == PORT_OUT) + return TMG_REGISTER_OUTPUT; + else + return TMG_REGISTER_INPUT; } log_error("cell type '%s' is unsupported (instantiated as '%s')\n", cell->type.c_str(this), cell->name.c_str(this)); } @@ -965,10 +1074,23 @@ TimingClockingInfo Arch::getPortClockingInfo(const CellInfo *cell, IdString port info.clock_port = id_CLK; info.edge = cell->lcInfo.negClk ? FALLING_EDGE : RISING_EDGE; if (port == id_O) { - bool has_clktoq = getCellDelay(cell, id_CLK, id_O, info.clockToQ); + bool has_clktoq = getCellDelayInternal(cell, id_CLK, id_O, info.clockToQ); NPNR_ASSERT(has_clktoq); } else { - info.setup.delay = 100; + if (port == id_I0 || port == id_I1 || port == id_I2 || port == id_I3) { + DelayInfo dlut; + bool has_ld = getCellDelayInternal(cell, port, id_O, dlut); + NPNR_ASSERT(has_ld); + if (args.type == ArchArgs::LP1K || args.type == ArchArgs::LP8K || args.type == ArchArgs::LP384) { + info.setup.delay = 30 + dlut.delay; + } else if (args.type == ArchArgs::UP5K || args.type == ArchArgs::U4K) { // XXX verify u4k + info.setup.delay = dlut.delay - 50; + } else { + info.setup.delay = 20 + dlut.delay; + } + } else { + info.setup.delay = 100; + } info.hold.delay = 0; } } else if (cell->type == id_ICESTORM_RAM) { @@ -980,23 +1102,69 @@ TimingClockingInfo Arch::getPortClockingInfo(const CellInfo *cell, IdString port info.edge = bool_or_default(cell->params, id("NEG_CLK_W")) ? FALLING_EDGE : RISING_EDGE; } if (cell->ports.at(port).type == PORT_OUT) { - bool has_clktoq = getCellDelay(cell, info.clock_port, port, info.clockToQ); + bool has_clktoq = getCellDelayInternal(cell, info.clock_port, port, info.clockToQ); NPNR_ASSERT(has_clktoq); } else { info.setup.delay = 100; info.hold.delay = 0; } + } else if (cell->type == id_SB_IO) { + delay_t io_setup = 80, io_clktoq = 140; + if (args.type == ArchArgs::LP1K || args.type == ArchArgs::LP8K || args.type == ArchArgs::LP384) { + io_setup = 115; + io_clktoq = 210; + } else if (args.type == ArchArgs::UP5K || args.type == ArchArgs::U4K) { + io_setup = 205; + io_clktoq = 1005; + } + if (port == id_CLOCK_ENABLE) { + info.clock_port = (index == 1) ? id_OUTPUT_CLK : id_INPUT_CLK; + info.edge = cell->ioInfo.negtrig ? FALLING_EDGE : RISING_EDGE; + info.setup.delay = io_setup; + info.hold.delay = 0; + } else if (port == id_D_OUT_0 || port == id_OUTPUT_ENABLE) { + info.clock_port = id_OUTPUT_CLK; + info.edge = cell->ioInfo.negtrig ? FALLING_EDGE : RISING_EDGE; + info.setup.delay = io_setup; + info.hold.delay = 0; + } else if (port == id_D_OUT_1) { + info.clock_port = id_OUTPUT_CLK; + info.edge = cell->ioInfo.negtrig ? RISING_EDGE : FALLING_EDGE; + info.setup.delay = io_setup; + info.hold.delay = 0; + } else if (port == id_D_IN_0) { + info.clock_port = id_INPUT_CLK; + info.edge = cell->ioInfo.negtrig ? FALLING_EDGE : RISING_EDGE; + info.clockToQ.delay = io_clktoq; + } else if (port == id_D_IN_1) { + info.clock_port = id_INPUT_CLK; + info.edge = cell->ioInfo.negtrig ? RISING_EDGE : FALLING_EDGE; + info.clockToQ.delay = io_clktoq; + } else { + NPNR_ASSERT_FALSE("no clock data for IO cell port"); + } } else if (cell->type == id_ICESTORM_DSP || cell->type == id_ICESTORM_SPRAM) { info.clock_port = cell->type == id_ICESTORM_SPRAM ? id_CLOCK : id_CLK; info.edge = RISING_EDGE; if (cell->ports.at(port).type == PORT_OUT) { - bool has_clktoq = getCellDelay(cell, info.clock_port, port, info.clockToQ); + bool has_clktoq = getCellDelayInternal(cell, info.clock_port, port, info.clockToQ); if (!has_clktoq) info.clockToQ.delay = 100; } else { info.setup.delay = 100; info.hold.delay = 0; } + } else if (cell->type == id_SB_I2C || cell->type == id_SB_SPI) { + info.clock_port = this->id("SBCLKI"); + info.edge = RISING_EDGE; + if (cell->ports.at(port).type == PORT_OUT) { + /* Dummy number */ + info.clockToQ.delay = 1500; + } else { + /* Dummy number */ + info.setup.delay = 1500; + info.hold.delay = 0; + } } else { NPNR_ASSERT_FALSE("unhandled cell type in getPortClockingInfo"); } @@ -1053,9 +1221,20 @@ void Arch::assignCellInfo(CellInfo *cell) } else if (cell->type == id_SB_IO) { cell->ioInfo.lvds = str_or_default(cell->params, id_IO_STANDARD, "SB_LVCMOS") == "SB_LVDS_INPUT"; cell->ioInfo.global = bool_or_default(cell->attrs, this->id("GLOBAL")); + cell->ioInfo.pintype = int_or_default(cell->params, this->id("PIN_TYPE")); + cell->ioInfo.negtrig = bool_or_default(cell->params, this->id("NEG_TRIGGER")); + } else if (cell->type == id_SB_GB) { cell->gbInfo.forPadIn = bool_or_default(cell->attrs, this->id("FOR_PAD_IN")); } } +const std::string Arch::defaultPlacer = "sa"; + +const std::vector<std::string> Arch::availablePlacers = {"sa", +#ifdef WITH_HEAP + "heap" +#endif +}; + NEXTPNR_NAMESPACE_END diff --git a/ice40/arch.h b/ice40/arch.h index 10255dbe..ea29f4f1 100644 --- a/ice40/arch.h +++ b/ice40/arch.h @@ -244,15 +244,17 @@ NPNR_PACKED_STRUCT(struct ChipInfoPOD { RelPtr<RelPtr<char>> tile_wire_names; }); -#if defined(_MSC_VER) +#if defined(_MSC_VER) || defined(EXTERNAL_CHIPDB_ROOT) extern const char *chipdb_blob_384; extern const char *chipdb_blob_1k; extern const char *chipdb_blob_5k; +extern const char *chipdb_blob_u4k; extern const char *chipdb_blob_8k; #else extern const char chipdb_blob_384[]; extern const char chipdb_blob_1k[]; extern const char chipdb_blob_5k[]; +extern const char chipdb_blob_u4k[]; extern const char chipdb_blob_8k[]; #endif @@ -400,7 +402,8 @@ struct ArchArgs LP8K, HX1K, HX8K, - UP5K + UP5K, + U4K } type = NONE; std::string package; }; @@ -841,8 +844,11 @@ struct Arch : BaseCtx // ------------------------------------------------- // Get the delay through a cell from one port to another, returning false - // if no path exists + // if no path exists. This only considers combinational delays, as required by the Arch API bool getCellDelay(const CellInfo *cell, IdString fromPort, IdString toPort, DelayInfo &delay) const; + // getCellDelayInternal is similar to the above, but without false path checks and including clock to out delays + // for internal arch use only + bool getCellDelayInternal(const CellInfo *cell, IdString fromPort, IdString toPort, DelayInfo &delay) const; // Get the port class, also setting clockInfoCount to the number of TimingClockingInfos associated with a port TimingPortClass getPortTimingClass(const CellInfo *cell, IdString port, int &clockInfoCount) const; // Get the TimingClockingInfo of a port @@ -891,6 +897,9 @@ struct Arch : BaseCtx IdString glb_net = getWireName(getBelPinWire(bel, id_GLOBAL_BUFFER_OUTPUT)); return std::stoi(std::string("") + glb_net.str(this).back()); } + + static const std::string defaultPlacer; + static const std::vector<std::string> availablePlacers; }; void ice40DelayFuzzerMain(Context *ctx); diff --git a/ice40/arch_place.cc b/ice40/arch_place.cc index 90bb62b9..ede8d47f 100644 --- a/ice40/arch_place.cc +++ b/ice40/arch_place.cc @@ -91,6 +91,18 @@ bool Arch::isBelLocationValid(BelId bel) const } } +static inline bool _io_pintype_need_clk_in(unsigned pin_type) { return (pin_type & 0x01) == 0x00; } + +static inline bool _io_pintype_need_clk_out(unsigned pin_type) +{ + return ((pin_type & 0x30) == 0x30) || ((pin_type & 0x3c) && ((pin_type & 0x0c) != 0x08)); +} + +static inline bool _io_pintype_need_clk_en(unsigned pin_type) +{ + return _io_pintype_need_clk_in(pin_type) || _io_pintype_need_clk_out(pin_type); +} + bool Arch::isValidBelForCell(CellInfo *cell, BelId bel) const { if (cell->type == id_ICESTORM_LC) { @@ -157,6 +169,30 @@ bool Arch::isValidBelForCell(CellInfo *cell, BelId bel) const CellInfo *compCell = getBoundBelCell(compBel); if (compCell && compCell->ioInfo.lvds) return false; + + // Check for conflicts on shared nets + // - CLOCK_ENABLE + // - OUTPUT_CLK + // - INPUT_CLK + if (compCell) { + bool use[6] = { + _io_pintype_need_clk_in(cell->ioInfo.pintype), + _io_pintype_need_clk_in(compCell->ioInfo.pintype), + _io_pintype_need_clk_out(cell->ioInfo.pintype), + _io_pintype_need_clk_out(compCell->ioInfo.pintype), + _io_pintype_need_clk_en(cell->ioInfo.pintype), + _io_pintype_need_clk_en(compCell->ioInfo.pintype), + }; + NetInfo *nets[] = { + cell->ports[id_INPUT_CLK].net, compCell->ports[id_INPUT_CLK].net, + cell->ports[id_OUTPUT_CLK].net, compCell->ports[id_OUTPUT_CLK].net, + cell->ports[id_CLOCK_ENABLE].net, compCell->ports[id_CLOCK_ENABLE].net, + }; + + for (int i = 0; i < 6; i++) + if (use[i] && (nets[i] != nets[i ^ 1]) && (use[i ^ 1] || (nets[i ^ 1] != nullptr))) + return false; + } } return getBelPackagePin(bel) != ""; diff --git a/ice40/arch_pybindings.cc b/ice40/arch_pybindings.cc index 3fafb1f6..bc0bfb84 100644 --- a/ice40/arch_pybindings.cc +++ b/ice40/arch_pybindings.cc @@ -39,6 +39,7 @@ void arch_wrap_python() .value("HX1K", ArchArgs::HX1K) .value("HX8K", ArchArgs::HX8K) .value("UP5K", ArchArgs::UP5K) + .value("U4K", ArchArgs::U4K) .export_values(); class_<BelId>("BelId").def_readwrite("index", &BelId::index); @@ -143,6 +144,13 @@ void arch_wrap_python() fn_wrapper_2a_v<Context, decltype(&Context::addClock), &Context::addClock, conv_from_str<IdString>, pass_through<float>>::def_wrap(ctx_cls, "addClock"); + fn_wrapper_5a_v<Context, decltype(&Context::createRectangularRegion), &Context::createRectangularRegion, + conv_from_str<IdString>, pass_through<int>, pass_through<int>, pass_through<int>, + pass_through<int>>::def_wrap(ctx_cls, "createRectangularRegion"); + fn_wrapper_2a_v<Context, decltype(&Context::addBelToRegion), &Context::addBelToRegion, conv_from_str<IdString>, + conv_from_str<BelId>>::def_wrap(ctx_cls, "addBelToRegion"); + fn_wrapper_2a_v<Context, decltype(&Context::constrainCellToRegion), &Context::constrainCellToRegion, + conv_from_str<IdString>, conv_from_str<IdString>>::def_wrap(ctx_cls, "constrainCellToRegion"); WRAP_RANGE(Bel, conv_to_str<BelId>); WRAP_RANGE(Wire, conv_to_str<WireId>); diff --git a/ice40/archdefs.h b/ice40/archdefs.h index 2bffe667..956fcb4c 100644 --- a/ice40/archdefs.h +++ b/ice40/archdefs.h @@ -151,6 +151,8 @@ struct ArchCellInfo { bool lvds; bool global; + bool negtrig; + int pintype; // TODO: clk packing checks... } ioInfo; struct diff --git a/ice40/bitstream.cc b/ice40/bitstream.cc index 87d77b9d..9b85dff5 100644 --- a/ice40/bitstream.cc +++ b/ice40/bitstream.cc @@ -156,7 +156,9 @@ void configure_extra_cell(chipconfig_t &config, const Context *ctx, CellInfo *ce // Lattice's weird string style params, not sure if // prefixes other than 0b should be supported, only 0b features in docs std::string raw = get_param_str_or_def(cell, ctx->id(p.first), "0b0"); - assert(raw.substr(0, 2) == "0b"); + if (raw.substr(0, 2) != "0b") + log_error("expected configuration string starting with '0b' for parameter '%s' on cell '%s'\n", + p.first.c_str(), cell->name.c_str(ctx)); raw = raw.substr(2); value.resize(raw.length()); for (int i = 0; i < (int)raw.length(); i++) { @@ -168,7 +170,13 @@ void configure_extra_cell(chipconfig_t &config, const Context *ctx, CellInfo *ce } } } else { - int ival = get_param_or_def(cell, ctx->id(p.first), 0); + int ival; + try { + ival = get_param_or_def(cell, ctx->id(p.first), 0); + } catch (std::invalid_argument &e) { + log_error("expected numeric value for parameter '%s' on cell '%s'\n", p.first.c_str(), + cell->name.c_str(ctx)); + } for (int i = 0; i < p.second; i++) value.push_back((ival >> i) & 0x1); @@ -289,6 +297,9 @@ void write_asc(const Context *ctx, std::ostream &out) case ArchArgs::UP5K: out << ".device 5k" << std::endl; break; + case ArchArgs::U4K: + out << ".device u4k" << std::endl; + break; default: NPNR_ASSERT_FALSE("unsupported device type\n"); } @@ -519,10 +530,23 @@ void write_asc(const Context *ctx, std::ostream &out) } if (ctx->args.type == ArchArgs::UP5K) { + std::string pullup_resistor = "100K"; + if (cell.second->attrs.count(ctx->id("PULLUP_RESISTOR"))) + pullup_resistor = cell.second->attrs.at(ctx->id("PULLUP_RESISTOR")); + NPNR_ASSERT(pullup_resistor == "100K" || pullup_resistor == "10K" || pullup_resistor == "6P8K" || + pullup_resistor == "3P3K"); if (iez == 0) { - set_config(ti, config.at(iey).at(iex), "IoCtrl.cf_bit_39", !pullup); + set_config(ti, config.at(iey).at(iex), "IoCtrl.cf_bit_39", + (!pullup) || (pullup_resistor != "100K")); + set_config(ti, config.at(iey).at(iex), "IoCtrl.cf_bit_36", pullup && pullup_resistor == "3P3K"); + set_config(ti, config.at(iey).at(iex), "IoCtrl.cf_bit_37", pullup && pullup_resistor == "6P8K"); + set_config(ti, config.at(iey).at(iex), "IoCtrl.cf_bit_38", pullup && pullup_resistor == "10K"); } else if (iez == 1) { - set_config(ti, config.at(iey).at(iex), "IoCtrl.cf_bit_35", !pullup); + set_config(ti, config.at(iey).at(iex), "IoCtrl.cf_bit_35", + (!pullup) || (pullup_resistor != "100K")); + set_config(ti, config.at(iey).at(iex), "IoCtrl.cf_bit_32", pullup && pullup_resistor == "3P3K"); + set_config(ti, config.at(iey).at(iex), "IoCtrl.cf_bit_33", pullup && pullup_resistor == "6P8K"); + set_config(ti, config.at(iey).at(iex), "IoCtrl.cf_bit_34", pullup && pullup_resistor == "10K"); } } } else { @@ -592,8 +616,30 @@ void write_asc(const Context *ctx, std::ostream &out) configure_extra_cell(config, ctx, cell.second.get(), rgba_params, true, std::string("IpConfig.")); set_ec_cbit(config, ctx, get_ec_config(ctx->chip_info, cell.second->bel), "RGBA_DRV_EN", true, "IpConfig."); } else if (cell.second->type == ctx->id("SB_WARMBOOT") || cell.second->type == ctx->id("ICESTORM_LFOSC") || - cell.second->type == ctx->id("SB_LEDDA_IP") ) { + cell.second->type == ctx->id("SB_LEDDA_IP")) { // No config needed + } else if (cell.second->type == ctx->id("SB_I2C")) { + bool sda_in_dly = !cell.second->attrs.count(ctx->id("SDA_INPUT_DELAYED")) || + std::stoi(cell.second->attrs[ctx->id("SDA_INPUT_DELAYED")]); + bool sda_out_dly = !cell.second->attrs.count(ctx->id("SDA_OUTPUT_DELAYED")) || + std::stoi(cell.second->attrs[ctx->id("SDA_OUTPUT_DELAYED")]); + set_ec_cbit(config, ctx, get_ec_config(ctx->chip_info, cell.second->bel), "SDA_INPUT_DELAYED", sda_in_dly, + "IpConfig."); + set_ec_cbit(config, ctx, get_ec_config(ctx->chip_info, cell.second->bel), "SDA_OUTPUT_DELAYED", sda_out_dly, + "IpConfig."); + set_ec_cbit(config, ctx, get_ec_config(ctx->chip_info, cell.second->bel), "I2C_ENABLE_0", true, + "IpConfig."); + set_ec_cbit(config, ctx, get_ec_config(ctx->chip_info, cell.second->bel), "I2C_ENABLE_1", true, + "IpConfig."); + } else if (cell.second->type == ctx->id("SB_SPI")) { + set_ec_cbit(config, ctx, get_ec_config(ctx->chip_info, cell.second->bel), "SPI_ENABLE_0", true, + "IpConfig."); + set_ec_cbit(config, ctx, get_ec_config(ctx->chip_info, cell.second->bel), "SPI_ENABLE_1", true, + "IpConfig."); + set_ec_cbit(config, ctx, get_ec_config(ctx->chip_info, cell.second->bel), "SPI_ENABLE_2", true, + "IpConfig."); + set_ec_cbit(config, ctx, get_ec_config(ctx->chip_info, cell.second->bel), "SPI_ENABLE_3", true, + "IpConfig."); } else if (cell.second->type == ctx->id("ICESTORM_SPRAM")) { const BelInfoPOD &beli = ci.bel_data[bel.index]; int x = beli.x, y = beli.y, z = beli.z; @@ -639,7 +685,9 @@ void write_asc(const Context *ctx, std::ostream &out) {"B_SIGNED", 1}}; configure_extra_cell(config, ctx, cell.second.get(), mac16_params, false, std::string("IpConfig.")); } else if (cell.second->type == ctx->id("ICESTORM_HFOSC")) { - const std::vector<std::pair<std::string, int>> hfosc_params = {{"CLKHF_DIV", 2}, {"TRIM_EN", 1}}; + std::vector<std::pair<std::string, int>> hfosc_params = {{"CLKHF_DIV", 2}}; + if (ctx->args.type != ArchArgs::U4K) + hfosc_params.push_back(std::pair<std::string, int>("TRIM_EN", 1)); configure_extra_cell(config, ctx, cell.second.get(), hfosc_params, true, std::string("IpConfig.")); } else if (cell.second->type == ctx->id("ICESTORM_PLL")) { @@ -732,6 +780,8 @@ void write_asc(const Context *ctx, std::ostream &out) setColBufCtrl = (y == 8 || y == 9 || y == 24 || y == 25); } else if (ctx->args.type == ArchArgs::UP5K) { setColBufCtrl = (y == 4 || y == 5 || y == 14 || y == 15 || y == 26 || y == 27); + } else if (ctx->args.type == ArchArgs::U4K) { + setColBufCtrl = (y == 4 || y == 5 || y == 16 || y == 17); } else if (ctx->args.type == ArchArgs::LP384) { setColBufCtrl = false; } @@ -863,6 +913,9 @@ void read_config(Context *ctx, std::istream &in, chipconfig_t &config) case ArchArgs::UP5K: expected = "5k"; break; + case ArchArgs::U4K: + expected = "u4k"; + break; default: log_error("unsupported device type\n"); } diff --git a/ice40/cells.cc b/ice40/cells.cc index aad719b1..5744fe50 100644 --- a/ice40/cells.cc +++ b/ice40/cells.cc @@ -269,11 +269,59 @@ std::unique_ptr<CellInfo> create_ice_cell(Context *ctx, IdString type, std::stri add_port(ctx, new_cell.get(), "LEDDADDR" + std::to_string(i), PORT_IN); add_port(ctx, new_cell.get(), "LEDDDEN", PORT_IN); add_port(ctx, new_cell.get(), "LEDDEXE", PORT_IN); - add_port(ctx, new_cell.get(), "LEDDRST", PORT_IN); //doesn't actually exist, for icecube code compatibility only + add_port(ctx, new_cell.get(), "LEDDRST", PORT_IN); // doesn't actually exist, for icecube code compatibility + // only add_port(ctx, new_cell.get(), "PWMOUT0", PORT_OUT); add_port(ctx, new_cell.get(), "PWMOUT1", PORT_OUT); add_port(ctx, new_cell.get(), "PWMOUT2", PORT_OUT); add_port(ctx, new_cell.get(), "LEDDON", PORT_OUT); + } else if (type == ctx->id("SB_I2C")) { + new_cell->params[ctx->id("I2C_SLAVE_INIT_ADDR")] = "0b1111100001"; + new_cell->params[ctx->id("BUS_ADDR74")] = "0b0001"; + for (int i = 0; i < 8; i++) { + add_port(ctx, new_cell.get(), "SBADRI" + std::to_string(i), PORT_IN); + add_port(ctx, new_cell.get(), "SBDATI" + std::to_string(i), PORT_IN); + add_port(ctx, new_cell.get(), "SBDATO" + std::to_string(i), PORT_OUT); + } + add_port(ctx, new_cell.get(), "SBCLKI", PORT_IN); + add_port(ctx, new_cell.get(), "SBRWI", PORT_IN); + add_port(ctx, new_cell.get(), "SBSTBI", PORT_IN); + add_port(ctx, new_cell.get(), "SCLI", PORT_IN); + add_port(ctx, new_cell.get(), "SDAI", PORT_IN); + add_port(ctx, new_cell.get(), "SBACKO", PORT_OUT); + add_port(ctx, new_cell.get(), "I2CIRQ", PORT_OUT); + add_port(ctx, new_cell.get(), "I2CWKUP", PORT_OUT); + add_port(ctx, new_cell.get(), "SCLO", PORT_OUT); + add_port(ctx, new_cell.get(), "SCLOE", PORT_OUT); + add_port(ctx, new_cell.get(), "SDAO", PORT_OUT); + add_port(ctx, new_cell.get(), "SDAOE", PORT_OUT); + } else if (type == ctx->id("SB_SPI")) { + new_cell->params[ctx->id("BUS_ADDR74")] = "0b0000"; + for (int i = 0; i < 8; i++) { + add_port(ctx, new_cell.get(), "SBADRI" + std::to_string(i), PORT_IN); + add_port(ctx, new_cell.get(), "SBDATI" + std::to_string(i), PORT_IN); + add_port(ctx, new_cell.get(), "SBDATO" + std::to_string(i), PORT_OUT); + } + add_port(ctx, new_cell.get(), "SBCLKI", PORT_IN); + add_port(ctx, new_cell.get(), "SBRWI", PORT_IN); + add_port(ctx, new_cell.get(), "SBSTBI", PORT_IN); + add_port(ctx, new_cell.get(), "MI", PORT_IN); + add_port(ctx, new_cell.get(), "SI", PORT_IN); + add_port(ctx, new_cell.get(), "SCKI", PORT_IN); + add_port(ctx, new_cell.get(), "SCSNI", PORT_IN); + add_port(ctx, new_cell.get(), "SBACKO", PORT_OUT); + add_port(ctx, new_cell.get(), "SPIIRQ", PORT_OUT); + add_port(ctx, new_cell.get(), "SPIWKUP", PORT_OUT); + add_port(ctx, new_cell.get(), "SO", PORT_OUT); + add_port(ctx, new_cell.get(), "SOE", PORT_OUT); + add_port(ctx, new_cell.get(), "MO", PORT_OUT); + add_port(ctx, new_cell.get(), "MOE", PORT_OUT); + add_port(ctx, new_cell.get(), "SCKO", PORT_OUT); + add_port(ctx, new_cell.get(), "SCKOE", PORT_OUT); + for (int i = 0; i < 4; i++) { + add_port(ctx, new_cell.get(), "MCSNO" + std::to_string(i), PORT_OUT); + add_port(ctx, new_cell.get(), "MCSNOE" + std::to_string(i), PORT_OUT); + } } else { log_error("unable to create iCE40 cell of type %s", type.c_str(ctx)); } diff --git a/ice40/cells.h b/ice40/cells.h index 93ef3db4..ec4d560d 100644 --- a/ice40/cells.h +++ b/ice40/cells.h @@ -78,6 +78,10 @@ inline bool is_sb_rgba_drv(const BaseCtx *ctx, const CellInfo *cell) { return ce inline bool is_sb_ledda_ip(const BaseCtx *ctx, const CellInfo *cell) { return cell->type == ctx->id("SB_LEDDA_IP"); } +inline bool is_sb_i2c(const BaseCtx *ctx, const CellInfo *cell) { return cell->type == ctx->id("SB_I2C"); } + +inline bool is_sb_spi(const BaseCtx *ctx, const CellInfo *cell) { return cell->type == ctx->id("SB_SPI"); } + inline bool is_sb_pll40(const BaseCtx *ctx, const CellInfo *cell) { return cell->type == ctx->id("SB_PLL40_PAD") || cell->type == ctx->id("SB_PLL40_2_PAD") || diff --git a/ice40/chains.cc b/ice40/chains.cc index fb361d2d..b3b54d6b 100644 --- a/ice40/chains.cc +++ b/ice40/chains.cc @@ -62,7 +62,7 @@ class ChainConstrainer bool split_chain = (!ctx->logicCellsCompatible(tile.data(), tile.size())) || (int(chains.back().cells.size()) > max_length); if (split_chain) { - CellInfo *passout = make_carry_pass_out(cell->ports.at(ctx->id("COUT"))); + CellInfo *passout = make_carry_pass_out((*(curr_cell - 1))->ports.at(ctx->id("COUT"))); tile.pop_back(); chains.back().cells.back() = passout; start_of_chain = true; @@ -74,10 +74,10 @@ class ChainConstrainer (net_only_drives(ctx, carry_net, is_lc, ctx->id("I3"), false) != net_only_drives(ctx, carry_net, is_lc, ctx->id("CIN"), false)) || (at_end && !net_only_drives(ctx, carry_net, is_lc, ctx->id("I3"), true))) { - CellInfo *passout = make_carry_pass_out(cell->ports.at(ctx->id("COUT"))); + CellInfo *passout = make_carry_pass_out(cell->ports.at(ctx->id("COUT")), + at_end ? nullptr : *(curr_cell + 1)); chains.back().cells.push_back(passout); tile.push_back(passout); - start_of_chain = true; } } ++curr_cell; @@ -87,30 +87,75 @@ class ChainConstrainer } // Insert a logic cell to legalise a COUT->fabric connection - CellInfo *make_carry_pass_out(PortInfo &cout_port) + CellInfo *make_carry_pass_out(PortInfo &cout_port, CellInfo *cin_cell = nullptr) { NPNR_ASSERT(cout_port.net != nullptr); std::unique_ptr<CellInfo> lc = create_ice_cell(ctx, ctx->id("ICESTORM_LC")); lc->params[ctx->id("LUT_INIT")] = "65280"; // 0xff00: O = I3 lc->params[ctx->id("CARRY_ENABLE")] = "1"; - lc->ports.at(ctx->id("O")).net = cout_port.net; + lc->ports.at(id_O).net = cout_port.net; std::unique_ptr<NetInfo> co_i3_net(new NetInfo()); co_i3_net->name = ctx->id(lc->name.str(ctx) + "$I3"); co_i3_net->driver = cout_port.net->driver; PortRef i3_r; - i3_r.port = ctx->id("I3"); + i3_r.port = id_I3; i3_r.cell = lc.get(); co_i3_net->users.push_back(i3_r); PortRef o_r; - o_r.port = ctx->id("O"); + o_r.port = id_O; o_r.cell = lc.get(); cout_port.net->driver = o_r; - lc->ports.at(ctx->id("I3")).net = co_i3_net.get(); + lc->ports.at(id_I3).net = co_i3_net.get(); cout_port.net = co_i3_net.get(); IdString co_i3_name = co_i3_net->name; NPNR_ASSERT(ctx->nets.find(co_i3_name) == ctx->nets.end()); ctx->nets[co_i3_name] = std::move(co_i3_net); + + // If COUT also connects to a CIN; preserve the carry chain + if (cin_cell) { + std::unique_ptr<NetInfo> co_cin_net(new NetInfo()); + co_cin_net->name = ctx->id(lc->name.str(ctx) + "$COUT"); + + // Connect I1 to 1 to preserve carry chain + NetInfo *vcc = ctx->nets.at(ctx->id("$PACKER_VCC_NET")).get(); + lc->ports.at(id_I1).net = vcc; + PortRef i1_r; + i1_r.port = id_I1; + i1_r.cell = lc.get(); + vcc->users.push_back(i1_r); + + // Connect co_cin_net to the COUT of the LC + PortRef co_r; + co_r.port = id_COUT; + co_r.cell = lc.get(); + co_cin_net->driver = co_r; + lc->ports.at(id_COUT).net = co_cin_net.get(); + + // Find the user corresponding to the next CIN + int replaced_ports = 0; + if (ctx->debug) + log_info("cell: %s\n", cin_cell->name.c_str(ctx)); + for (auto port : {id_CIN, id_I3}) { + auto &usr = lc->ports.at(id_O).net->users; + if (ctx->debug) + for (auto user : usr) + log_info("%s.%s\n", user.cell->name.c_str(ctx), user.port.c_str(ctx)); + auto fnd_user = std::find_if(usr.begin(), usr.end(), + [&](const PortRef &pr) { return pr.cell == cin_cell && pr.port == port; }); + if (fnd_user != usr.end()) { + co_cin_net->users.push_back(*fnd_user); + usr.erase(fnd_user); + cin_cell->ports.at(port).net = co_cin_net.get(); + ++replaced_ports; + } + } + NPNR_ASSERT(replaced_ports > 0); + IdString co_cin_name = co_cin_net->name; + NPNR_ASSERT(ctx->nets.find(co_cin_name) == ctx->nets.end()); + ctx->nets[co_cin_name] = std::move(co_cin_net); + } + IdString name = lc->name; ctx->assignCellInfo(lc.get()); ctx->cells[lc->name] = std::move(lc); @@ -163,29 +208,31 @@ class ChainConstrainer void process_carries() { - std::vector<CellChain> carry_chains = - find_chains(ctx, [](const Context *ctx, const CellInfo *cell) { return is_lc(ctx, cell); }, - [](const Context *ctx, const - - CellInfo *cell) { - CellInfo *carry_prev = - net_driven_by(ctx, cell->ports.at(ctx->id("CIN")).net, is_lc, ctx->id("COUT")); - if (carry_prev != nullptr) - return carry_prev; - /*CellInfo *i3_prev = net_driven_by(ctx, cell->ports.at(ctx->id("I3")).net, is_lc, - ctx->id("COUT")); if (i3_prev != nullptr) return i3_prev;*/ - return (CellInfo *)nullptr; - }, - [](const Context *ctx, const CellInfo *cell) { - CellInfo *carry_next = net_only_drives(ctx, cell->ports.at(ctx->id("COUT")).net, is_lc, - ctx->id("CIN"), false); - if (carry_next != nullptr) - return carry_next; - /*CellInfo *i3_next = - net_only_drives(ctx, cell->ports.at(ctx->id("COUT")).net, is_lc, ctx->id("I3"), - false); if (i3_next != nullptr) return i3_next;*/ - return (CellInfo *)nullptr; - }); + std::vector<CellChain> carry_chains = find_chains( + ctx, [](const Context *ctx, const CellInfo *cell) { return is_lc(ctx, cell); }, + [](const Context *ctx, const + + CellInfo *cell) { + CellInfo *carry_prev = + net_driven_by(ctx, cell->ports.at(ctx->id("CIN")).net, is_lc, ctx->id("COUT")); + if (carry_prev != nullptr) + return carry_prev; + CellInfo *i3_prev = net_driven_by(ctx, cell->ports.at(ctx->id("I3")).net, is_lc, ctx->id("COUT")); + if (i3_prev != nullptr) + return i3_prev; + return (CellInfo *)nullptr; + }, + [](const Context *ctx, const CellInfo *cell) { + CellInfo *carry_next = + net_only_drives(ctx, cell->ports.at(ctx->id("COUT")).net, is_lc, ctx->id("CIN"), false); + if (carry_next != nullptr) + return carry_next; + CellInfo *i3_next = + net_only_drives(ctx, cell->ports.at(ctx->id("COUT")).net, is_lc, ctx->id("I3"), false); + if (i3_next != nullptr) + return i3_next; + return (CellInfo *)nullptr; + }); std::unordered_set<IdString> chained; for (auto &base_chain : carry_chains) { for (auto c : base_chain.cells) diff --git a/ice40/chipdb.py b/ice40/chipdb.py index 96231b26..42ca6ac1 100644 --- a/ice40/chipdb.py +++ b/ice40/chipdb.py @@ -492,7 +492,7 @@ def wiredelay(wire_idx, db): def init_tiletypes(device): global num_tile_types, tile_sizes, tile_bits - if device == "5k": + if device in ["5k", "u4k"]: num_tile_types = 10 else: num_tile_types = 5 @@ -954,6 +954,27 @@ def add_bel_ec(ec): add_pll_clock_output(bel, ec, entry) else: extra_cell_config[bel].append(entry) + if ectype == "MAC16": + if y == 5: + last_dsp_y = 0 # dummy, but the wire is needed + elif y == 10: + last_dsp_y = 5 + elif y == 13: + last_dsp_y = 5 + elif y == 15: + last_dsp_y = 10 + elif y == 23: + last_dsp_y = 23 + else: + assert False, "unknown DSP y " + str(y) + wire_signextin = add_wire(x, last_dsp_y, "dsp/signextout") + wire_signextout = add_wire(x, y, "dsp/signextout") + wire_accumci = add_wire(x, last_dsp_y, "dsp/accumco") + wire_accumco = add_wire(x, y, "dsp/accumco") + add_bel_input(bel, wire_signextin, "SIGNEXTIN") + add_bel_output(bel, wire_signextout, "SIGNEXTOUT") + add_bel_input(bel, wire_accumci, "ACCUMCI") + add_bel_output(bel, wire_accumco, "ACCUMCO") cell_timings = {} tmport_to_constids = { diff --git a/ice40/constids.inc b/ice40/constids.inc index e1c4992e..366a3a9d 100644 --- a/ice40/constids.inc +++ b/ice40/constids.inc @@ -247,6 +247,11 @@ X(O_6) X(O_7) X(O_8) X(O_9) +X(SIGNEXTIN) +X(SIGNEXTOUT) +X(ACCUMCI) +X(ACCUMCO) + X(CLKHF) X(CLKHFEN) @@ -426,6 +431,7 @@ X(SB_WARMBOOT) X(ICESTORM_DSP) X(ICESTORM_HFOSC) X(ICESTORM_LFOSC) +X(SMCCLK) X(SB_I2C) X(SB_SPI) X(IO_I3C) diff --git a/ice40/delay.cc b/ice40/delay.cc index 54905551..707208d8 100644 --- a/ice40/delay.cc +++ b/ice40/delay.cc @@ -138,7 +138,7 @@ struct model_params_t if (args.type == ArchArgs::LP384 || args.type == ArchArgs::LP1K || args.type == ArchArgs::LP8K) return model_lp8k; - if (args.type == ArchArgs::UP5K) + if (args.type == ArchArgs::UP5K || args.type == ArchArgs::U4K) return model_up5k; NPNR_ASSERT(0); diff --git a/ice40/blinky.pcf b/ice40/examples/blinky/blinky.pcf index 141dfcc8..141dfcc8 100644 --- a/ice40/blinky.pcf +++ b/ice40/examples/blinky/blinky.pcf diff --git a/ice40/blinky.proj b/ice40/examples/blinky/blinky.proj index f5bb9f88..f5bb9f88 100644 --- a/ice40/blinky.proj +++ b/ice40/examples/blinky/blinky.proj diff --git a/ice40/blinky.sh b/ice40/examples/blinky/blinky.sh index a2326fc3..a2326fc3 100755 --- a/ice40/blinky.sh +++ b/ice40/examples/blinky/blinky.sh diff --git a/ice40/blinky.v b/ice40/examples/blinky/blinky.v index 36eaee86..36eaee86 100644 --- a/ice40/blinky.v +++ b/ice40/examples/blinky/blinky.v diff --git a/ice40/blinky.ys b/ice40/examples/blinky/blinky.ys index a5dd2c85..a5dd2c85 100644 --- a/ice40/blinky.ys +++ b/ice40/examples/blinky/blinky.ys diff --git a/ice40/blinky_tb.v b/ice40/examples/blinky/blinky_tb.v index f80b5e64..f80b5e64 100644 --- a/ice40/blinky_tb.v +++ b/ice40/examples/blinky/blinky_tb.v diff --git a/ice40/examples/floorplan/.gitignore b/ice40/examples/floorplan/.gitignore new file mode 100644 index 00000000..d93659be --- /dev/null +++ b/ice40/examples/floorplan/.gitignore @@ -0,0 +1,4 @@ +*.json +*.asc +*.bin +__pycache__
\ No newline at end of file diff --git a/ice40/examples/floorplan/floorplan.py b/ice40/examples/floorplan/floorplan.py new file mode 100644 index 00000000..85c53ccd --- /dev/null +++ b/ice40/examples/floorplan/floorplan.py @@ -0,0 +1,5 @@ +ctx.createRectangularRegion("osc", 1, 1, 1, 4) +for cell, cellinfo in ctx.cells: + if "ringosc" in cellinfo.attrs: + print("Floorplanned cell %s" % cell) + ctx.constrainCellToRegion(cell, "osc") diff --git a/ice40/examples/floorplan/floorplan.sh b/ice40/examples/floorplan/floorplan.sh new file mode 100755 index 00000000..e0ed7a64 --- /dev/null +++ b/ice40/examples/floorplan/floorplan.sh @@ -0,0 +1,6 @@ +#!/usr/bin/env bash +set -ex +yosys -p "synth_ice40 -top top -json floorplan.json" floorplan.v +../../../nextpnr-ice40 --up5k --json floorplan.json --pcf icebreaker.pcf --asc floorplan.asc --ignore-loops --pre-place floorplan.py +icepack floorplan.asc floorplan.bin +iceprog floorplan.bin diff --git a/ice40/examples/floorplan/floorplan.v b/ice40/examples/floorplan/floorplan.v new file mode 100644 index 00000000..8f99ed4e --- /dev/null +++ b/ice40/examples/floorplan/floorplan.v @@ -0,0 +1,22 @@ +module top(output LED1, LED2, LED3, LED4, LED5); + localparam N = 31; + wire [N:0] x; + assign x[0] = x[N]; + + genvar ii; + generate + + for (ii = 0; ii < N; ii = ii + 1) begin + (* ringosc *) + SB_LUT4 #(.LUT_INIT(1)) lut_i(.I0(x[ii]), .I1(), .I2(), .I3(), .O(x[ii+1])); + end + endgenerate + + assign clk = x[N]; + + + reg [19:0] ctr; + always @(posedge clk) + ctr <= ctr + 1'b1; + assign {LED5, LED4, LED3, LED2, LED1} = ctr[19:15]; +endmodule diff --git a/ice40/examples/floorplan/icebreaker.pcf b/ice40/examples/floorplan/icebreaker.pcf new file mode 100644 index 00000000..ac7ebf9e --- /dev/null +++ b/ice40/examples/floorplan/icebreaker.pcf @@ -0,0 +1,5 @@ +set_io -nowarn LED1 26 +set_io -nowarn LED2 27 +set_io -nowarn LED3 25 +set_io -nowarn LED4 23 +set_io -nowarn LED5 21 diff --git a/ice40/family.cmake b/ice40/family.cmake index 0e1d36e6..e1fcec16 100644 --- a/ice40/family.cmake +++ b/ice40/family.cmake @@ -1,84 +1,92 @@ -if(ICE40_HX1K_ONLY) - set(devices 1k) - foreach (target ${family_targets}) - target_compile_definitions(${target} PRIVATE ICE40_HX1K_ONLY=1) - endforeach (target) -else() - set(devices 384 1k 5k 8k) -endif() +if (NOT EXTERNAL_CHIPDB) + if(ICE40_HX1K_ONLY) + set(devices 1k) + foreach (target ${family_targets}) + target_compile_definitions(${target} PRIVATE ICE40_HX1K_ONLY=1) + endforeach (target) + else() + set(devices 384 1k 5k u4k 8k) + endif() -set(DB_PY ${CMAKE_CURRENT_SOURCE_DIR}/ice40/chipdb.py) + set(DB_PY ${CMAKE_CURRENT_SOURCE_DIR}/ice40/chipdb.py) -set(ICEBOX_ROOT "/usr/local/share/icebox" CACHE STRING "icebox location root") -file(MAKE_DIRECTORY ice40/chipdbs/) -add_library(ice40_chipdb OBJECT ice40/chipdbs/) -target_compile_definitions(ice40_chipdb PRIVATE NEXTPNR_NAMESPACE=nextpnr_${family}) -target_include_directories(ice40_chipdb PRIVATE ${family}/) + set(ICEBOX_ROOT "/usr/local/share/icebox" CACHE STRING "icebox location root") + file(MAKE_DIRECTORY ice40/chipdbs/) + add_library(ice40_chipdb OBJECT ice40/chipdbs/) + target_compile_definitions(ice40_chipdb PRIVATE NEXTPNR_NAMESPACE=nextpnr_${family}) + target_include_directories(ice40_chipdb PRIVATE ${family}/) -if (MSVC) - target_sources(ice40_chipdb PRIVATE ${CMAKE_CURRENT_SOURCE_DIR}/ice40/resource/embed.cc) - set_source_files_properties(${CMAKE_CURRENT_SOURCE_DIR}/ice40/resources/chipdb.rc PROPERTIES LANGUAGE RC) - foreach (dev ${devices}) - if (dev EQUAL "5k") - set(OPT_FAST "") - set(OPT_SLOW --slow ${ICEBOX_ROOT}/timings_up5k.txt) - elseif(dev EQUAL "384") - set(OPT_FAST "") - set(OPT_SLOW --slow ${ICEBOX_ROOT}/timings_lp384.txt) - else() - set(OPT_FAST --fast ${ICEBOX_ROOT}/timings_hx${dev}.txt) - set(OPT_SLOW --slow ${ICEBOX_ROOT}/timings_lp${dev}.txt) - endif() - set(DEV_TXT_DB ${ICEBOX_ROOT}/chipdb-${dev}.txt) - set(DEV_CC_BBA_DB ${CMAKE_CURRENT_SOURCE_DIR}/ice40/chipdbs/chipdb-${dev}.bba) - set(DEV_CC_DB ${CMAKE_CURRENT_SOURCE_DIR}/ice40/chipdbs/chipdb-${dev}.bin) - set(DEV_CONSTIDS_INC ${CMAKE_CURRENT_SOURCE_DIR}/ice40/constids.inc) - set(DEV_GFXH ${CMAKE_CURRENT_SOURCE_DIR}/ice40/gfx.h) - add_custom_command(OUTPUT ${DEV_CC_BBA_DB} - COMMAND ${PYTHON_EXECUTABLE} ${DB_PY} -p ${DEV_CONSTIDS_INC} -g ${DEV_GFXH} ${OPT_FAST} ${OPT_SLOW} ${DEV_TXT_DB} > ${DEV_CC_BBA_DB} - DEPENDS ${DEV_CONSTIDS_INC} ${DEV_GFXH} ${DEV_TXT_DB} ${DB_PY} - ) - add_custom_command(OUTPUT ${DEV_CC_DB} - COMMAND bbasm ${DEV_CC_BBA_DB} ${DEV_CC_DB} - DEPENDS bbasm ${DEV_CC_BBA_DB} - ) - target_sources(ice40_chipdb PRIVATE ${DEV_CC_DB}) - set_source_files_properties(${DEV_CC_DB} PROPERTIES HEADER_FILE_ONLY TRUE) - foreach (target ${family_targets}) - target_sources(${target} PRIVATE $<TARGET_OBJECTS:ice40_chipdb> ${CMAKE_CURRENT_SOURCE_DIR}/ice40/resource/chipdb.rc) - endforeach (target) - endforeach (dev) -else() - target_compile_options(ice40_chipdb PRIVATE -g0 -O0 -w) - foreach (dev ${devices}) - if (dev EQUAL "5k") - set(OPT_FAST "") - set(OPT_SLOW --slow ${ICEBOX_ROOT}/timings_up5k.txt) - elseif(dev EQUAL "384") - set(OPT_FAST "") - set(OPT_SLOW --slow ${ICEBOX_ROOT}/timings_lp384.txt) - else() - set(OPT_FAST --fast ${ICEBOX_ROOT}/timings_hx${dev}.txt) - set(OPT_SLOW --slow ${ICEBOX_ROOT}/timings_lp${dev}.txt) - endif() - set(DEV_TXT_DB ${ICEBOX_ROOT}/chipdb-${dev}.txt) - set(DEV_CC_BBA_DB ${CMAKE_CURRENT_SOURCE_DIR}/ice40/chipdbs/chipdb-${dev}.bba) - set(DEV_CC_DB ${CMAKE_CURRENT_SOURCE_DIR}/ice40/chipdbs/chipdb-${dev}.cc) - set(DEV_CONSTIDS_INC ${CMAKE_CURRENT_SOURCE_DIR}/ice40/constids.inc) - set(DEV_GFXH ${CMAKE_CURRENT_SOURCE_DIR}/ice40/gfx.h) - add_custom_command(OUTPUT ${DEV_CC_BBA_DB} - COMMAND ${PYTHON_EXECUTABLE} ${DB_PY} -p ${DEV_CONSTIDS_INC} -g ${DEV_GFXH} ${OPT_FAST} ${OPT_SLOW} ${DEV_TXT_DB} > ${DEV_CC_BBA_DB}.new - COMMAND mv ${DEV_CC_BBA_DB}.new ${DEV_CC_BBA_DB} - DEPENDS ${DEV_CONSTIDS_INC} ${DEV_GFXH} ${DEV_TXT_DB} ${DB_PY} - ) - add_custom_command(OUTPUT ${DEV_CC_DB} - COMMAND bbasm --c ${DEV_CC_BBA_DB} ${DEV_CC_DB}.new - COMMAND mv ${DEV_CC_DB}.new ${DEV_CC_DB} - DEPENDS bbasm ${DEV_CC_BBA_DB} - ) - target_sources(ice40_chipdb PRIVATE ${DEV_CC_DB}) - foreach (target ${family_targets}) - target_sources(${target} PRIVATE $<TARGET_OBJECTS:ice40_chipdb>) - endforeach (target) - endforeach (dev) + if (MSVC) + target_sources(ice40_chipdb PRIVATE ${CMAKE_CURRENT_SOURCE_DIR}/ice40/resource/embed.cc) + set_source_files_properties(${CMAKE_CURRENT_SOURCE_DIR}/ice40/resources/chipdb.rc PROPERTIES LANGUAGE RC) + foreach (dev ${devices}) + if (dev STREQUAL "5k") + set(OPT_FAST "") + set(OPT_SLOW --slow ${ICEBOX_ROOT}/timings_up5k.txt) + elseif (dev STREQUAL "u4k") + set(OPT_FAST "") + set(OPT_SLOW --slow ${ICEBOX_ROOT}/timings_u4k.txt) + elseif(dev STREQUAL "384") + set(OPT_FAST "") + set(OPT_SLOW --slow ${ICEBOX_ROOT}/timings_lp384.txt) + else() + set(OPT_FAST --fast ${ICEBOX_ROOT}/timings_hx${dev}.txt) + set(OPT_SLOW --slow ${ICEBOX_ROOT}/timings_lp${dev}.txt) + endif() + set(DEV_TXT_DB ${ICEBOX_ROOT}/chipdb-${dev}.txt) + set(DEV_CC_BBA_DB ${CMAKE_CURRENT_SOURCE_DIR}/ice40/chipdbs/chipdb-${dev}.bba) + set(DEV_CC_DB ${CMAKE_CURRENT_SOURCE_DIR}/ice40/chipdbs/chipdb-${dev}.bin) + set(DEV_CONSTIDS_INC ${CMAKE_CURRENT_SOURCE_DIR}/ice40/constids.inc) + set(DEV_GFXH ${CMAKE_CURRENT_SOURCE_DIR}/ice40/gfx.h) + add_custom_command(OUTPUT ${DEV_CC_BBA_DB} + COMMAND ${PYTHON_EXECUTABLE} ${DB_PY} -p ${DEV_CONSTIDS_INC} -g ${DEV_GFXH} ${OPT_FAST} ${OPT_SLOW} ${DEV_TXT_DB} > ${DEV_CC_BBA_DB} + DEPENDS ${DEV_CONSTIDS_INC} ${DEV_GFXH} ${DEV_TXT_DB} ${DB_PY} + ) + add_custom_command(OUTPUT ${DEV_CC_DB} + COMMAND bbasm ${DEV_CC_BBA_DB} ${DEV_CC_DB} + DEPENDS bbasm ${DEV_CC_BBA_DB} + ) + target_sources(ice40_chipdb PRIVATE ${DEV_CC_DB}) + set_source_files_properties(${DEV_CC_DB} PROPERTIES HEADER_FILE_ONLY TRUE) + foreach (target ${family_targets}) + target_sources(${target} PRIVATE $<TARGET_OBJECTS:ice40_chipdb> ${CMAKE_CURRENT_SOURCE_DIR}/ice40/resource/chipdb.rc) + endforeach (target) + endforeach (dev) + else() + target_compile_options(ice40_chipdb PRIVATE -g0 -O0 -w) + foreach (dev ${devices}) + if (dev STREQUAL "5k") + set(OPT_FAST "") + set(OPT_SLOW --slow ${ICEBOX_ROOT}/timings_up5k.txt) + elseif (dev STREQUAL "u4k") + set(OPT_FAST "") + set(OPT_SLOW --slow ${ICEBOX_ROOT}/timings_u4k.txt) + elseif(dev STREQUAL "384") + set(OPT_FAST "") + set(OPT_SLOW --slow ${ICEBOX_ROOT}/timings_lp384.txt) + else() + set(OPT_FAST --fast ${ICEBOX_ROOT}/timings_hx${dev}.txt) + set(OPT_SLOW --slow ${ICEBOX_ROOT}/timings_lp${dev}.txt) + endif() + set(DEV_TXT_DB ${ICEBOX_ROOT}/chipdb-${dev}.txt) + set(DEV_CC_BBA_DB ${CMAKE_CURRENT_SOURCE_DIR}/ice40/chipdbs/chipdb-${dev}.bba) + set(DEV_CC_DB ${CMAKE_CURRENT_SOURCE_DIR}/ice40/chipdbs/chipdb-${dev}.cc) + set(DEV_CONSTIDS_INC ${CMAKE_CURRENT_SOURCE_DIR}/ice40/constids.inc) + set(DEV_GFXH ${CMAKE_CURRENT_SOURCE_DIR}/ice40/gfx.h) + add_custom_command(OUTPUT ${DEV_CC_BBA_DB} + COMMAND ${PYTHON_EXECUTABLE} ${DB_PY} -p ${DEV_CONSTIDS_INC} -g ${DEV_GFXH} ${OPT_FAST} ${OPT_SLOW} ${DEV_TXT_DB} > ${DEV_CC_BBA_DB}.new + COMMAND mv ${DEV_CC_BBA_DB}.new ${DEV_CC_BBA_DB} + DEPENDS ${DEV_CONSTIDS_INC} ${DEV_GFXH} ${DEV_TXT_DB} ${DB_PY} + ) + add_custom_command(OUTPUT ${DEV_CC_DB} + COMMAND bbasm --c ${DEV_CC_BBA_DB} ${DEV_CC_DB}.new + COMMAND mv ${DEV_CC_DB}.new ${DEV_CC_DB} + DEPENDS bbasm ${DEV_CC_BBA_DB} + ) + target_sources(ice40_chipdb PRIVATE ${DEV_CC_DB}) + foreach (target ${family_targets}) + target_sources(${target} PRIVATE $<TARGET_OBJECTS:ice40_chipdb>) + endforeach (target) + endforeach (dev) + endif() endif() diff --git a/ice40/main.cc b/ice40/main.cc index 4b6a9e42..9b79a08c 100644 --- a/ice40/main.cc +++ b/ice40/main.cc @@ -60,6 +60,7 @@ po::options_description Ice40CommandHandler::getArchOptions() specific.add_options()("hx1k", "set device type to iCE40HX1K"); specific.add_options()("hx8k", "set device type to iCE40HX8K"); specific.add_options()("up5k", "set device type to iCE40UP5K"); + specific.add_options()("u4k", "set device type to iCE5LP4K"); #endif specific.add_options()("package", po::value<std::string>(), "set device package"); specific.add_options()("pcf", po::value<std::string>(), "PCF constraints file to ingest"); @@ -68,14 +69,17 @@ po::options_description Ice40CommandHandler::getArchOptions() specific.add_options()("promote-logic", "enable promotion of 'logic' globals (in addition to clk/ce/sr by default)"); specific.add_options()("no-promote-globals", "disable all global promotion"); + specific.add_options()("opt-timing", "run post-placement timing optimisation pass (experimental)"); specific.add_options()("tmfuzz", "run path delay estimate fuzzer"); + specific.add_options()("pcf-allow-unconstrained", "don't require PCF to constrain all IO"); + return specific; } void Ice40CommandHandler::validate() { conflicting_options(vm, "read", "json"); if ((vm.count("lp384") + vm.count("lp1k") + vm.count("lp8k") + vm.count("hx1k") + vm.count("hx8k") + - vm.count("up5k")) > 1) + vm.count("up5k") + vm.count("u4k")) > 1) log_error("Only one device type can be set\n"); } @@ -86,6 +90,8 @@ void Ice40CommandHandler::customAfterLoad(Context *ctx) std::ifstream pcf(filename); if (!apply_pcf(ctx, filename, pcf)) log_error("Loading PCF failed.\n"); + } else { + log_warning("No PCF file specified; IO pins will be placed automatically\n"); } } void Ice40CommandHandler::customBitstream(Context *ctx) @@ -142,6 +148,11 @@ std::unique_ptr<Context> Ice40CommandHandler::createContext() chipArgs.package = "sg48"; } + if (vm.count("u4k")) { + chipArgs.type = ArchArgs::U4K; + chipArgs.package = "sg48"; + } + if (chipArgs.type == ArchArgs::NONE) { chipArgs.type = ArchArgs::HX1K; chipArgs.package = "tq144"; @@ -161,6 +172,10 @@ std::unique_ptr<Context> Ice40CommandHandler::createContext() ctx->settings[ctx->id("promote_logic")] = "1"; if (vm.count("no-promote-globals")) ctx->settings[ctx->id("no_promote_globals")] = "1"; + if (vm.count("opt-timing")) + ctx->settings[ctx->id("opt_timing")] = "1"; + if (vm.count("pcf-allow-unconstrained")) + ctx->settings[ctx->id("pcf_allow_unconstrained")] = "1"; return ctx; } diff --git a/ice40/pack.cc b/ice40/pack.cc index e71db46f..390cbf57 100644 --- a/ice40/pack.cc +++ b/ice40/pack.cc @@ -265,6 +265,8 @@ static void pack_ram(Context *ctx) std::unique_ptr<CellInfo> packed = create_ice_cell(ctx, ctx->id("ICESTORM_RAM"), ci->name.str(ctx) + "_RAM"); packed_cells.insert(ci->name); + for (auto attr : ci->attrs) + packed->attrs[attr.first] = attr.second; for (auto param : ci->params) packed->params[param.first] = param.second; packed->params[ctx->id("NEG_CLK_W")] = @@ -381,13 +383,14 @@ static void pack_constants(Context *ctx) } } -static std::unique_ptr<CellInfo> create_padin_gbuf(Context *ctx, CellInfo *cell, IdString port_name, - std::string gbuf_name) +static BelId find_padin_gbuf(Context *ctx, BelId bel, IdString port_name) { - // Find the matching SB_GB BEL connected to the same global network BelId gb_bel; - BelId bel = ctx->getBelByName(ctx->id(cell->attrs[ctx->id("BEL")])); auto wire = ctx->getBelPinWire(bel, port_name); + + if (wire == WireId()) + log_error("BEL '%s' has no global buffer connection available\n", ctx->getBelName(bel).c_str(ctx)); + for (auto src_bel : ctx->getWireBelPins(wire)) { if (ctx->getBelType(src_bel.bel) == id_SB_GB && src_bel.pin == id_GLOBAL_BUFFER_OUTPUT) { gb_bel = src_bel.bel; @@ -395,6 +398,15 @@ static std::unique_ptr<CellInfo> create_padin_gbuf(Context *ctx, CellInfo *cell, } } + return gb_bel; +} + +static std::unique_ptr<CellInfo> create_padin_gbuf(Context *ctx, CellInfo *cell, IdString port_name, + std::string gbuf_name) +{ + // Find the matching SB_GB BEL connected to the same global network + BelId bel = ctx->getBelByName(ctx->id(cell->attrs[ctx->id("BEL")])); + BelId gb_bel = find_padin_gbuf(ctx, bel, port_name); NPNR_ASSERT(gb_bel != BelId()); // Create a SB_GB Cell and lock it there @@ -478,9 +490,6 @@ static void pack_io(Context *ctx) } packed_cells.insert(ci->name); std::copy(ci->attrs.begin(), ci->attrs.end(), std::inserter(sb->attrs, sb->attrs.begin())); - if (!sb->attrs.count(ctx->id("BEL"))) - log_warning("IO '%s' is not constrained to a pin and will be automatically placed\n", - ci->name.c_str(ctx)); } else if (is_sb_io(ctx, ci) || is_sb_gb_io(ctx, ci)) { NetInfo *net = ci->ports.at(ctx->id("PACKAGE_PIN")).net; if ((net != nullptr) && (net->users.size() > 1)) @@ -499,6 +508,19 @@ static void pack_io(Context *ctx) // Make it a normal SB_IO with global marker ci->type = ctx->id("SB_IO"); ci->attrs[ctx->id("GLOBAL")] = "1"; + } else if (is_sb_io(ctx, ci)) { + // Disconnect unused inputs + NetInfo *net_in0 = ci->ports.count(id_D_IN_0) ? ci->ports[id_D_IN_0].net : nullptr; + NetInfo *net_in1 = ci->ports.count(id_D_IN_1) ? ci->ports[id_D_IN_1].net : nullptr; + + if (net_in0 != nullptr && net_in0->users.size() == 0) { + delete_nets.insert(net_in0->name); + ci->ports[id_D_IN_0].net = nullptr; + } + if (net_in1 != nullptr && net_in1->users.size() == 0) { + delete_nets.insert(net_in1->name); + ci->ports[id_D_IN_1].net = nullptr; + } } } for (auto pcell : packed_cells) { @@ -688,14 +710,15 @@ static void promote_globals(Context *ctx) // Figure out where to place PLLs static void place_plls(Context *ctx) { - std::map<BelId, std::pair<BelPin, BelPin>> pll_all_bels; + std::map<BelId, std::tuple<BelPin, BelId, BelPin, BelId>> pll_all_bels; std::map<BelId, CellInfo *> pll_used_bels; std::vector<CellInfo *> pll_cells; std::map<BelId, CellInfo *> bel2io; + std::map<BelId, CellInfo *> bel2gb; log_info("Placing PLLs..\n"); - // Find all the PLLs BELs and matching IO sites + // Find all the PLLs BELs and matching IO sites and global networks for (auto bel : ctx->getBels()) { if (ctx->getBelType(bel) != id_ICESTORM_PLL) continue; @@ -704,8 +727,10 @@ static void place_plls(Context *ctx) auto io_a_pin = ctx->getIOBSharingPLLPin(bel, id_PLLOUT_A); auto io_b_pin = ctx->getIOBSharingPLLPin(bel, id_PLLOUT_B); + auto gb_a = find_padin_gbuf(ctx, bel, id_PLLOUT_A_GLOBAL); + auto gb_b = find_padin_gbuf(ctx, bel, id_PLLOUT_B_GLOBAL); - pll_all_bels[bel] = std::make_pair(io_a_pin, io_b_pin); + pll_all_bels[bel] = std::make_tuple(io_a_pin, gb_a, io_b_pin, gb_b); } // Find all the PLLs cells we need to place and do pre-checks @@ -767,6 +792,8 @@ static void place_plls(Context *ctx) io_cell->name.c_str(ctx)); if (pll_used_bels.count(found_bel)) { CellInfo *conflict_cell = pll_used_bels.at(found_bel); + if (conflict_cell == ci) + continue; log_error("PLL '%s' PACKAGEPIN forces it to BEL %s but BEL is already assigned to PLL '%s'\n", ci->name.c_str(ctx), ctx->getBelName(found_bel).c_str(ctx), conflict_cell->name.c_str(ctx)); } @@ -808,7 +835,8 @@ static void place_plls(Context *ctx) for (auto placed_pll : pll_used_bels) { BelPin pll_io_a, pll_io_b; - std::tie(pll_io_a, pll_io_b) = pll_all_bels[placed_pll.first]; + BelId gb_a, gb_b; + std::tie(pll_io_a, gb_a, pll_io_b, gb_b) = pll_all_bels[placed_pll.first]; if (io_bel == pll_io_a.bel) { // All the PAD type PLL stuff already checked above,so only // check for conflict with a user placed CORE PLL @@ -826,6 +854,47 @@ static void place_plls(Context *ctx) bel2io[io_bel] = io_ci; } + // Scan all SB_GBs to check for conflicts with PLL BELs + for (auto gb_cell : sorted(ctx->cells)) { + CellInfo *gb_ci = gb_cell.second; + if (!is_gbuf(ctx, gb_ci)) + continue; + + // Only consider the bound ones + if (!gb_ci->attrs.count(ctx->id("BEL"))) + continue; + + // Check all placed PLL (either forced by user, or forced by PACKAGEPIN) + BelId gb_bel = ctx->getBelByName(ctx->id(gb_ci->attrs[ctx->id("BEL")])); + + for (auto placed_pll : pll_used_bels) { + CellInfo *ci = placed_pll.second; + + // Used global connections + bool gb_a_used = ci->ports.count(id_PLLOUT_A_GLOBAL) && (ci->ports[id_PLLOUT_A_GLOBAL].net != nullptr) && + (ci->ports[id_PLLOUT_A_GLOBAL].net->users.size() > 0); + bool gb_b_used = is_sb_pll40_dual(ctx, ci) && ci->ports.count(id_PLLOUT_B_GLOBAL) && + (ci->ports[id_PLLOUT_B_GLOBAL].net != nullptr) && + (ci->ports[id_PLLOUT_B_GLOBAL].net->users.size() > 0); + + // Check for conflict + BelPin pll_io_a, pll_io_b; + BelId gb_a, gb_b; + std::tie(pll_io_a, gb_a, pll_io_b, gb_b) = pll_all_bels[placed_pll.first]; + if (gb_a_used && (gb_bel == gb_a)) { + log_error("PLL '%s' A output conflict with SB_GB '%s'\n", placed_pll.second->name.c_str(ctx), + gb_cell.second->name.c_str(ctx)); + } + if (gb_b_used && (gb_bel == gb_b)) { + log_error("PLL '%s' B output conflicts with SB_GB '%s'\n", placed_pll.second->name.c_str(ctx), + gb_cell.second->name.c_str(ctx)); + } + } + + // Save for later checks + bel2gb[gb_bel] = gb_ci; + } + // Scan all the CORE PLLs and place them in remaining available PLL BELs // (in two pass ... first do the dual ones, harder to place, then single port) for (int i = 0; i < 2; i++) { @@ -844,6 +913,13 @@ static void place_plls(Context *ctx) log_error("PLL '%s' is of CORE type but doesn't have a valid REFERENCECLK connection\n", ci->name.c_str(ctx)); + // Used global connections + bool gb_a_used = ci->ports.count(id_PLLOUT_A_GLOBAL) && (ci->ports[id_PLLOUT_A_GLOBAL].net != nullptr) && + (ci->ports[id_PLLOUT_A_GLOBAL].net->users.size() > 0); + bool gb_b_used = is_sb_pll40_dual(ctx, ci) && ci->ports.count(id_PLLOUT_B_GLOBAL) && + (ci->ports[id_PLLOUT_B_GLOBAL].net != nullptr) && + (ci->ports[id_PLLOUT_B_GLOBAL].net->users.size() > 0); + // Could this be a PAD PLL ? bool could_be_pad = false; BelId pad_bel; @@ -853,8 +929,11 @@ static void place_plls(Context *ctx) // Find a BEL for it BelId found_bel; for (auto bel_pll : pll_all_bels) { + if (pll_used_bels.count(bel_pll.first)) + continue; BelPin pll_io_a, pll_io_b; - std::tie(pll_io_a, pll_io_b) = bel_pll.second; + BelId gb_a, gb_b; + std::tie(pll_io_a, gb_a, pll_io_b, gb_b) = bel_pll.second; if (bel2io.count(pll_io_a.bel)) { if (pll_io_a.bel == pad_bel) could_be_pad = !bel2io.count(pll_io_b.bel) || !is_sb_pll40_dual(ctx, ci); @@ -862,6 +941,10 @@ static void place_plls(Context *ctx) } if (bel2io.count(pll_io_b.bel) && is_sb_pll40_dual(ctx, ci)) continue; + if (gb_a_used && bel2gb.count(gb_a)) + continue; + if (gb_b_used && bel2gb.count(gb_b)) + continue; found_bel = bel_pll.first; break; } @@ -978,9 +1061,14 @@ static void pack_special(Context *ctx) create_ice_cell(ctx, ctx->id("ICESTORM_HFOSC"), ci->name.str(ctx) + "_OSC"); packed_cells.insert(ci->name); cell_place_unique(ctx, packed.get()); + packed->params[ctx->id("TRIM_EN")] = str_or_default(ci->params, ctx->id("TRIM_EN"), "0b0"); packed->params[ctx->id("CLKHF_DIV")] = str_or_default(ci->params, ctx->id("CLKHF_DIV"), "0b00"); replace_port(ci, ctx->id("CLKHFEN"), packed.get(), ctx->id("CLKHFEN")); replace_port(ci, ctx->id("CLKHFPU"), packed.get(), ctx->id("CLKHFPU")); + for (int i = 0; i < 10; i++) { + auto port = ctx->id("TRIM" + std::to_string(i)); + replace_port(ci, port, packed.get(), port); + } if (bool_or_default(ci->attrs, ctx->id("ROUTE_THROUGH_FABRIC"))) { replace_port(ci, ctx->id("CLKHF"), packed.get(), ctx->id("CLKHF_FABRIC")); } else { @@ -994,6 +1082,8 @@ static void pack_special(Context *ctx) std::unique_ptr<CellInfo> packed = create_ice_cell(ctx, ctx->id("ICESTORM_SPRAM"), ci->name.str(ctx) + "_RAM"); packed_cells.insert(ci->name); + for (auto attr : ci->attrs) + packed->attrs[attr.first] = attr.second; for (auto port : ci->ports) { PortInfo &pi = port.second; std::string newname = pi.name.str(ctx); @@ -1049,7 +1139,24 @@ static void pack_special(Context *ctx) } else if (is_sb_ledda_ip(ctx, ci)) { /* Force placement (no choices anyway) */ cell_place_unique(ctx, ci); - + } else if (is_sb_i2c(ctx, ci) || is_sb_spi(ctx, ci)) { + const std::map<std::tuple<IdString, std::string>, Loc> map_ba74 = { + {std::make_tuple(id_SB_SPI, "0b0000"), Loc(0, 0, 0)}, + {std::make_tuple(id_SB_I2C, "0b0001"), Loc(0, 31, 0)}, + {std::make_tuple(id_SB_SPI, "0b0010"), Loc(25, 0, 1)}, + {std::make_tuple(id_SB_I2C, "0b0011"), Loc(25, 31, 0)}, + }; + if (map_ba74.find(std::make_tuple(ci->type, ci->params[ctx->id("BUS_ADDR74")])) == map_ba74.end()) + log_error("Invalid value for BUS_ADDR74 for cell '%s' of type '%s'\n", ci->name.c_str(ctx), + ci->type.c_str(ctx)); + Loc bel_loc = map_ba74.at(std::make_tuple(ci->type, ci->params[ctx->id("BUS_ADDR74")])); + BelId bel = ctx->getBelByLocation(bel_loc); + if (bel == BelId() || ctx->getBelType(bel) != ci->type) + log_error("Unable to find placement for cell '%s' of type '%s'\n", ci->name.c_str(ctx), + ci->type.c_str(ctx)); + IdString bel_name = ctx->getBelName(bel); + ci->attrs[ctx->id("BEL")] = bel_name.str(ctx); + log_info(" constrained %s '%s' to %s\n", ci->type.c_str(ctx), ci->name.c_str(ctx), bel_name.c_str(ctx)); } else if (is_sb_pll40(ctx, ci)) { bool is_pad = is_sb_pll40_pad(ctx, ci); bool is_core = !is_pad; @@ -1058,7 +1165,12 @@ static void pack_special(Context *ctx) create_ice_cell(ctx, ctx->id("ICESTORM_PLL"), ci->name.str(ctx) + "_PLL"); packed->attrs[ctx->id("TYPE")] = ci->type.str(ctx); packed_cells.insert(ci->name); - + if (!is_sb_pll40_dual(ctx, ci)) { + // Remove second output, so a buffer isn't created for it, for these + // cell types with only one output + packed->ports.erase(ctx->id("PLLOUT_B")); + packed->ports.erase(ctx->id("PLLOUT_B_GLOBAL")); + } for (auto attr : ci->attrs) packed->attrs[attr.first] = attr.second; for (auto param : ci->params) @@ -1083,13 +1195,17 @@ static void pack_special(Context *ctx) } auto feedback_path = packed->params[ctx->id("FEEDBACK_PATH")]; - packed->params[ctx->id("FEEDBACK_PATH")] = - feedback_path == "DELAY" - ? "0" - : feedback_path == "SIMPLE" ? "1" - : feedback_path == "PHASE_AND_DELAY" - ? "2" - : feedback_path == "EXTERNAL" ? "6" : feedback_path; + std::string fbp_value = feedback_path == "DELAY" + ? "0" + : feedback_path == "SIMPLE" + ? "1" + : feedback_path == "PHASE_AND_DELAY" + ? "2" + : feedback_path == "EXTERNAL" ? "6" : feedback_path; + if (!std::all_of(fbp_value.begin(), fbp_value.end(), isdigit)) + log_error("PLL '%s' has unsupported FEEDBACK_PATH value '%s'\n", ci->name.c_str(ctx), + feedback_path.c_str()); + packed->params[ctx->id("FEEDBACK_PATH")] = fbp_value; packed->params[ctx->id("PLLTYPE")] = std::to_string(sb_pll40_type(ctx, ci)); NetInfo *pad_packagepin_net = nullptr; @@ -1177,20 +1293,26 @@ static void pack_special(Context *ctx) log_info(" PLL '%s' has LOCK output, need to pass all outputs via LUT\n", ci->name.c_str(ctx)); bool found_lut = false; bool all_luts = true; + bool found_carry = false; unsigned int lut_count = 0; for (const auto &user : port.net->users) { NPNR_ASSERT(user.cell != nullptr); if (user.cell->type == ctx->id("ICESTORM_LC")) { - found_lut = true; - lut_count++; + if (bool_or_default(user.cell->params, ctx->id("CARRY_ENABLE"), false)) { + found_carry = true; + all_luts = false; + } else { + found_lut = true; + lut_count++; + } } else { all_luts = false; } } - if (found_lut && all_luts) { + if (found_lut && all_luts && lut_count < 8) { // Every user is a LUT, carry on now. - } else if (found_lut && !all_luts && lut_count < 8) { + } else if (found_lut && !all_luts && !found_carry && lut_count < 8) { // Strategy: create a pass-through LUT, move all non-LUT users behind it. log_info(" LUT strategy for %s: move non-LUT users to new LUT\n", port.name.c_str(ctx)); auto pt = spliceLUT(ctx, packed.get(), port.name, true); @@ -1237,10 +1359,20 @@ static void pack_special(Context *ctx) else continue; - std::unique_ptr<CellInfo> gb = - create_padin_gbuf(ctx, packed.get(), pi.name, - "$gbuf_" + ci->name.str(ctx) + "_pllout_" + (is_b_port ? "b" : "a")); - new_cells.push_back(std::move(gb)); + // Only if there is actually a net ... + if (pi.net != nullptr) { + // ... and it's used + if (pi.net->users.size() > 0) { + std::unique_ptr<CellInfo> gb = + create_padin_gbuf(ctx, packed.get(), pi.name, + "$gbuf_" + ci->name.str(ctx) + "_pllout_" + (is_b_port ? "b" : "a")); + new_cells.push_back(std::move(gb)); + } else { + // If not, remove it to avoid routing issues + ctx->nets.erase(pi.net->name); + packed->ports[pi.name].net = nullptr; + } + } } new_cells.push_back(std::move(packed)); diff --git a/ice40/pcf.cc b/ice40/pcf.cc index ce453af9..a8273dd6 100644 --- a/ice40/pcf.cc +++ b/ice40/pcf.cc @@ -21,6 +21,7 @@ #include "pcf.h" #include <sstream> #include "log.h" +#include "util.h" NEXTPNR_NAMESPACE_BEGIN @@ -47,17 +48,43 @@ bool apply_pcf(Context *ctx, std::string filename, std::istream &in) if (words.size() == 0) continue; std::string cmd = words.at(0); + bool nowarn = false; if (cmd == "set_io") { size_t args_end = 1; - while (args_end < words.size() && words.at(args_end).at(0) == '-') + std::vector<std::pair<IdString, std::string>> extra_attrs; + while (args_end < words.size() && words.at(args_end).at(0) == '-') { + const auto &setting = words.at(args_end); + if (setting == "-pullup") { + const auto &value = words.at(++args_end); + if (value == "yes" || value == "1") + extra_attrs.emplace_back(std::make_pair(ctx->id("PULLUP"), "1")); + else if (value == "no" || value == "0") + extra_attrs.emplace_back(std::make_pair(ctx->id("PULLUP"), "0")); + else + log_error("Invalid value '%s' for -pullup (on line %d)\n", value.c_str(), lineno); + } else if (setting == "-pullup_resistor") { + const auto &value = words.at(++args_end); + if (ctx->args.type != ArchArgs::UP5K) + log_error("Pullup resistance can only be set on UP5K (on line %d)\n", lineno); + if (value != "3P3K" && value != "6P8K" && value != "10K" && value != "100K") + log_error("Invalid value '%s' for -pullup_resistor (on line %d)\n", value.c_str(), lineno); + extra_attrs.emplace_back(std::make_pair(ctx->id("PULLUP_RESISTOR"), value)); + } else if (setting == "-nowarn") { + nowarn = true; + } else if (setting == "--warn-no-port") { + } else { + log_warning("Ignoring PCF setting '%s' (on line %d)\n", setting.c_str(), lineno); + } args_end++; + } if (args_end >= words.size() - 1) log_error("expected PCF syntax 'set_io cell pin' (on line %d)\n", lineno); std::string cell = words.at(args_end); std::string pin = words.at(args_end + 1); auto fnd_cell = ctx->cells.find(ctx->id(cell)); if (fnd_cell == ctx->cells.end()) { - log_warning("unmatched constraint '%s' (on line %d)\n", cell.c_str(), lineno); + if (!nowarn) + log_warning("unmatched constraint '%s' (on line %d)\n", cell.c_str(), lineno); } else { BelId pin_bel = ctx->getPackagePinBel(pin); if (pin_bel == BelId()) @@ -67,11 +94,28 @@ bool apply_pcf(Context *ctx, std::string filename, std::istream &in) fnd_cell->second->attrs[ctx->id("BEL")] = ctx->getBelName(pin_bel).str(ctx); log_info("constrained '%s' to bel '%s'\n", cell.c_str(), fnd_cell->second->attrs[ctx->id("BEL")].c_str()); + for (const auto &attr : extra_attrs) + fnd_cell->second->attrs[attr.first] = attr.second; } } else { log_error("unsupported PCF command '%s' (on line %d)\n", cmd.c_str(), lineno); } } + for (auto cell : sorted(ctx->cells)) { + CellInfo *ci = cell.second; + if (ci->type == ctx->id("$nextpnr_ibuf") || ci->type == ctx->id("$nextpnr_obuf") || + ci->type == ctx->id("$nextpnr_iobuf")) { + if (!ci->attrs.count(ctx->id("BEL"))) { + if (bool_or_default(ctx->settings, ctx->id("pcf_allow_unconstrained"))) + log_warning("IO '%s' is unconstrained in PCF and will be automatically placed\n", + cell.first.c_str(ctx)); + else + log_error("IO '%s' is unconstrained in PCF (override this error with " + "--pcf-allow-unconstrained)\n", + cell.first.c_str(ctx)); + } + } + } ctx->settings.emplace(ctx->id("input/pcf"), filename); return true; } catch (log_execution_error_exception) { diff --git a/ice40/picorv32_benchmark.py b/ice40/picorv32_benchmark.py index a4ec581e..5e4fc2e1 100755 --- a/ice40/picorv32_benchmark.py +++ b/ice40/picorv32_benchmark.py @@ -22,7 +22,7 @@ for i in range(num_runs): ascfile = "picorv32_work/picorv32_s{}.asc".format(run) if path.exists(ascfile): os.remove(ascfile) - result = subprocess.run(["../nextpnr-ice40", "--hx8k", "--seed", str(run), "--json", "picorv32.json", "--asc", ascfile, "--freq", "70"], stderr=subprocess.DEVNULL, stdout=subprocess.DEVNULL) + result = subprocess.run(["../nextpnr-ice40", "--hx8k", "--seed", str(run), "--json", "picorv32.json", "--asc", ascfile, "--freq", "40", "--opt-timing"], stderr=subprocess.DEVNULL, stdout=subprocess.DEVNULL) if result.returncode != 0: print("Run {} failed!".format(run)) else: diff --git a/ice40/project.cc b/ice40/project.cc index 47c0903d..bbd82fd7 100644 --- a/ice40/project.cc +++ b/ice40/project.cc @@ -56,6 +56,9 @@ std::unique_ptr<Context> ProjectHandler::createContext(pt::ptree &root) if (arch_type == "up5k") { chipArgs.type = ArchArgs::UP5K; } + if (arch_type == "u4k") { + chipArgs.type = ArchArgs::U4K; + } chipArgs.package = root.get<std::string>("project.arch.package"); return std::unique_ptr<Context>(new Context(chipArgs)); diff --git a/ice40/resource/chipdb.rc b/ice40/resource/chipdb.rc index a6f2dbe8..46459538 100644 --- a/ice40/resource/chipdb.rc +++ b/ice40/resource/chipdb.rc @@ -3,4 +3,5 @@ IDR_CHIPDB_384 BINARYFILE "..\chipdbs\chipdb-384.bin" IDR_CHIPDB_1K BINARYFILE "..\chipdbs\chipdb-1k.bin" IDR_CHIPDB_5K BINARYFILE "..\chipdbs\chipdb-5k.bin" +IDR_CHIPDB_U4K BINARYFILE "..\chipdbs\chipdb-u4k.bin" IDR_CHIPDB_8K BINARYFILE "..\chipdbs\chipdb-8k.bin" diff --git a/ice40/resource/embed.cc b/ice40/resource/embed.cc index 74f2eee9..048ac474 100644 --- a/ice40/resource/embed.cc +++ b/ice40/resource/embed.cc @@ -8,6 +8,7 @@ NEXTPNR_NAMESPACE_BEGIN const char *chipdb_blob_384; const char *chipdb_blob_1k; const char *chipdb_blob_5k; +const char *chipdb_blob_u4k; const char *chipdb_blob_8k; const char *LoadFileInResource(int name, int type, DWORD &size) @@ -24,7 +25,8 @@ void load_chipdb() chipdb_blob_384 = LoadFileInResource(IDR_CHIPDB_384, BINARYFILE, size); chipdb_blob_1k = LoadFileInResource(IDR_CHIPDB_1K, BINARYFILE, size); chipdb_blob_5k = LoadFileInResource(IDR_CHIPDB_5K, BINARYFILE, size); + chipdb_blob_u4k = LoadFileInResource(IDR_CHIPDB_U4K, BINARYFILE, size); chipdb_blob_8k = LoadFileInResource(IDR_CHIPDB_8K, BINARYFILE, size); } -NEXTPNR_NAMESPACE_END
\ No newline at end of file +NEXTPNR_NAMESPACE_END diff --git a/ice40/resource/resource.h b/ice40/resource/resource.h index 46997ae5..4dacbf61 100644 --- a/ice40/resource/resource.h +++ b/ice40/resource/resource.h @@ -3,3 +3,4 @@ #define IDR_CHIPDB_1K 102 #define IDR_CHIPDB_5K 103 #define IDR_CHIPDB_8K 104 +#define IDR_CHIPDB_U4K 105 diff --git a/ice40/smoketest/attosoc/.gitignore b/ice40/smoketest/attosoc/.gitignore new file mode 100644 index 00000000..7acb082f --- /dev/null +++ b/ice40/smoketest/attosoc/.gitignore @@ -0,0 +1,6 @@ +attosoc_pnr.v +attosoc.asc +attosoc.json +attosoc_pnr_tb +testbench.vcd +output.txt diff --git a/ice40/smoketest/attosoc/attosoc.pcf b/ice40/smoketest/attosoc/attosoc.pcf new file mode 100644 index 00000000..4f283d45 --- /dev/null +++ b/ice40/smoketest/attosoc/attosoc.pcf @@ -0,0 +1,10 @@ +set_io clk E4 +set_io led[0] B2 +set_io led[1] F5 +set_io led[2] B1 +set_io led[3] C1 +set_io led[4] C2 +set_io led[5] F4 +set_io led[6] D2 +set_io led[7] G5 + diff --git a/ice40/smoketest/attosoc/attosoc.v b/ice40/smoketest/attosoc/attosoc.v new file mode 100644 index 00000000..4921e298 --- /dev/null +++ b/ice40/smoketest/attosoc/attosoc.v @@ -0,0 +1,127 @@ +/* + * ECP5 PicoRV32 demo + * + * Copyright (C) 2017 Clifford Wolf <clifford@clifford.at> + * Copyright (C) 2018 David Shah <dave@ds0.me> + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +`ifdef PICORV32_V +`error "attosoc.v must be read before picorv32.v!" +`endif + +`define PICORV32_REGS picosoc_regs + +module attosoc ( + input clk, + output reg [7:0] led +); + + reg [5:0] reset_cnt = 0; + wire resetn = &reset_cnt; + + always @(posedge clk) begin + reset_cnt <= reset_cnt + !resetn; + end + + parameter integer MEM_WORDS = 256; + parameter [31:0] STACKADDR = (4*MEM_WORDS); // end of memory + parameter [31:0] PROGADDR_RESET = 32'h 0000_0000; // ROM at 0x0 + parameter integer ROM_BYTES = 256; + + reg [7:0] rom [0:ROM_BYTES-1]; + wire [31:0] rom_rdata = {rom[mem_addr+3], rom[mem_addr+2], rom[mem_addr+1], rom[mem_addr+0]}; + initial $readmemh("firmware.hex", rom); + + wire mem_valid; + wire mem_instr; + wire mem_ready; + wire [31:0] mem_addr; + wire [31:0] mem_wdata; + wire [3:0] mem_wstrb; + wire [31:0] mem_rdata; + + wire rom_ready = mem_valid && mem_addr[31:24] == 8'h00; + + wire iomem_valid; + wire iomem_ready; + wire [31:0] iomem_addr; + wire [31:0] iomem_wdata; + wire [3:0] iomem_wstrb; + wire [31:0] iomem_rdata; + + assign iomem_valid = mem_valid && (mem_addr[31:24] > 8'h 01); + assign iomem_ready = 1'b1; + assign iomem_wstrb = mem_wstrb; + assign iomem_addr = mem_addr; + assign iomem_wdata = mem_wdata; + + wire [31:0] spimemio_cfgreg_do; + + + always @(posedge clk) + if (iomem_valid && iomem_wstrb[0]) + led <= iomem_wdata[7:0]; + + assign mem_ready = (iomem_valid && iomem_ready) || rom_ready; + + assign mem_rdata = rom_rdata; + + picorv32 #( + .STACKADDR(STACKADDR), + .PROGADDR_RESET(PROGADDR_RESET), + .PROGADDR_IRQ(32'h 0000_0000), + .BARREL_SHIFTER(0), + .COMPRESSED_ISA(0), + .ENABLE_MUL(0), + .ENABLE_DIV(0), + .ENABLE_IRQ(0), + .ENABLE_IRQ_QREGS(0) + ) cpu ( + .clk (clk ), + .resetn (resetn ), + .mem_valid (mem_valid ), + .mem_instr (mem_instr ), + .mem_ready (mem_ready ), + .mem_addr (mem_addr ), + .mem_wdata (mem_wdata ), + .mem_wstrb (mem_wstrb ), + .mem_rdata (mem_rdata ) + ); + + + +endmodule + +// Implementation note: +// Replace the following two modules with wrappers for your SRAM cells. + +module picosoc_regs ( + input clk, wen, + input [5:0] waddr, + input [5:0] raddr1, + input [5:0] raddr2, + input [31:0] wdata, + output [31:0] rdata1, + output [31:0] rdata2 +); + reg [31:0] regs [0:31]; + + always @(posedge clk) + if (wen) regs[waddr[4:0]] <= wdata; + + assign rdata1 = regs[raddr1[4:0]]; + assign rdata2 = regs[raddr2[4:0]]; +endmodule diff --git a/ice40/smoketest/attosoc/attosoc_tb.v b/ice40/smoketest/attosoc/attosoc_tb.v new file mode 100644 index 00000000..65496fcd --- /dev/null +++ b/ice40/smoketest/attosoc/attosoc_tb.v @@ -0,0 +1,32 @@ +module testbench(); + integer out; + reg clk; + + always #5 clk = (clk === 1'b0); + + initial begin + out = $fopen("output.txt","w"); + $dumpfile("testbench.vcd"); + $dumpvars(0, testbench); + + repeat (100) begin + repeat (256) @(posedge clk); + $display("+256 cycles"); + end + $fclose(out); + #100; + $finish; + end + + wire [7:0] led; + + always @(led) begin + #1 $display("%b", led); + $fwrite(out, "%b\n", led); + end + + attosoc uut ( + .clk (clk ), + .led (led ) + ); +endmodule diff --git a/ice40/smoketest/attosoc/firmware.hex b/ice40/smoketest/attosoc/firmware.hex new file mode 100644 index 00000000..dfa64022 --- /dev/null +++ b/ice40/smoketest/attosoc/firmware.hex @@ -0,0 +1,6 @@ +@00000000
+13 04 10 00 B7 04 00 02 93 09 00 10 13 04 14 00
+63 44 34 01 13 04 20 00 13 09 20 00 63 5E 89 00
+13 05 04 00 93 05 09 00 EF 00 80 01 63 08 05 00
+13 09 19 00 6F F0 9F FE 23 A0 84 00 6F F0 1F FD
+93 02 10 00 33 05 B5 40 E3 5E 55 FE 67 80 00 00
diff --git a/ice40/smoketest/attosoc/golden.txt b/ice40/smoketest/attosoc/golden.txt new file mode 100644 index 00000000..0c92568d --- /dev/null +++ b/ice40/smoketest/attosoc/golden.txt @@ -0,0 +1,16 @@ +00000000 +00000010 +00000011 +00000101 +00000111 +00001011 +00001101 +00010001 +00010011 +00010111 +00011101 +00011111 +00100101 +00101001 +00101011 +00101111 diff --git a/ice40/smoketest/attosoc/picorv32.v b/ice40/smoketest/attosoc/picorv32.v new file mode 100644 index 00000000..1aed4121 --- /dev/null +++ b/ice40/smoketest/attosoc/picorv32.v @@ -0,0 +1,2979 @@ +/* + * PicoRV32 -- A Small RISC-V (RV32I) Processor Core + * + * Copyright (C) 2015 Clifford Wolf <clifford@clifford.at> + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +`timescale 1 ns / 1 ps +// `default_nettype none +// `define DEBUGNETS +// `define DEBUGREGS +// `define DEBUGASM +// `define DEBUG + +`ifdef DEBUG + `define debug(debug_command) debug_command +`else + `define debug(debug_command) +`endif + +`ifdef FORMAL + `define FORMAL_KEEP (* keep *) + `define assert(assert_expr) assert(assert_expr) +`else + `ifdef DEBUGNETS + `define FORMAL_KEEP (* keep *) + `else + `define FORMAL_KEEP + `endif + `define assert(assert_expr) empty_statement +`endif + +// uncomment this for register file in extra module +// `define PICORV32_REGS picorv32_regs + +// this macro can be used to check if the verilog files in your +// design are read in the correct order. +`define PICORV32_V + + +/*************************************************************** + * picorv32 + ***************************************************************/ + +module picorv32 #( + parameter [ 0:0] ENABLE_COUNTERS = 1, + parameter [ 0:0] ENABLE_COUNTERS64 = 1, + parameter [ 0:0] ENABLE_REGS_16_31 = 1, + parameter [ 0:0] ENABLE_REGS_DUALPORT = 1, + parameter [ 0:0] LATCHED_MEM_RDATA = 0, + parameter [ 0:0] TWO_STAGE_SHIFT = 1, + parameter [ 0:0] BARREL_SHIFTER = 0, + parameter [ 0:0] TWO_CYCLE_COMPARE = 0, + parameter [ 0:0] TWO_CYCLE_ALU = 0, + parameter [ 0:0] COMPRESSED_ISA = 0, + parameter [ 0:0] CATCH_MISALIGN = 1, + parameter [ 0:0] CATCH_ILLINSN = 1, + parameter [ 0:0] ENABLE_PCPI = 0, + parameter [ 0:0] ENABLE_MUL = 0, + parameter [ 0:0] ENABLE_FAST_MUL = 0, + parameter [ 0:0] ENABLE_DIV = 0, + parameter [ 0:0] ENABLE_IRQ = 0, + parameter [ 0:0] ENABLE_IRQ_QREGS = 1, + parameter [ 0:0] ENABLE_IRQ_TIMER = 1, + parameter [ 0:0] ENABLE_TRACE = 0, + parameter [ 0:0] REGS_INIT_ZERO = 0, + parameter [31:0] MASKED_IRQ = 32'h 0000_0000, + parameter [31:0] LATCHED_IRQ = 32'h ffff_ffff, + parameter [31:0] PROGADDR_RESET = 32'h 0000_0000, + parameter [31:0] PROGADDR_IRQ = 32'h 0000_0010, + parameter [31:0] STACKADDR = 32'h ffff_ffff +) ( + input clk, resetn, + output reg trap, + + output reg mem_valid, + output reg mem_instr, + input mem_ready, + + output reg [31:0] mem_addr, + output reg [31:0] mem_wdata, + output reg [ 3:0] mem_wstrb, + input [31:0] mem_rdata, + + // Look-Ahead Interface + output mem_la_read, + output mem_la_write, + output [31:0] mem_la_addr, + output reg [31:0] mem_la_wdata, + output reg [ 3:0] mem_la_wstrb, + + // Pico Co-Processor Interface (PCPI) + output reg pcpi_valid, + output reg [31:0] pcpi_insn, + output [31:0] pcpi_rs1, + output [31:0] pcpi_rs2, + input pcpi_wr, + input [31:0] pcpi_rd, + input pcpi_wait, + input pcpi_ready, + + // IRQ Interface + input [31:0] irq, + output reg [31:0] eoi, + +`ifdef RISCV_FORMAL + output reg rvfi_valid, + output reg [63:0] rvfi_order, + output reg [31:0] rvfi_insn, + output reg rvfi_trap, + output reg rvfi_halt, + output reg rvfi_intr, + output reg [ 1:0] rvfi_mode, + output reg [ 4:0] rvfi_rs1_addr, + output reg [ 4:0] rvfi_rs2_addr, + output reg [31:0] rvfi_rs1_rdata, + output reg [31:0] rvfi_rs2_rdata, + output reg [ 4:0] rvfi_rd_addr, + output reg [31:0] rvfi_rd_wdata, + output reg [31:0] rvfi_pc_rdata, + output reg [31:0] rvfi_pc_wdata, + output reg [31:0] rvfi_mem_addr, + output reg [ 3:0] rvfi_mem_rmask, + output reg [ 3:0] rvfi_mem_wmask, + output reg [31:0] rvfi_mem_rdata, + output reg [31:0] rvfi_mem_wdata, +`endif + + // Trace Interface + output reg trace_valid, + output reg [35:0] trace_data +); + localparam integer irq_timer = 0; + localparam integer irq_ebreak = 1; + localparam integer irq_buserror = 2; + + localparam integer irqregs_offset = ENABLE_REGS_16_31 ? 32 : 16; + localparam integer regfile_size = (ENABLE_REGS_16_31 ? 32 : 16) + 4*ENABLE_IRQ*ENABLE_IRQ_QREGS; + localparam integer regindex_bits = (ENABLE_REGS_16_31 ? 5 : 4) + ENABLE_IRQ*ENABLE_IRQ_QREGS; + + localparam WITH_PCPI = ENABLE_PCPI || ENABLE_MUL || ENABLE_FAST_MUL || ENABLE_DIV; + + localparam [35:0] TRACE_BRANCH = {4'b 0001, 32'b 0}; + localparam [35:0] TRACE_ADDR = {4'b 0010, 32'b 0}; + localparam [35:0] TRACE_IRQ = {4'b 1000, 32'b 0}; + + reg [63:0] count_cycle, count_instr; + reg [31:0] reg_pc, reg_next_pc, reg_op1, reg_op2, reg_out; + reg [4:0] reg_sh; + + reg [31:0] next_insn_opcode; + reg [31:0] dbg_insn_opcode; + reg [31:0] dbg_insn_addr; + + wire dbg_mem_valid = mem_valid; + wire dbg_mem_instr = mem_instr; + wire dbg_mem_ready = mem_ready; + wire [31:0] dbg_mem_addr = mem_addr; + wire [31:0] dbg_mem_wdata = mem_wdata; + wire [ 3:0] dbg_mem_wstrb = mem_wstrb; + wire [31:0] dbg_mem_rdata = mem_rdata; + + assign pcpi_rs1 = reg_op1; + assign pcpi_rs2 = reg_op2; + + wire [31:0] next_pc; + + reg irq_delay; + reg irq_active; + reg [31:0] irq_mask; + reg [31:0] irq_pending; + reg [31:0] timer; + +`ifndef PICORV32_REGS + reg [31:0] cpuregs [0:regfile_size-1]; + + integer i; + initial begin + if (REGS_INIT_ZERO) begin + for (i = 0; i < regfile_size; i = i+1) + cpuregs[i] = 0; + end + end +`endif + + task empty_statement; + // This task is used by the `assert directive in non-formal mode to + // avoid empty statement (which are unsupported by plain Verilog syntax). + begin end + endtask + +`ifdef DEBUGREGS + wire [31:0] dbg_reg_x0 = 0; + wire [31:0] dbg_reg_x1 = cpuregs[1]; + wire [31:0] dbg_reg_x2 = cpuregs[2]; + wire [31:0] dbg_reg_x3 = cpuregs[3]; + wire [31:0] dbg_reg_x4 = cpuregs[4]; + wire [31:0] dbg_reg_x5 = cpuregs[5]; + wire [31:0] dbg_reg_x6 = cpuregs[6]; + wire [31:0] dbg_reg_x7 = cpuregs[7]; + wire [31:0] dbg_reg_x8 = cpuregs[8]; + wire [31:0] dbg_reg_x9 = cpuregs[9]; + wire [31:0] dbg_reg_x10 = cpuregs[10]; + wire [31:0] dbg_reg_x11 = cpuregs[11]; + wire [31:0] dbg_reg_x12 = cpuregs[12]; + wire [31:0] dbg_reg_x13 = cpuregs[13]; + wire [31:0] dbg_reg_x14 = cpuregs[14]; + wire [31:0] dbg_reg_x15 = cpuregs[15]; + wire [31:0] dbg_reg_x16 = cpuregs[16]; + wire [31:0] dbg_reg_x17 = cpuregs[17]; + wire [31:0] dbg_reg_x18 = cpuregs[18]; + wire [31:0] dbg_reg_x19 = cpuregs[19]; + wire [31:0] dbg_reg_x20 = cpuregs[20]; + wire [31:0] dbg_reg_x21 = cpuregs[21]; + wire [31:0] dbg_reg_x22 = cpuregs[22]; + wire [31:0] dbg_reg_x23 = cpuregs[23]; + wire [31:0] dbg_reg_x24 = cpuregs[24]; + wire [31:0] dbg_reg_x25 = cpuregs[25]; + wire [31:0] dbg_reg_x26 = cpuregs[26]; + wire [31:0] dbg_reg_x27 = cpuregs[27]; + wire [31:0] dbg_reg_x28 = cpuregs[28]; + wire [31:0] dbg_reg_x29 = cpuregs[29]; + wire [31:0] dbg_reg_x30 = cpuregs[30]; + wire [31:0] dbg_reg_x31 = cpuregs[31]; +`endif + + // Internal PCPI Cores + + wire pcpi_mul_wr; + wire [31:0] pcpi_mul_rd; + wire pcpi_mul_wait; + wire pcpi_mul_ready; + + wire pcpi_div_wr; + wire [31:0] pcpi_div_rd; + wire pcpi_div_wait; + wire pcpi_div_ready; + + reg pcpi_int_wr; + reg [31:0] pcpi_int_rd; + reg pcpi_int_wait; + reg pcpi_int_ready; + + generate if (ENABLE_FAST_MUL) begin + picorv32_pcpi_fast_mul pcpi_mul ( + .clk (clk ), + .resetn (resetn ), + .pcpi_valid(pcpi_valid ), + .pcpi_insn (pcpi_insn ), + .pcpi_rs1 (pcpi_rs1 ), + .pcpi_rs2 (pcpi_rs2 ), + .pcpi_wr (pcpi_mul_wr ), + .pcpi_rd (pcpi_mul_rd ), + .pcpi_wait (pcpi_mul_wait ), + .pcpi_ready(pcpi_mul_ready ) + ); + end else if (ENABLE_MUL) begin + picorv32_pcpi_mul pcpi_mul ( + .clk (clk ), + .resetn (resetn ), + .pcpi_valid(pcpi_valid ), + .pcpi_insn (pcpi_insn ), + .pcpi_rs1 (pcpi_rs1 ), + .pcpi_rs2 (pcpi_rs2 ), + .pcpi_wr (pcpi_mul_wr ), + .pcpi_rd (pcpi_mul_rd ), + .pcpi_wait (pcpi_mul_wait ), + .pcpi_ready(pcpi_mul_ready ) + ); + end else begin + assign pcpi_mul_wr = 0; + assign pcpi_mul_rd = 32'bx; + assign pcpi_mul_wait = 0; + assign pcpi_mul_ready = 0; + end endgenerate + + generate if (ENABLE_DIV) begin + picorv32_pcpi_div pcpi_div ( + .clk (clk ), + .resetn (resetn ), + .pcpi_valid(pcpi_valid ), + .pcpi_insn (pcpi_insn ), + .pcpi_rs1 (pcpi_rs1 ), + .pcpi_rs2 (pcpi_rs2 ), + .pcpi_wr (pcpi_div_wr ), + .pcpi_rd (pcpi_div_rd ), + .pcpi_wait (pcpi_div_wait ), + .pcpi_ready(pcpi_div_ready ) + ); + end else begin + assign pcpi_div_wr = 0; + assign pcpi_div_rd = 32'bx; + assign pcpi_div_wait = 0; + assign pcpi_div_ready = 0; + end endgenerate + + always @* begin + pcpi_int_wr = 0; + pcpi_int_rd = 32'bx; + pcpi_int_wait = |{ENABLE_PCPI && pcpi_wait, (ENABLE_MUL || ENABLE_FAST_MUL) && pcpi_mul_wait, ENABLE_DIV && pcpi_div_wait}; + pcpi_int_ready = |{ENABLE_PCPI && pcpi_ready, (ENABLE_MUL || ENABLE_FAST_MUL) && pcpi_mul_ready, ENABLE_DIV && pcpi_div_ready}; + + (* parallel_case *) + case (1'b1) + ENABLE_PCPI && pcpi_ready: begin + pcpi_int_wr = ENABLE_PCPI ? pcpi_wr : 0; + pcpi_int_rd = ENABLE_PCPI ? pcpi_rd : 0; + end + (ENABLE_MUL || ENABLE_FAST_MUL) && pcpi_mul_ready: begin + pcpi_int_wr = pcpi_mul_wr; + pcpi_int_rd = pcpi_mul_rd; + end + ENABLE_DIV && pcpi_div_ready: begin + pcpi_int_wr = pcpi_div_wr; + pcpi_int_rd = pcpi_div_rd; + end + endcase + end + + + // Memory Interface + + reg [1:0] mem_state; + reg [1:0] mem_wordsize; + reg [31:0] mem_rdata_word; + reg [31:0] mem_rdata_q; + reg mem_do_prefetch; + reg mem_do_rinst; + reg mem_do_rdata; + reg mem_do_wdata; + + wire mem_xfer; + reg mem_la_secondword, mem_la_firstword_reg, last_mem_valid; + wire mem_la_firstword = COMPRESSED_ISA && (mem_do_prefetch || mem_do_rinst) && next_pc[1] && !mem_la_secondword; + wire mem_la_firstword_xfer = COMPRESSED_ISA && mem_xfer && (!last_mem_valid ? mem_la_firstword : mem_la_firstword_reg); + + reg prefetched_high_word; + reg clear_prefetched_high_word; + reg [15:0] mem_16bit_buffer; + + wire [31:0] mem_rdata_latched_noshuffle; + wire [31:0] mem_rdata_latched; + + wire mem_la_use_prefetched_high_word = COMPRESSED_ISA && mem_la_firstword && prefetched_high_word && !clear_prefetched_high_word; + assign mem_xfer = (mem_valid && mem_ready) || (mem_la_use_prefetched_high_word && mem_do_rinst); + + wire mem_busy = |{mem_do_prefetch, mem_do_rinst, mem_do_rdata, mem_do_wdata}; + wire mem_done = resetn && ((mem_xfer && |mem_state && (mem_do_rinst || mem_do_rdata || mem_do_wdata)) || (&mem_state && mem_do_rinst)) && + (!mem_la_firstword || (~&mem_rdata_latched[1:0] && mem_xfer)); + + assign mem_la_write = resetn && !mem_state && mem_do_wdata; + assign mem_la_read = resetn && ((!mem_la_use_prefetched_high_word && !mem_state && (mem_do_rinst || mem_do_prefetch || mem_do_rdata)) || + (COMPRESSED_ISA && mem_xfer && (!last_mem_valid ? mem_la_firstword : mem_la_firstword_reg) && !mem_la_secondword && &mem_rdata_latched[1:0])); + assign mem_la_addr = (mem_do_prefetch || mem_do_rinst) ? {next_pc[31:2] + mem_la_firstword_xfer, 2'b00} : {reg_op1[31:2], 2'b00}; + + assign mem_rdata_latched_noshuffle = (mem_xfer || LATCHED_MEM_RDATA) ? mem_rdata : mem_rdata_q; + + assign mem_rdata_latched = COMPRESSED_ISA && mem_la_use_prefetched_high_word ? {16'bx, mem_16bit_buffer} : + COMPRESSED_ISA && mem_la_secondword ? {mem_rdata_latched_noshuffle[15:0], mem_16bit_buffer} : + COMPRESSED_ISA && mem_la_firstword ? {16'bx, mem_rdata_latched_noshuffle[31:16]} : mem_rdata_latched_noshuffle; + + always @(posedge clk) begin + if (!resetn) begin + mem_la_firstword_reg <= 0; + last_mem_valid <= 0; + end else begin + if (!last_mem_valid) + mem_la_firstword_reg <= mem_la_firstword; + last_mem_valid <= mem_valid && !mem_ready; + end + end + + always @* begin + (* full_case *) + case (mem_wordsize) + 0: begin + mem_la_wdata = reg_op2; + mem_la_wstrb = 4'b1111; + mem_rdata_word = mem_rdata; + end + 1: begin + mem_la_wdata = {2{reg_op2[15:0]}}; + mem_la_wstrb = reg_op1[1] ? 4'b1100 : 4'b0011; + case (reg_op1[1]) + 1'b0: mem_rdata_word = {16'b0, mem_rdata[15: 0]}; + 1'b1: mem_rdata_word = {16'b0, mem_rdata[31:16]}; + endcase + end + 2: begin + mem_la_wdata = {4{reg_op2[7:0]}}; + mem_la_wstrb = 4'b0001 << reg_op1[1:0]; + case (reg_op1[1:0]) + 2'b00: mem_rdata_word = {24'b0, mem_rdata[ 7: 0]}; + 2'b01: mem_rdata_word = {24'b0, mem_rdata[15: 8]}; + 2'b10: mem_rdata_word = {24'b0, mem_rdata[23:16]}; + 2'b11: mem_rdata_word = {24'b0, mem_rdata[31:24]}; + endcase + end + endcase + end + + always @(posedge clk) begin + if (mem_xfer) begin + mem_rdata_q <= COMPRESSED_ISA ? mem_rdata_latched : mem_rdata; + next_insn_opcode <= COMPRESSED_ISA ? mem_rdata_latched : mem_rdata; + end + + if (COMPRESSED_ISA && mem_done && (mem_do_prefetch || mem_do_rinst)) begin + case (mem_rdata_latched[1:0]) + 2'b00: begin // Quadrant 0 + case (mem_rdata_latched[15:13]) + 3'b000: begin // C.ADDI4SPN + mem_rdata_q[14:12] <= 3'b000; + mem_rdata_q[31:20] <= {2'b0, mem_rdata_latched[10:7], mem_rdata_latched[12:11], mem_rdata_latched[5], mem_rdata_latched[6], 2'b00}; + end + 3'b010: begin // C.LW + mem_rdata_q[31:20] <= {5'b0, mem_rdata_latched[5], mem_rdata_latched[12:10], mem_rdata_latched[6], 2'b00}; + mem_rdata_q[14:12] <= 3'b 010; + end + 3'b 110: begin // C.SW + {mem_rdata_q[31:25], mem_rdata_q[11:7]} <= {5'b0, mem_rdata_latched[5], mem_rdata_latched[12:10], mem_rdata_latched[6], 2'b00}; + mem_rdata_q[14:12] <= 3'b 010; + end + endcase + end + 2'b01: begin // Quadrant 1 + case (mem_rdata_latched[15:13]) + 3'b 000: begin // C.ADDI + mem_rdata_q[14:12] <= 3'b000; + mem_rdata_q[31:20] <= $signed({mem_rdata_latched[12], mem_rdata_latched[6:2]}); + end + 3'b 010: begin // C.LI + mem_rdata_q[14:12] <= 3'b000; + mem_rdata_q[31:20] <= $signed({mem_rdata_latched[12], mem_rdata_latched[6:2]}); + end + 3'b 011: begin + if (mem_rdata_latched[11:7] == 2) begin // C.ADDI16SP + mem_rdata_q[14:12] <= 3'b000; + mem_rdata_q[31:20] <= $signed({mem_rdata_latched[12], mem_rdata_latched[4:3], + mem_rdata_latched[5], mem_rdata_latched[2], mem_rdata_latched[6], 4'b 0000}); + end else begin // C.LUI + mem_rdata_q[31:12] <= $signed({mem_rdata_latched[12], mem_rdata_latched[6:2]}); + end + end + 3'b100: begin + if (mem_rdata_latched[11:10] == 2'b00) begin // C.SRLI + mem_rdata_q[31:25] <= 7'b0000000; + mem_rdata_q[14:12] <= 3'b 101; + end + if (mem_rdata_latched[11:10] == 2'b01) begin // C.SRAI + mem_rdata_q[31:25] <= 7'b0100000; + mem_rdata_q[14:12] <= 3'b 101; + end + if (mem_rdata_latched[11:10] == 2'b10) begin // C.ANDI + mem_rdata_q[14:12] <= 3'b111; + mem_rdata_q[31:20] <= $signed({mem_rdata_latched[12], mem_rdata_latched[6:2]}); + end + if (mem_rdata_latched[12:10] == 3'b011) begin // C.SUB, C.XOR, C.OR, C.AND + if (mem_rdata_latched[6:5] == 2'b00) mem_rdata_q[14:12] <= 3'b000; + if (mem_rdata_latched[6:5] == 2'b01) mem_rdata_q[14:12] <= 3'b100; + if (mem_rdata_latched[6:5] == 2'b10) mem_rdata_q[14:12] <= 3'b110; + if (mem_rdata_latched[6:5] == 2'b11) mem_rdata_q[14:12] <= 3'b111; + mem_rdata_q[31:25] <= mem_rdata_latched[6:5] == 2'b00 ? 7'b0100000 : 7'b0000000; + end + end + 3'b 110: begin // C.BEQZ + mem_rdata_q[14:12] <= 3'b000; + { mem_rdata_q[31], mem_rdata_q[7], mem_rdata_q[30:25], mem_rdata_q[11:8] } <= + $signed({mem_rdata_latched[12], mem_rdata_latched[6:5], mem_rdata_latched[2], + mem_rdata_latched[11:10], mem_rdata_latched[4:3]}); + end + 3'b 111: begin // C.BNEZ + mem_rdata_q[14:12] <= 3'b001; + { mem_rdata_q[31], mem_rdata_q[7], mem_rdata_q[30:25], mem_rdata_q[11:8] } <= + $signed({mem_rdata_latched[12], mem_rdata_latched[6:5], mem_rdata_latched[2], + mem_rdata_latched[11:10], mem_rdata_latched[4:3]}); + end + endcase + end + 2'b10: begin // Quadrant 2 + case (mem_rdata_latched[15:13]) + 3'b000: begin // C.SLLI + mem_rdata_q[31:25] <= 7'b0000000; + mem_rdata_q[14:12] <= 3'b 001; + end + 3'b010: begin // C.LWSP + mem_rdata_q[31:20] <= {4'b0, mem_rdata_latched[3:2], mem_rdata_latched[12], mem_rdata_latched[6:4], 2'b00}; + mem_rdata_q[14:12] <= 3'b 010; + end + 3'b100: begin + if (mem_rdata_latched[12] == 0 && mem_rdata_latched[6:2] == 0) begin // C.JR + mem_rdata_q[14:12] <= 3'b000; + mem_rdata_q[31:20] <= 12'b0; + end + if (mem_rdata_latched[12] == 0 && mem_rdata_latched[6:2] != 0) begin // C.MV + mem_rdata_q[14:12] <= 3'b000; + mem_rdata_q[31:25] <= 7'b0000000; + end + if (mem_rdata_latched[12] != 0 && mem_rdata_latched[11:7] != 0 && mem_rdata_latched[6:2] == 0) begin // C.JALR + mem_rdata_q[14:12] <= 3'b000; + mem_rdata_q[31:20] <= 12'b0; + end + if (mem_rdata_latched[12] != 0 && mem_rdata_latched[6:2] != 0) begin // C.ADD + mem_rdata_q[14:12] <= 3'b000; + mem_rdata_q[31:25] <= 7'b0000000; + end + end + 3'b110: begin // C.SWSP + {mem_rdata_q[31:25], mem_rdata_q[11:7]} <= {4'b0, mem_rdata_latched[8:7], mem_rdata_latched[12:9], 2'b00}; + mem_rdata_q[14:12] <= 3'b 010; + end + endcase + end + endcase + end + end + + always @(posedge clk) begin + if (resetn && !trap) begin + if (mem_do_prefetch || mem_do_rinst || mem_do_rdata) + `assert(!mem_do_wdata); + + if (mem_do_prefetch || mem_do_rinst) + `assert(!mem_do_rdata); + + if (mem_do_rdata) + `assert(!mem_do_prefetch && !mem_do_rinst); + + if (mem_do_wdata) + `assert(!(mem_do_prefetch || mem_do_rinst || mem_do_rdata)); + + if (mem_state == 2 || mem_state == 3) + `assert(mem_valid || mem_do_prefetch); + end + end + + always @(posedge clk) begin + if (!resetn || trap) begin + if (!resetn) + mem_state <= 0; + if (!resetn || mem_ready) + mem_valid <= 0; + mem_la_secondword <= 0; + prefetched_high_word <= 0; + end else begin + if (mem_la_read || mem_la_write) begin + mem_addr <= mem_la_addr; + mem_wstrb <= mem_la_wstrb & {4{mem_la_write}}; + end + if (mem_la_write) begin + mem_wdata <= mem_la_wdata; + end + case (mem_state) + 0: begin + if (mem_do_prefetch || mem_do_rinst || mem_do_rdata) begin + mem_valid <= !mem_la_use_prefetched_high_word; + mem_instr <= mem_do_prefetch || mem_do_rinst; + mem_wstrb <= 0; + mem_state <= 1; + end + if (mem_do_wdata) begin + mem_valid <= 1; + mem_instr <= 0; + mem_state <= 2; + end + end + 1: begin + `assert(mem_wstrb == 0); + `assert(mem_do_prefetch || mem_do_rinst || mem_do_rdata); + `assert(mem_valid == !mem_la_use_prefetched_high_word); + `assert(mem_instr == (mem_do_prefetch || mem_do_rinst)); + if (mem_xfer) begin + if (COMPRESSED_ISA && mem_la_read) begin + mem_valid <= 1; + mem_la_secondword <= 1; + if (!mem_la_use_prefetched_high_word) + mem_16bit_buffer <= mem_rdata[31:16]; + end else begin + mem_valid <= 0; + mem_la_secondword <= 0; + if (COMPRESSED_ISA && !mem_do_rdata) begin + if (~&mem_rdata[1:0] || mem_la_secondword) begin + mem_16bit_buffer <= mem_rdata[31:16]; + prefetched_high_word <= 1; + end else begin + prefetched_high_word <= 0; + end + end + mem_state <= mem_do_rinst || mem_do_rdata ? 0 : 3; + end + end + end + 2: begin + `assert(mem_wstrb != 0); + `assert(mem_do_wdata); + if (mem_xfer) begin + mem_valid <= 0; + mem_state <= 0; + end + end + 3: begin + `assert(mem_wstrb == 0); + `assert(mem_do_prefetch); + if (mem_do_rinst) begin + mem_state <= 0; + end + end + endcase + end + + if (clear_prefetched_high_word) + prefetched_high_word <= 0; + end + + + // Instruction Decoder + + reg instr_lui, instr_auipc, instr_jal, instr_jalr; + reg instr_beq, instr_bne, instr_blt, instr_bge, instr_bltu, instr_bgeu; + reg instr_lb, instr_lh, instr_lw, instr_lbu, instr_lhu, instr_sb, instr_sh, instr_sw; + reg instr_addi, instr_slti, instr_sltiu, instr_xori, instr_ori, instr_andi, instr_slli, instr_srli, instr_srai; + reg instr_add, instr_sub, instr_sll, instr_slt, instr_sltu, instr_xor, instr_srl, instr_sra, instr_or, instr_and; + reg instr_rdcycle, instr_rdcycleh, instr_rdinstr, instr_rdinstrh, instr_ecall_ebreak; + reg instr_getq, instr_setq, instr_retirq, instr_maskirq, instr_waitirq, instr_timer; + wire instr_trap; + + reg [regindex_bits-1:0] decoded_rd, decoded_rs1, decoded_rs2; + reg [31:0] decoded_imm, decoded_imm_uj; + reg decoder_trigger; + reg decoder_trigger_q; + reg decoder_pseudo_trigger; + reg decoder_pseudo_trigger_q; + reg compressed_instr; + + reg is_lui_auipc_jal; + reg is_lb_lh_lw_lbu_lhu; + reg is_slli_srli_srai; + reg is_jalr_addi_slti_sltiu_xori_ori_andi; + reg is_sb_sh_sw; + reg is_sll_srl_sra; + reg is_lui_auipc_jal_jalr_addi_add_sub; + reg is_slti_blt_slt; + reg is_sltiu_bltu_sltu; + reg is_beq_bne_blt_bge_bltu_bgeu; + reg is_lbu_lhu_lw; + reg is_alu_reg_imm; + reg is_alu_reg_reg; + reg is_compare; + + assign instr_trap = (CATCH_ILLINSN || WITH_PCPI) && !{instr_lui, instr_auipc, instr_jal, instr_jalr, + instr_beq, instr_bne, instr_blt, instr_bge, instr_bltu, instr_bgeu, + instr_lb, instr_lh, instr_lw, instr_lbu, instr_lhu, instr_sb, instr_sh, instr_sw, + instr_addi, instr_slti, instr_sltiu, instr_xori, instr_ori, instr_andi, instr_slli, instr_srli, instr_srai, + instr_add, instr_sub, instr_sll, instr_slt, instr_sltu, instr_xor, instr_srl, instr_sra, instr_or, instr_and, + instr_rdcycle, instr_rdcycleh, instr_rdinstr, instr_rdinstrh, + instr_getq, instr_setq, instr_retirq, instr_maskirq, instr_waitirq, instr_timer}; + + wire is_rdcycle_rdcycleh_rdinstr_rdinstrh; + assign is_rdcycle_rdcycleh_rdinstr_rdinstrh = |{instr_rdcycle, instr_rdcycleh, instr_rdinstr, instr_rdinstrh}; + + reg [63:0] new_ascii_instr; + `FORMAL_KEEP reg [63:0] dbg_ascii_instr; + `FORMAL_KEEP reg [31:0] dbg_insn_imm; + `FORMAL_KEEP reg [4:0] dbg_insn_rs1; + `FORMAL_KEEP reg [4:0] dbg_insn_rs2; + `FORMAL_KEEP reg [4:0] dbg_insn_rd; + `FORMAL_KEEP reg [31:0] dbg_rs1val; + `FORMAL_KEEP reg [31:0] dbg_rs2val; + `FORMAL_KEEP reg dbg_rs1val_valid; + `FORMAL_KEEP reg dbg_rs2val_valid; + + always @* begin + new_ascii_instr = ""; + + if (instr_lui) new_ascii_instr = "lui"; + if (instr_auipc) new_ascii_instr = "auipc"; + if (instr_jal) new_ascii_instr = "jal"; + if (instr_jalr) new_ascii_instr = "jalr"; + + if (instr_beq) new_ascii_instr = "beq"; + if (instr_bne) new_ascii_instr = "bne"; + if (instr_blt) new_ascii_instr = "blt"; + if (instr_bge) new_ascii_instr = "bge"; + if (instr_bltu) new_ascii_instr = "bltu"; + if (instr_bgeu) new_ascii_instr = "bgeu"; + + if (instr_lb) new_ascii_instr = "lb"; + if (instr_lh) new_ascii_instr = "lh"; + if (instr_lw) new_ascii_instr = "lw"; + if (instr_lbu) new_ascii_instr = "lbu"; + if (instr_lhu) new_ascii_instr = "lhu"; + if (instr_sb) new_ascii_instr = "sb"; + if (instr_sh) new_ascii_instr = "sh"; + if (instr_sw) new_ascii_instr = "sw"; + + if (instr_addi) new_ascii_instr = "addi"; + if (instr_slti) new_ascii_instr = "slti"; + if (instr_sltiu) new_ascii_instr = "sltiu"; + if (instr_xori) new_ascii_instr = "xori"; + if (instr_ori) new_ascii_instr = "ori"; + if (instr_andi) new_ascii_instr = "andi"; + if (instr_slli) new_ascii_instr = "slli"; + if (instr_srli) new_ascii_instr = "srli"; + if (instr_srai) new_ascii_instr = "srai"; + + if (instr_add) new_ascii_instr = "add"; + if (instr_sub) new_ascii_instr = "sub"; + if (instr_sll) new_ascii_instr = "sll"; + if (instr_slt) new_ascii_instr = "slt"; + if (instr_sltu) new_ascii_instr = "sltu"; + if (instr_xor) new_ascii_instr = "xor"; + if (instr_srl) new_ascii_instr = "srl"; + if (instr_sra) new_ascii_instr = "sra"; + if (instr_or) new_ascii_instr = "or"; + if (instr_and) new_ascii_instr = "and"; + + if (instr_rdcycle) new_ascii_instr = "rdcycle"; + if (instr_rdcycleh) new_ascii_instr = "rdcycleh"; + if (instr_rdinstr) new_ascii_instr = "rdinstr"; + if (instr_rdinstrh) new_ascii_instr = "rdinstrh"; + + if (instr_getq) new_ascii_instr = "getq"; + if (instr_setq) new_ascii_instr = "setq"; + if (instr_retirq) new_ascii_instr = "retirq"; + if (instr_maskirq) new_ascii_instr = "maskirq"; + if (instr_waitirq) new_ascii_instr = "waitirq"; + if (instr_timer) new_ascii_instr = "timer"; + end + + reg [63:0] q_ascii_instr; + reg [31:0] q_insn_imm; + reg [31:0] q_insn_opcode; + reg [4:0] q_insn_rs1; + reg [4:0] q_insn_rs2; + reg [4:0] q_insn_rd; + reg dbg_next; + + wire launch_next_insn; + reg dbg_valid_insn; + + reg [63:0] cached_ascii_instr; + reg [31:0] cached_insn_imm; + reg [31:0] cached_insn_opcode; + reg [4:0] cached_insn_rs1; + reg [4:0] cached_insn_rs2; + reg [4:0] cached_insn_rd; + + always @(posedge clk) begin + q_ascii_instr <= dbg_ascii_instr; + q_insn_imm <= dbg_insn_imm; + q_insn_opcode <= dbg_insn_opcode; + q_insn_rs1 <= dbg_insn_rs1; + q_insn_rs2 <= dbg_insn_rs2; + q_insn_rd <= dbg_insn_rd; + dbg_next <= launch_next_insn; + + if (!resetn || trap) + dbg_valid_insn <= 0; + else if (launch_next_insn) + dbg_valid_insn <= 1; + + if (decoder_trigger_q) begin + cached_ascii_instr <= new_ascii_instr; + cached_insn_imm <= decoded_imm; + if (&next_insn_opcode[1:0]) + cached_insn_opcode <= next_insn_opcode; + else + cached_insn_opcode <= {16'b0, next_insn_opcode[15:0]}; + cached_insn_rs1 <= decoded_rs1; + cached_insn_rs2 <= decoded_rs2; + cached_insn_rd <= decoded_rd; + end + + if (launch_next_insn) begin + dbg_insn_addr <= next_pc; + end + end + + always @* begin + dbg_ascii_instr = q_ascii_instr; + dbg_insn_imm = q_insn_imm; + dbg_insn_opcode = q_insn_opcode; + dbg_insn_rs1 = q_insn_rs1; + dbg_insn_rs2 = q_insn_rs2; + dbg_insn_rd = q_insn_rd; + + if (dbg_next) begin + if (decoder_pseudo_trigger_q) begin + dbg_ascii_instr = cached_ascii_instr; + dbg_insn_imm = cached_insn_imm; + dbg_insn_opcode = cached_insn_opcode; + dbg_insn_rs1 = cached_insn_rs1; + dbg_insn_rs2 = cached_insn_rs2; + dbg_insn_rd = cached_insn_rd; + end else begin + dbg_ascii_instr = new_ascii_instr; + if (&next_insn_opcode[1:0]) + dbg_insn_opcode = next_insn_opcode; + else + dbg_insn_opcode = {16'b0, next_insn_opcode[15:0]}; + dbg_insn_imm = decoded_imm; + dbg_insn_rs1 = decoded_rs1; + dbg_insn_rs2 = decoded_rs2; + dbg_insn_rd = decoded_rd; + end + end + end + +`ifdef DEBUGASM + always @(posedge clk) begin + if (dbg_next) begin + $display("debugasm %x %x %s", dbg_insn_addr, dbg_insn_opcode, dbg_ascii_instr ? dbg_ascii_instr : "*"); + end + end +`endif + +`ifdef DEBUG + always @(posedge clk) begin + if (dbg_next) begin + if (&dbg_insn_opcode[1:0]) + $display("DECODE: 0x%08x 0x%08x %-0s", dbg_insn_addr, dbg_insn_opcode, dbg_ascii_instr ? dbg_ascii_instr : "UNKNOWN"); + else + $display("DECODE: 0x%08x 0x%04x %-0s", dbg_insn_addr, dbg_insn_opcode[15:0], dbg_ascii_instr ? dbg_ascii_instr : "UNKNOWN"); + end + end +`endif + + always @(posedge clk) begin + is_lui_auipc_jal <= |{instr_lui, instr_auipc, instr_jal}; + is_lui_auipc_jal_jalr_addi_add_sub <= |{instr_lui, instr_auipc, instr_jal, instr_jalr, instr_addi, instr_add, instr_sub}; + is_slti_blt_slt <= |{instr_slti, instr_blt, instr_slt}; + is_sltiu_bltu_sltu <= |{instr_sltiu, instr_bltu, instr_sltu}; + is_lbu_lhu_lw <= |{instr_lbu, instr_lhu, instr_lw}; + is_compare <= |{is_beq_bne_blt_bge_bltu_bgeu, instr_slti, instr_slt, instr_sltiu, instr_sltu}; + + if (mem_do_rinst && mem_done) begin + instr_lui <= mem_rdata_latched[6:0] == 7'b0110111; + instr_auipc <= mem_rdata_latched[6:0] == 7'b0010111; + instr_jal <= mem_rdata_latched[6:0] == 7'b1101111; + instr_jalr <= mem_rdata_latched[6:0] == 7'b1100111 && mem_rdata_latched[14:12] == 3'b000; + instr_retirq <= mem_rdata_latched[6:0] == 7'b0001011 && mem_rdata_latched[31:25] == 7'b0000010 && ENABLE_IRQ; + instr_waitirq <= mem_rdata_latched[6:0] == 7'b0001011 && mem_rdata_latched[31:25] == 7'b0000100 && ENABLE_IRQ; + + is_beq_bne_blt_bge_bltu_bgeu <= mem_rdata_latched[6:0] == 7'b1100011; + is_lb_lh_lw_lbu_lhu <= mem_rdata_latched[6:0] == 7'b0000011; + is_sb_sh_sw <= mem_rdata_latched[6:0] == 7'b0100011; + is_alu_reg_imm <= mem_rdata_latched[6:0] == 7'b0010011; + is_alu_reg_reg <= mem_rdata_latched[6:0] == 7'b0110011; + + { decoded_imm_uj[31:20], decoded_imm_uj[10:1], decoded_imm_uj[11], decoded_imm_uj[19:12], decoded_imm_uj[0] } <= $signed({mem_rdata_latched[31:12], 1'b0}); + + decoded_rd <= mem_rdata_latched[11:7]; + decoded_rs1 <= mem_rdata_latched[19:15]; + decoded_rs2 <= mem_rdata_latched[24:20]; + + if (mem_rdata_latched[6:0] == 7'b0001011 && mem_rdata_latched[31:25] == 7'b0000000 && ENABLE_IRQ && ENABLE_IRQ_QREGS) + decoded_rs1[regindex_bits-1] <= 1; // instr_getq + + if (mem_rdata_latched[6:0] == 7'b0001011 && mem_rdata_latched[31:25] == 7'b0000010 && ENABLE_IRQ) + decoded_rs1 <= ENABLE_IRQ_QREGS ? irqregs_offset : 3; // instr_retirq + + compressed_instr <= 0; + if (COMPRESSED_ISA && mem_rdata_latched[1:0] != 2'b11) begin + compressed_instr <= 1; + decoded_rd <= 0; + decoded_rs1 <= 0; + decoded_rs2 <= 0; + + { decoded_imm_uj[31:11], decoded_imm_uj[4], decoded_imm_uj[9:8], decoded_imm_uj[10], decoded_imm_uj[6], + decoded_imm_uj[7], decoded_imm_uj[3:1], decoded_imm_uj[5], decoded_imm_uj[0] } <= $signed({mem_rdata_latched[12:2], 1'b0}); + + case (mem_rdata_latched[1:0]) + 2'b00: begin // Quadrant 0 + case (mem_rdata_latched[15:13]) + 3'b000: begin // C.ADDI4SPN + is_alu_reg_imm <= |mem_rdata_latched[12:5]; + decoded_rs1 <= 2; + decoded_rd <= 8 + mem_rdata_latched[4:2]; + end + 3'b010: begin // C.LW + is_lb_lh_lw_lbu_lhu <= 1; + decoded_rs1 <= 8 + mem_rdata_latched[9:7]; + decoded_rd <= 8 + mem_rdata_latched[4:2]; + end + 3'b110: begin // C.SW + is_sb_sh_sw <= 1; + decoded_rs1 <= 8 + mem_rdata_latched[9:7]; + decoded_rs2 <= 8 + mem_rdata_latched[4:2]; + end + endcase + end + 2'b01: begin // Quadrant 1 + case (mem_rdata_latched[15:13]) + 3'b000: begin // C.NOP / C.ADDI + is_alu_reg_imm <= 1; + decoded_rd <= mem_rdata_latched[11:7]; + decoded_rs1 <= mem_rdata_latched[11:7]; + end + 3'b001: begin // C.JAL + instr_jal <= 1; + decoded_rd <= 1; + end + 3'b 010: begin // C.LI + is_alu_reg_imm <= 1; + decoded_rd <= mem_rdata_latched[11:7]; + decoded_rs1 <= 0; + end + 3'b 011: begin + if (mem_rdata_latched[12] || mem_rdata_latched[6:2]) begin + if (mem_rdata_latched[11:7] == 2) begin // C.ADDI16SP + is_alu_reg_imm <= 1; + decoded_rd <= mem_rdata_latched[11:7]; + decoded_rs1 <= mem_rdata_latched[11:7]; + end else begin // C.LUI + instr_lui <= 1; + decoded_rd <= mem_rdata_latched[11:7]; + decoded_rs1 <= 0; + end + end + end + 3'b100: begin + if (!mem_rdata_latched[11] && !mem_rdata_latched[12]) begin // C.SRLI, C.SRAI + is_alu_reg_imm <= 1; + decoded_rd <= 8 + mem_rdata_latched[9:7]; + decoded_rs1 <= 8 + mem_rdata_latched[9:7]; + decoded_rs2 <= {mem_rdata_latched[12], mem_rdata_latched[6:2]}; + end + if (mem_rdata_latched[11:10] == 2'b10) begin // C.ANDI + is_alu_reg_imm <= 1; + decoded_rd <= 8 + mem_rdata_latched[9:7]; + decoded_rs1 <= 8 + mem_rdata_latched[9:7]; + end + if (mem_rdata_latched[12:10] == 3'b011) begin // C.SUB, C.XOR, C.OR, C.AND + is_alu_reg_reg <= 1; + decoded_rd <= 8 + mem_rdata_latched[9:7]; + decoded_rs1 <= 8 + mem_rdata_latched[9:7]; + decoded_rs2 <= 8 + mem_rdata_latched[4:2]; + end + end + 3'b101: begin // C.J + instr_jal <= 1; + end + 3'b110: begin // C.BEQZ + is_beq_bne_blt_bge_bltu_bgeu <= 1; + decoded_rs1 <= 8 + mem_rdata_latched[9:7]; + decoded_rs2 <= 0; + end + 3'b111: begin // C.BNEZ + is_beq_bne_blt_bge_bltu_bgeu <= 1; + decoded_rs1 <= 8 + mem_rdata_latched[9:7]; + decoded_rs2 <= 0; + end + endcase + end + 2'b10: begin // Quadrant 2 + case (mem_rdata_latched[15:13]) + 3'b000: begin // C.SLLI + if (!mem_rdata_latched[12]) begin + is_alu_reg_imm <= 1; + decoded_rd <= mem_rdata_latched[11:7]; + decoded_rs1 <= mem_rdata_latched[11:7]; + decoded_rs2 <= {mem_rdata_latched[12], mem_rdata_latched[6:2]}; + end + end + 3'b010: begin // C.LWSP + if (mem_rdata_latched[11:7]) begin + is_lb_lh_lw_lbu_lhu <= 1; + decoded_rd <= mem_rdata_latched[11:7]; + decoded_rs1 <= 2; + end + end + 3'b100: begin + if (mem_rdata_latched[12] == 0 && mem_rdata_latched[11:7] != 0 && mem_rdata_latched[6:2] == 0) begin // C.JR + instr_jalr <= 1; + decoded_rd <= 0; + decoded_rs1 <= mem_rdata_latched[11:7]; + end + if (mem_rdata_latched[12] == 0 && mem_rdata_latched[6:2] != 0) begin // C.MV + is_alu_reg_reg <= 1; + decoded_rd <= mem_rdata_latched[11:7]; + decoded_rs1 <= 0; + decoded_rs2 <= mem_rdata_latched[6:2]; + end + if (mem_rdata_latched[12] != 0 && mem_rdata_latched[11:7] != 0 && mem_rdata_latched[6:2] == 0) begin // C.JALR + instr_jalr <= 1; + decoded_rd <= 1; + decoded_rs1 <= mem_rdata_latched[11:7]; + end + if (mem_rdata_latched[12] != 0 && mem_rdata_latched[6:2] != 0) begin // C.ADD + is_alu_reg_reg <= 1; + decoded_rd <= mem_rdata_latched[11:7]; + decoded_rs1 <= mem_rdata_latched[11:7]; + decoded_rs2 <= mem_rdata_latched[6:2]; + end + end + 3'b110: begin // C.SWSP + is_sb_sh_sw <= 1; + decoded_rs1 <= 2; + decoded_rs2 <= mem_rdata_latched[6:2]; + end + endcase + end + endcase + end + end + + if (decoder_trigger && !decoder_pseudo_trigger) begin + pcpi_insn <= WITH_PCPI ? mem_rdata_q : 'bx; + + instr_beq <= is_beq_bne_blt_bge_bltu_bgeu && mem_rdata_q[14:12] == 3'b000; + instr_bne <= is_beq_bne_blt_bge_bltu_bgeu && mem_rdata_q[14:12] == 3'b001; + instr_blt <= is_beq_bne_blt_bge_bltu_bgeu && mem_rdata_q[14:12] == 3'b100; + instr_bge <= is_beq_bne_blt_bge_bltu_bgeu && mem_rdata_q[14:12] == 3'b101; + instr_bltu <= is_beq_bne_blt_bge_bltu_bgeu && mem_rdata_q[14:12] == 3'b110; + instr_bgeu <= is_beq_bne_blt_bge_bltu_bgeu && mem_rdata_q[14:12] == 3'b111; + + instr_lb <= is_lb_lh_lw_lbu_lhu && mem_rdata_q[14:12] == 3'b000; + instr_lh <= is_lb_lh_lw_lbu_lhu && mem_rdata_q[14:12] == 3'b001; + instr_lw <= is_lb_lh_lw_lbu_lhu && mem_rdata_q[14:12] == 3'b010; + instr_lbu <= is_lb_lh_lw_lbu_lhu && mem_rdata_q[14:12] == 3'b100; + instr_lhu <= is_lb_lh_lw_lbu_lhu && mem_rdata_q[14:12] == 3'b101; + + instr_sb <= is_sb_sh_sw && mem_rdata_q[14:12] == 3'b000; + instr_sh <= is_sb_sh_sw && mem_rdata_q[14:12] == 3'b001; + instr_sw <= is_sb_sh_sw && mem_rdata_q[14:12] == 3'b010; + + instr_addi <= is_alu_reg_imm && mem_rdata_q[14:12] == 3'b000; + instr_slti <= is_alu_reg_imm && mem_rdata_q[14:12] == 3'b010; + instr_sltiu <= is_alu_reg_imm && mem_rdata_q[14:12] == 3'b011; + instr_xori <= is_alu_reg_imm && mem_rdata_q[14:12] == 3'b100; + instr_ori <= is_alu_reg_imm && mem_rdata_q[14:12] == 3'b110; + instr_andi <= is_alu_reg_imm && mem_rdata_q[14:12] == 3'b111; + + instr_slli <= is_alu_reg_imm && mem_rdata_q[14:12] == 3'b001 && mem_rdata_q[31:25] == 7'b0000000; + instr_srli <= is_alu_reg_imm && mem_rdata_q[14:12] == 3'b101 && mem_rdata_q[31:25] == 7'b0000000; + instr_srai <= is_alu_reg_imm && mem_rdata_q[14:12] == 3'b101 && mem_rdata_q[31:25] == 7'b0100000; + + instr_add <= is_alu_reg_reg && mem_rdata_q[14:12] == 3'b000 && mem_rdata_q[31:25] == 7'b0000000; + instr_sub <= is_alu_reg_reg && mem_rdata_q[14:12] == 3'b000 && mem_rdata_q[31:25] == 7'b0100000; + instr_sll <= is_alu_reg_reg && mem_rdata_q[14:12] == 3'b001 && mem_rdata_q[31:25] == 7'b0000000; + instr_slt <= is_alu_reg_reg && mem_rdata_q[14:12] == 3'b010 && mem_rdata_q[31:25] == 7'b0000000; + instr_sltu <= is_alu_reg_reg && mem_rdata_q[14:12] == 3'b011 && mem_rdata_q[31:25] == 7'b0000000; + instr_xor <= is_alu_reg_reg && mem_rdata_q[14:12] == 3'b100 && mem_rdata_q[31:25] == 7'b0000000; + instr_srl <= is_alu_reg_reg && mem_rdata_q[14:12] == 3'b101 && mem_rdata_q[31:25] == 7'b0000000; + instr_sra <= is_alu_reg_reg && mem_rdata_q[14:12] == 3'b101 && mem_rdata_q[31:25] == 7'b0100000; + instr_or <= is_alu_reg_reg && mem_rdata_q[14:12] == 3'b110 && mem_rdata_q[31:25] == 7'b0000000; + instr_and <= is_alu_reg_reg && mem_rdata_q[14:12] == 3'b111 && mem_rdata_q[31:25] == 7'b0000000; + + instr_rdcycle <= ((mem_rdata_q[6:0] == 7'b1110011 && mem_rdata_q[31:12] == 'b11000000000000000010) || + (mem_rdata_q[6:0] == 7'b1110011 && mem_rdata_q[31:12] == 'b11000000000100000010)) && ENABLE_COUNTERS; + instr_rdcycleh <= ((mem_rdata_q[6:0] == 7'b1110011 && mem_rdata_q[31:12] == 'b11001000000000000010) || + (mem_rdata_q[6:0] == 7'b1110011 && mem_rdata_q[31:12] == 'b11001000000100000010)) && ENABLE_COUNTERS && ENABLE_COUNTERS64; + instr_rdinstr <= (mem_rdata_q[6:0] == 7'b1110011 && mem_rdata_q[31:12] == 'b11000000001000000010) && ENABLE_COUNTERS; + instr_rdinstrh <= (mem_rdata_q[6:0] == 7'b1110011 && mem_rdata_q[31:12] == 'b11001000001000000010) && ENABLE_COUNTERS && ENABLE_COUNTERS64; + + instr_ecall_ebreak <= ((mem_rdata_q[6:0] == 7'b1110011 && !mem_rdata_q[31:21] && !mem_rdata_q[19:7]) || + (COMPRESSED_ISA && mem_rdata_q[15:0] == 16'h9002)); + + instr_getq <= mem_rdata_q[6:0] == 7'b0001011 && mem_rdata_q[31:25] == 7'b0000000 && ENABLE_IRQ && ENABLE_IRQ_QREGS; + instr_setq <= mem_rdata_q[6:0] == 7'b0001011 && mem_rdata_q[31:25] == 7'b0000001 && ENABLE_IRQ && ENABLE_IRQ_QREGS; + instr_maskirq <= mem_rdata_q[6:0] == 7'b0001011 && mem_rdata_q[31:25] == 7'b0000011 && ENABLE_IRQ; + instr_timer <= mem_rdata_q[6:0] == 7'b0001011 && mem_rdata_q[31:25] == 7'b0000101 && ENABLE_IRQ && ENABLE_IRQ_TIMER; + + is_slli_srli_srai <= is_alu_reg_imm && |{ + mem_rdata_q[14:12] == 3'b001 && mem_rdata_q[31:25] == 7'b0000000, + mem_rdata_q[14:12] == 3'b101 && mem_rdata_q[31:25] == 7'b0000000, + mem_rdata_q[14:12] == 3'b101 && mem_rdata_q[31:25] == 7'b0100000 + }; + + is_jalr_addi_slti_sltiu_xori_ori_andi <= instr_jalr || is_alu_reg_imm && |{ + mem_rdata_q[14:12] == 3'b000, + mem_rdata_q[14:12] == 3'b010, + mem_rdata_q[14:12] == 3'b011, + mem_rdata_q[14:12] == 3'b100, + mem_rdata_q[14:12] == 3'b110, + mem_rdata_q[14:12] == 3'b111 + }; + + is_sll_srl_sra <= is_alu_reg_reg && |{ + mem_rdata_q[14:12] == 3'b001 && mem_rdata_q[31:25] == 7'b0000000, + mem_rdata_q[14:12] == 3'b101 && mem_rdata_q[31:25] == 7'b0000000, + mem_rdata_q[14:12] == 3'b101 && mem_rdata_q[31:25] == 7'b0100000 + }; + + is_lui_auipc_jal_jalr_addi_add_sub <= 0; + is_compare <= 0; + + (* parallel_case *) + case (1'b1) + instr_jal: + decoded_imm <= decoded_imm_uj; + |{instr_lui, instr_auipc}: + decoded_imm <= mem_rdata_q[31:12] << 12; + |{instr_jalr, is_lb_lh_lw_lbu_lhu, is_alu_reg_imm}: + decoded_imm <= $signed(mem_rdata_q[31:20]); + is_beq_bne_blt_bge_bltu_bgeu: + decoded_imm <= $signed({mem_rdata_q[31], mem_rdata_q[7], mem_rdata_q[30:25], mem_rdata_q[11:8], 1'b0}); + is_sb_sh_sw: + decoded_imm <= $signed({mem_rdata_q[31:25], mem_rdata_q[11:7]}); + default: + decoded_imm <= 1'bx; + endcase + end + + if (!resetn) begin + is_beq_bne_blt_bge_bltu_bgeu <= 0; + is_compare <= 0; + + instr_beq <= 0; + instr_bne <= 0; + instr_blt <= 0; + instr_bge <= 0; + instr_bltu <= 0; + instr_bgeu <= 0; + + instr_addi <= 0; + instr_slti <= 0; + instr_sltiu <= 0; + instr_xori <= 0; + instr_ori <= 0; + instr_andi <= 0; + + instr_add <= 0; + instr_sub <= 0; + instr_sll <= 0; + instr_slt <= 0; + instr_sltu <= 0; + instr_xor <= 0; + instr_srl <= 0; + instr_sra <= 0; + instr_or <= 0; + instr_and <= 0; + end + end + + + // Main State Machine + + localparam cpu_state_trap = 8'b10000000; + localparam cpu_state_fetch = 8'b01000000; + localparam cpu_state_ld_rs1 = 8'b00100000; + localparam cpu_state_ld_rs2 = 8'b00010000; + localparam cpu_state_exec = 8'b00001000; + localparam cpu_state_shift = 8'b00000100; + localparam cpu_state_stmem = 8'b00000010; + localparam cpu_state_ldmem = 8'b00000001; + + reg [7:0] cpu_state; + reg [1:0] irq_state; + + `FORMAL_KEEP reg [127:0] dbg_ascii_state; + + always @* begin + dbg_ascii_state = ""; + if (cpu_state == cpu_state_trap) dbg_ascii_state = "trap"; + if (cpu_state == cpu_state_fetch) dbg_ascii_state = "fetch"; + if (cpu_state == cpu_state_ld_rs1) dbg_ascii_state = "ld_rs1"; + if (cpu_state == cpu_state_ld_rs2) dbg_ascii_state = "ld_rs2"; + if (cpu_state == cpu_state_exec) dbg_ascii_state = "exec"; + if (cpu_state == cpu_state_shift) dbg_ascii_state = "shift"; + if (cpu_state == cpu_state_stmem) dbg_ascii_state = "stmem"; + if (cpu_state == cpu_state_ldmem) dbg_ascii_state = "ldmem"; + end + + reg set_mem_do_rinst; + reg set_mem_do_rdata; + reg set_mem_do_wdata; + + reg latched_store; + reg latched_stalu; + reg latched_branch; + reg latched_compr; + reg latched_trace; + reg latched_is_lu; + reg latched_is_lh; + reg latched_is_lb; + reg [regindex_bits-1:0] latched_rd; + + reg [31:0] current_pc; + assign next_pc = latched_store && latched_branch ? reg_out & ~1 : reg_next_pc; + + reg [3:0] pcpi_timeout_counter; + reg pcpi_timeout; + + reg [31:0] next_irq_pending; + reg do_waitirq; + + reg [31:0] alu_out, alu_out_q; + reg alu_out_0, alu_out_0_q; + reg alu_wait, alu_wait_2; + + reg [31:0] alu_add_sub; + reg [31:0] alu_shl, alu_shr; + reg alu_eq, alu_ltu, alu_lts; + + generate if (TWO_CYCLE_ALU) begin + always @(posedge clk) begin + alu_add_sub <= instr_sub ? reg_op1 - reg_op2 : reg_op1 + reg_op2; + alu_eq <= reg_op1 == reg_op2; + alu_lts <= $signed(reg_op1) < $signed(reg_op2); + alu_ltu <= reg_op1 < reg_op2; + alu_shl <= reg_op1 << reg_op2[4:0]; + alu_shr <= $signed({instr_sra || instr_srai ? reg_op1[31] : 1'b0, reg_op1}) >>> reg_op2[4:0]; + end + end else begin + always @* begin + alu_add_sub = instr_sub ? reg_op1 - reg_op2 : reg_op1 + reg_op2; + alu_eq = reg_op1 == reg_op2; + alu_lts = $signed(reg_op1) < $signed(reg_op2); + alu_ltu = reg_op1 < reg_op2; + alu_shl = reg_op1 << reg_op2[4:0]; + alu_shr = $signed({instr_sra || instr_srai ? reg_op1[31] : 1'b0, reg_op1}) >>> reg_op2[4:0]; + end + end endgenerate + + always @* begin + alu_out_0 = 'bx; + (* parallel_case, full_case *) + case (1'b1) + instr_beq: + alu_out_0 = alu_eq; + instr_bne: + alu_out_0 = !alu_eq; + instr_bge: + alu_out_0 = !alu_lts; + instr_bgeu: + alu_out_0 = !alu_ltu; + is_slti_blt_slt && (!TWO_CYCLE_COMPARE || !{instr_beq,instr_bne,instr_bge,instr_bgeu}): + alu_out_0 = alu_lts; + is_sltiu_bltu_sltu && (!TWO_CYCLE_COMPARE || !{instr_beq,instr_bne,instr_bge,instr_bgeu}): + alu_out_0 = alu_ltu; + endcase + + alu_out = 'bx; + (* parallel_case, full_case *) + case (1'b1) + is_lui_auipc_jal_jalr_addi_add_sub: + alu_out = alu_add_sub; + is_compare: + alu_out = alu_out_0; + instr_xori || instr_xor: + alu_out = reg_op1 ^ reg_op2; + instr_ori || instr_or: + alu_out = reg_op1 | reg_op2; + instr_andi || instr_and: + alu_out = reg_op1 & reg_op2; + BARREL_SHIFTER && (instr_sll || instr_slli): + alu_out = alu_shl; + BARREL_SHIFTER && (instr_srl || instr_srli || instr_sra || instr_srai): + alu_out = alu_shr; + endcase + +`ifdef RISCV_FORMAL_BLACKBOX_ALU + alu_out_0 = $anyseq; + alu_out = $anyseq; +`endif + end + + reg clear_prefetched_high_word_q; + always @(posedge clk) clear_prefetched_high_word_q <= clear_prefetched_high_word; + + always @* begin + clear_prefetched_high_word = clear_prefetched_high_word_q; + if (!prefetched_high_word) + clear_prefetched_high_word = 0; + if (latched_branch || irq_state || !resetn) + clear_prefetched_high_word = COMPRESSED_ISA; + end + + reg cpuregs_write; + reg [31:0] cpuregs_wrdata; + reg [31:0] cpuregs_rs1; + reg [31:0] cpuregs_rs2; + reg [regindex_bits-1:0] decoded_rs; + + always @* begin + cpuregs_write = 0; + cpuregs_wrdata = 'bx; + + if (cpu_state == cpu_state_fetch) begin + (* parallel_case *) + case (1'b1) + latched_branch: begin + cpuregs_wrdata = reg_pc + (latched_compr ? 2 : 4); + cpuregs_write = 1; + end + latched_store && !latched_branch: begin + cpuregs_wrdata = latched_stalu ? alu_out_q : reg_out; + cpuregs_write = 1; + end + ENABLE_IRQ && irq_state[0]: begin + cpuregs_wrdata = reg_next_pc | latched_compr; + cpuregs_write = 1; + end + ENABLE_IRQ && irq_state[1]: begin + cpuregs_wrdata = irq_pending & ~irq_mask; + cpuregs_write = 1; + end + endcase + end + end + +`ifndef PICORV32_REGS + always @(posedge clk) begin + if (resetn && cpuregs_write && latched_rd) + cpuregs[latched_rd] <= cpuregs_wrdata; + end + + always @* begin + decoded_rs = 'bx; + if (ENABLE_REGS_DUALPORT) begin +`ifndef RISCV_FORMAL_BLACKBOX_REGS + cpuregs_rs1 = decoded_rs1 ? cpuregs[decoded_rs1] : 0; + cpuregs_rs2 = decoded_rs2 ? cpuregs[decoded_rs2] : 0; +`else + cpuregs_rs1 = decoded_rs1 ? $anyseq : 0; + cpuregs_rs2 = decoded_rs2 ? $anyseq : 0; +`endif + end else begin + decoded_rs = (cpu_state == cpu_state_ld_rs2) ? decoded_rs2 : decoded_rs1; +`ifndef RISCV_FORMAL_BLACKBOX_REGS + cpuregs_rs1 = decoded_rs ? cpuregs[decoded_rs] : 0; +`else + cpuregs_rs1 = decoded_rs ? $anyseq : 0; +`endif + cpuregs_rs2 = cpuregs_rs1; + end + end +`else + wire[31:0] cpuregs_rdata1; + wire[31:0] cpuregs_rdata2; + + wire [5:0] cpuregs_waddr = latched_rd; + wire [5:0] cpuregs_raddr1 = ENABLE_REGS_DUALPORT ? decoded_rs1 : decoded_rs; + wire [5:0] cpuregs_raddr2 = ENABLE_REGS_DUALPORT ? decoded_rs2 : 0; + + `PICORV32_REGS cpuregs ( + .clk(clk), + .wen(resetn && cpuregs_write && latched_rd), + .waddr(cpuregs_waddr), + .raddr1(cpuregs_raddr1), + .raddr2(cpuregs_raddr2), + .wdata(cpuregs_wrdata), + .rdata1(cpuregs_rdata1), + .rdata2(cpuregs_rdata2) + ); + + always @* begin + decoded_rs = 'bx; + if (ENABLE_REGS_DUALPORT) begin + cpuregs_rs1 = decoded_rs1 ? cpuregs_rdata1 : 0; + cpuregs_rs2 = decoded_rs2 ? cpuregs_rdata2 : 0; + end else begin + decoded_rs = (cpu_state == cpu_state_ld_rs2) ? decoded_rs2 : decoded_rs1; + cpuregs_rs1 = decoded_rs ? cpuregs_rdata1 : 0; + cpuregs_rs2 = cpuregs_rs1; + end + end +`endif + + assign launch_next_insn = cpu_state == cpu_state_fetch && decoder_trigger && (!ENABLE_IRQ || irq_delay || irq_active || !(irq_pending & ~irq_mask)); + + always @(posedge clk) begin + trap <= 0; + reg_sh <= 'bx; + reg_out <= 'bx; + set_mem_do_rinst = 0; + set_mem_do_rdata = 0; + set_mem_do_wdata = 0; + + alu_out_0_q <= alu_out_0; + alu_out_q <= alu_out; + + alu_wait <= 0; + alu_wait_2 <= 0; + + if (launch_next_insn) begin + dbg_rs1val <= 'bx; + dbg_rs2val <= 'bx; + dbg_rs1val_valid <= 0; + dbg_rs2val_valid <= 0; + end + + if (WITH_PCPI && CATCH_ILLINSN) begin + if (resetn && pcpi_valid && !pcpi_int_wait) begin + if (pcpi_timeout_counter) + pcpi_timeout_counter <= pcpi_timeout_counter - 1; + end else + pcpi_timeout_counter <= ~0; + pcpi_timeout <= !pcpi_timeout_counter; + end + + if (ENABLE_COUNTERS) begin + count_cycle <= resetn ? count_cycle + 1 : 0; + if (!ENABLE_COUNTERS64) count_cycle[63:32] <= 0; + end else begin + count_cycle <= 'bx; + count_instr <= 'bx; + end + + next_irq_pending = ENABLE_IRQ ? irq_pending & LATCHED_IRQ : 'bx; + + if (ENABLE_IRQ && ENABLE_IRQ_TIMER && timer) begin + if (timer - 1 == 0) + next_irq_pending[irq_timer] = 1; + timer <= timer - 1; + end + + if (ENABLE_IRQ) begin + next_irq_pending = next_irq_pending | irq; + end + + decoder_trigger <= mem_do_rinst && mem_done; + decoder_trigger_q <= decoder_trigger; + decoder_pseudo_trigger <= 0; + decoder_pseudo_trigger_q <= decoder_pseudo_trigger; + do_waitirq <= 0; + + trace_valid <= 0; + + if (!ENABLE_TRACE) + trace_data <= 'bx; + + if (!resetn) begin + reg_pc <= PROGADDR_RESET; + reg_next_pc <= PROGADDR_RESET; + if (ENABLE_COUNTERS) + count_instr <= 0; + latched_store <= 0; + latched_stalu <= 0; + latched_branch <= 0; + latched_trace <= 0; + latched_is_lu <= 0; + latched_is_lh <= 0; + latched_is_lb <= 0; + pcpi_valid <= 0; + pcpi_timeout <= 0; + irq_active <= 0; + irq_delay <= 0; + irq_mask <= ~0; + next_irq_pending = 0; + irq_state <= 0; + eoi <= 0; + timer <= 0; + if (~STACKADDR) begin + latched_store <= 1; + latched_rd <= 2; + reg_out <= STACKADDR; + end + cpu_state <= cpu_state_fetch; + end else + (* parallel_case, full_case *) + case (cpu_state) + cpu_state_trap: begin + trap <= 1; + end + + cpu_state_fetch: begin + mem_do_rinst <= !decoder_trigger && !do_waitirq; + mem_wordsize <= 0; + + current_pc = reg_next_pc; + + (* parallel_case *) + case (1'b1) + latched_branch: begin + current_pc = latched_store ? (latched_stalu ? alu_out_q : reg_out) & ~1 : reg_next_pc; + `debug($display("ST_RD: %2d 0x%08x, BRANCH 0x%08x", latched_rd, reg_pc + (latched_compr ? 2 : 4), current_pc);) + end + latched_store && !latched_branch: begin + `debug($display("ST_RD: %2d 0x%08x", latched_rd, latched_stalu ? alu_out_q : reg_out);) + end + ENABLE_IRQ && irq_state[0]: begin + current_pc = PROGADDR_IRQ; + irq_active <= 1; + mem_do_rinst <= 1; + end + ENABLE_IRQ && irq_state[1]: begin + eoi <= irq_pending & ~irq_mask; + next_irq_pending = next_irq_pending & irq_mask; + end + endcase + + if (ENABLE_TRACE && latched_trace) begin + latched_trace <= 0; + trace_valid <= 1; + if (latched_branch) + trace_data <= (irq_active ? TRACE_IRQ : 0) | TRACE_BRANCH | (current_pc & 32'hfffffffe); + else + trace_data <= (irq_active ? TRACE_IRQ : 0) | (latched_stalu ? alu_out_q : reg_out); + end + + reg_pc <= current_pc; + reg_next_pc <= current_pc; + + latched_store <= 0; + latched_stalu <= 0; + latched_branch <= 0; + latched_is_lu <= 0; + latched_is_lh <= 0; + latched_is_lb <= 0; + latched_rd <= decoded_rd; + latched_compr <= compressed_instr; + + if (ENABLE_IRQ && ((decoder_trigger && !irq_active && !irq_delay && |(irq_pending & ~irq_mask)) || irq_state)) begin + irq_state <= + irq_state == 2'b00 ? 2'b01 : + irq_state == 2'b01 ? 2'b10 : 2'b00; + latched_compr <= latched_compr; + if (ENABLE_IRQ_QREGS) + latched_rd <= irqregs_offset | irq_state[0]; + else + latched_rd <= irq_state[0] ? 4 : 3; + end else + if (ENABLE_IRQ && (decoder_trigger || do_waitirq) && instr_waitirq) begin + if (irq_pending) begin + latched_store <= 1; + reg_out <= irq_pending; + reg_next_pc <= current_pc + (compressed_instr ? 2 : 4); + mem_do_rinst <= 1; + end else + do_waitirq <= 1; + end else + if (decoder_trigger) begin + `debug($display("-- %-0t", $time);) + irq_delay <= irq_active; + reg_next_pc <= current_pc + (compressed_instr ? 2 : 4); + if (ENABLE_TRACE) + latched_trace <= 1; + if (ENABLE_COUNTERS) begin + count_instr <= count_instr + 1; + if (!ENABLE_COUNTERS64) count_instr[63:32] <= 0; + end + if (instr_jal) begin + mem_do_rinst <= 1; + reg_next_pc <= current_pc + decoded_imm_uj; + latched_branch <= 1; + end else begin + mem_do_rinst <= 0; + mem_do_prefetch <= !instr_jalr && !instr_retirq; + cpu_state <= cpu_state_ld_rs1; + end + end + end + + cpu_state_ld_rs1: begin + reg_op1 <= 'bx; + reg_op2 <= 'bx; + + (* parallel_case *) + case (1'b1) + (CATCH_ILLINSN || WITH_PCPI) && instr_trap: begin + if (WITH_PCPI) begin + `debug($display("LD_RS1: %2d 0x%08x", decoded_rs1, cpuregs_rs1);) + reg_op1 <= cpuregs_rs1; + dbg_rs1val <= cpuregs_rs1; + dbg_rs1val_valid <= 1; + if (ENABLE_REGS_DUALPORT) begin + pcpi_valid <= 1; + `debug($display("LD_RS2: %2d 0x%08x", decoded_rs2, cpuregs_rs2);) + reg_sh <= cpuregs_rs2; + reg_op2 <= cpuregs_rs2; + dbg_rs2val <= cpuregs_rs2; + dbg_rs2val_valid <= 1; + if (pcpi_int_ready) begin + mem_do_rinst <= 1; + pcpi_valid <= 0; + reg_out <= pcpi_int_rd; + latched_store <= pcpi_int_wr; + cpu_state <= cpu_state_fetch; + end else + if (CATCH_ILLINSN && (pcpi_timeout || instr_ecall_ebreak)) begin + pcpi_valid <= 0; + `debug($display("EBREAK OR UNSUPPORTED INSN AT 0x%08x", reg_pc);) + if (ENABLE_IRQ && !irq_mask[irq_ebreak] && !irq_active) begin + next_irq_pending[irq_ebreak] = 1; + cpu_state <= cpu_state_fetch; + end else + cpu_state <= cpu_state_trap; + end + end else begin + cpu_state <= cpu_state_ld_rs2; + end + end else begin + `debug($display("EBREAK OR UNSUPPORTED INSN AT 0x%08x", reg_pc);) + if (ENABLE_IRQ && !irq_mask[irq_ebreak] && !irq_active) begin + next_irq_pending[irq_ebreak] = 1; + cpu_state <= cpu_state_fetch; + end else + cpu_state <= cpu_state_trap; + end + end + ENABLE_COUNTERS && is_rdcycle_rdcycleh_rdinstr_rdinstrh: begin + (* parallel_case, full_case *) + case (1'b1) + instr_rdcycle: + reg_out <= count_cycle[31:0]; + instr_rdcycleh && ENABLE_COUNTERS64: + reg_out <= count_cycle[63:32]; + instr_rdinstr: + reg_out <= count_instr[31:0]; + instr_rdinstrh && ENABLE_COUNTERS64: + reg_out <= count_instr[63:32]; + endcase + latched_store <= 1; + cpu_state <= cpu_state_fetch; + end + is_lui_auipc_jal: begin + reg_op1 <= instr_lui ? 0 : reg_pc; + reg_op2 <= decoded_imm; + if (TWO_CYCLE_ALU) + alu_wait <= 1; + else + mem_do_rinst <= mem_do_prefetch; + cpu_state <= cpu_state_exec; + end + ENABLE_IRQ && ENABLE_IRQ_QREGS && instr_getq: begin + `debug($display("LD_RS1: %2d 0x%08x", decoded_rs1, cpuregs_rs1);) + reg_out <= cpuregs_rs1; + dbg_rs1val <= cpuregs_rs1; + dbg_rs1val_valid <= 1; + latched_store <= 1; + cpu_state <= cpu_state_fetch; + end + ENABLE_IRQ && ENABLE_IRQ_QREGS && instr_setq: begin + `debug($display("LD_RS1: %2d 0x%08x", decoded_rs1, cpuregs_rs1);) + reg_out <= cpuregs_rs1; + dbg_rs1val <= cpuregs_rs1; + dbg_rs1val_valid <= 1; + latched_rd <= latched_rd | irqregs_offset; + latched_store <= 1; + cpu_state <= cpu_state_fetch; + end + ENABLE_IRQ && instr_retirq: begin + eoi <= 0; + irq_active <= 0; + latched_branch <= 1; + latched_store <= 1; + `debug($display("LD_RS1: %2d 0x%08x", decoded_rs1, cpuregs_rs1);) + reg_out <= CATCH_MISALIGN ? (cpuregs_rs1 & 32'h fffffffe) : cpuregs_rs1; + dbg_rs1val <= cpuregs_rs1; + dbg_rs1val_valid <= 1; + cpu_state <= cpu_state_fetch; + end + ENABLE_IRQ && instr_maskirq: begin + latched_store <= 1; + reg_out <= irq_mask; + `debug($display("LD_RS1: %2d 0x%08x", decoded_rs1, cpuregs_rs1);) + irq_mask <= cpuregs_rs1 | MASKED_IRQ; + dbg_rs1val <= cpuregs_rs1; + dbg_rs1val_valid <= 1; + cpu_state <= cpu_state_fetch; + end + ENABLE_IRQ && ENABLE_IRQ_TIMER && instr_timer: begin + latched_store <= 1; + reg_out <= timer; + `debug($display("LD_RS1: %2d 0x%08x", decoded_rs1, cpuregs_rs1);) + timer <= cpuregs_rs1; + dbg_rs1val <= cpuregs_rs1; + dbg_rs1val_valid <= 1; + cpu_state <= cpu_state_fetch; + end + is_lb_lh_lw_lbu_lhu && !instr_trap: begin + `debug($display("LD_RS1: %2d 0x%08x", decoded_rs1, cpuregs_rs1);) + reg_op1 <= cpuregs_rs1; + dbg_rs1val <= cpuregs_rs1; + dbg_rs1val_valid <= 1; + cpu_state <= cpu_state_ldmem; + mem_do_rinst <= 1; + end + is_slli_srli_srai && !BARREL_SHIFTER: begin + `debug($display("LD_RS1: %2d 0x%08x", decoded_rs1, cpuregs_rs1);) + reg_op1 <= cpuregs_rs1; + dbg_rs1val <= cpuregs_rs1; + dbg_rs1val_valid <= 1; + reg_sh <= decoded_rs2; + cpu_state <= cpu_state_shift; + end + is_jalr_addi_slti_sltiu_xori_ori_andi, is_slli_srli_srai && BARREL_SHIFTER: begin + `debug($display("LD_RS1: %2d 0x%08x", decoded_rs1, cpuregs_rs1);) + reg_op1 <= cpuregs_rs1; + dbg_rs1val <= cpuregs_rs1; + dbg_rs1val_valid <= 1; + reg_op2 <= is_slli_srli_srai && BARREL_SHIFTER ? decoded_rs2 : decoded_imm; + if (TWO_CYCLE_ALU) + alu_wait <= 1; + else + mem_do_rinst <= mem_do_prefetch; + cpu_state <= cpu_state_exec; + end + default: begin + `debug($display("LD_RS1: %2d 0x%08x", decoded_rs1, cpuregs_rs1);) + reg_op1 <= cpuregs_rs1; + dbg_rs1val <= cpuregs_rs1; + dbg_rs1val_valid <= 1; + if (ENABLE_REGS_DUALPORT) begin + `debug($display("LD_RS2: %2d 0x%08x", decoded_rs2, cpuregs_rs2);) + reg_sh <= cpuregs_rs2; + reg_op2 <= cpuregs_rs2; + dbg_rs2val <= cpuregs_rs2; + dbg_rs2val_valid <= 1; + (* parallel_case *) + case (1'b1) + is_sb_sh_sw: begin + cpu_state <= cpu_state_stmem; + mem_do_rinst <= 1; + end + is_sll_srl_sra && !BARREL_SHIFTER: begin + cpu_state <= cpu_state_shift; + end + default: begin + if (TWO_CYCLE_ALU || (TWO_CYCLE_COMPARE && is_beq_bne_blt_bge_bltu_bgeu)) begin + alu_wait_2 <= TWO_CYCLE_ALU && (TWO_CYCLE_COMPARE && is_beq_bne_blt_bge_bltu_bgeu); + alu_wait <= 1; + end else + mem_do_rinst <= mem_do_prefetch; + cpu_state <= cpu_state_exec; + end + endcase + end else + cpu_state <= cpu_state_ld_rs2; + end + endcase + end + + cpu_state_ld_rs2: begin + `debug($display("LD_RS2: %2d 0x%08x", decoded_rs2, cpuregs_rs2);) + reg_sh <= cpuregs_rs2; + reg_op2 <= cpuregs_rs2; + dbg_rs2val <= cpuregs_rs2; + dbg_rs2val_valid <= 1; + + (* parallel_case *) + case (1'b1) + WITH_PCPI && instr_trap: begin + pcpi_valid <= 1; + if (pcpi_int_ready) begin + mem_do_rinst <= 1; + pcpi_valid <= 0; + reg_out <= pcpi_int_rd; + latched_store <= pcpi_int_wr; + cpu_state <= cpu_state_fetch; + end else + if (CATCH_ILLINSN && (pcpi_timeout || instr_ecall_ebreak)) begin + pcpi_valid <= 0; + `debug($display("EBREAK OR UNSUPPORTED INSN AT 0x%08x", reg_pc);) + if (ENABLE_IRQ && !irq_mask[irq_ebreak] && !irq_active) begin + next_irq_pending[irq_ebreak] = 1; + cpu_state <= cpu_state_fetch; + end else + cpu_state <= cpu_state_trap; + end + end + is_sb_sh_sw: begin + cpu_state <= cpu_state_stmem; + mem_do_rinst <= 1; + end + is_sll_srl_sra && !BARREL_SHIFTER: begin + cpu_state <= cpu_state_shift; + end + default: begin + if (TWO_CYCLE_ALU || (TWO_CYCLE_COMPARE && is_beq_bne_blt_bge_bltu_bgeu)) begin + alu_wait_2 <= TWO_CYCLE_ALU && (TWO_CYCLE_COMPARE && is_beq_bne_blt_bge_bltu_bgeu); + alu_wait <= 1; + end else + mem_do_rinst <= mem_do_prefetch; + cpu_state <= cpu_state_exec; + end + endcase + end + + cpu_state_exec: begin + reg_out <= reg_pc + decoded_imm; + if ((TWO_CYCLE_ALU || TWO_CYCLE_COMPARE) && (alu_wait || alu_wait_2)) begin + mem_do_rinst <= mem_do_prefetch && !alu_wait_2; + alu_wait <= alu_wait_2; + end else + if (is_beq_bne_blt_bge_bltu_bgeu) begin + latched_rd <= 0; + latched_store <= TWO_CYCLE_COMPARE ? alu_out_0_q : alu_out_0; + latched_branch <= TWO_CYCLE_COMPARE ? alu_out_0_q : alu_out_0; + if (mem_done) + cpu_state <= cpu_state_fetch; + if (TWO_CYCLE_COMPARE ? alu_out_0_q : alu_out_0) begin + decoder_trigger <= 0; + set_mem_do_rinst = 1; + end + end else begin + latched_branch <= instr_jalr; + latched_store <= 1; + latched_stalu <= 1; + cpu_state <= cpu_state_fetch; + end + end + + cpu_state_shift: begin + latched_store <= 1; + if (reg_sh == 0) begin + reg_out <= reg_op1; + mem_do_rinst <= mem_do_prefetch; + cpu_state <= cpu_state_fetch; + end else if (TWO_STAGE_SHIFT && reg_sh >= 4) begin + (* parallel_case, full_case *) + case (1'b1) + instr_slli || instr_sll: reg_op1 <= reg_op1 << 4; + instr_srli || instr_srl: reg_op1 <= reg_op1 >> 4; + instr_srai || instr_sra: reg_op1 <= $signed(reg_op1) >>> 4; + endcase + reg_sh <= reg_sh - 4; + end else begin + (* parallel_case, full_case *) + case (1'b1) + instr_slli || instr_sll: reg_op1 <= reg_op1 << 1; + instr_srli || instr_srl: reg_op1 <= reg_op1 >> 1; + instr_srai || instr_sra: reg_op1 <= $signed(reg_op1) >>> 1; + endcase + reg_sh <= reg_sh - 1; + end + end + + cpu_state_stmem: begin + if (ENABLE_TRACE) + reg_out <= reg_op2; + if (!mem_do_prefetch || mem_done) begin + if (!mem_do_wdata) begin + (* parallel_case, full_case *) + case (1'b1) + instr_sb: mem_wordsize <= 2; + instr_sh: mem_wordsize <= 1; + instr_sw: mem_wordsize <= 0; + endcase + if (ENABLE_TRACE) begin + trace_valid <= 1; + trace_data <= (irq_active ? TRACE_IRQ : 0) | TRACE_ADDR | ((reg_op1 + decoded_imm) & 32'hffffffff); + end + reg_op1 <= reg_op1 + decoded_imm; + set_mem_do_wdata = 1; + end + if (!mem_do_prefetch && mem_done) begin + cpu_state <= cpu_state_fetch; + decoder_trigger <= 1; + decoder_pseudo_trigger <= 1; + end + end + end + + cpu_state_ldmem: begin + latched_store <= 1; + if (!mem_do_prefetch || mem_done) begin + if (!mem_do_rdata) begin + (* parallel_case, full_case *) + case (1'b1) + instr_lb || instr_lbu: mem_wordsize <= 2; + instr_lh || instr_lhu: mem_wordsize <= 1; + instr_lw: mem_wordsize <= 0; + endcase + latched_is_lu <= is_lbu_lhu_lw; + latched_is_lh <= instr_lh; + latched_is_lb <= instr_lb; + if (ENABLE_TRACE) begin + trace_valid <= 1; + trace_data <= (irq_active ? TRACE_IRQ : 0) | TRACE_ADDR | ((reg_op1 + decoded_imm) & 32'hffffffff); + end + reg_op1 <= reg_op1 + decoded_imm; + set_mem_do_rdata = 1; + end + if (!mem_do_prefetch && mem_done) begin + (* parallel_case, full_case *) + case (1'b1) + latched_is_lu: reg_out <= mem_rdata_word; + latched_is_lh: reg_out <= $signed(mem_rdata_word[15:0]); + latched_is_lb: reg_out <= $signed(mem_rdata_word[7:0]); + endcase + decoder_trigger <= 1; + decoder_pseudo_trigger <= 1; + cpu_state <= cpu_state_fetch; + end + end + end + endcase + + if (CATCH_MISALIGN && resetn && (mem_do_rdata || mem_do_wdata)) begin + if (mem_wordsize == 0 && reg_op1[1:0] != 0) begin + `debug($display("MISALIGNED WORD: 0x%08x", reg_op1);) + if (ENABLE_IRQ && !irq_mask[irq_buserror] && !irq_active) begin + next_irq_pending[irq_buserror] = 1; + end else + cpu_state <= cpu_state_trap; + end + if (mem_wordsize == 1 && reg_op1[0] != 0) begin + `debug($display("MISALIGNED HALFWORD: 0x%08x", reg_op1);) + if (ENABLE_IRQ && !irq_mask[irq_buserror] && !irq_active) begin + next_irq_pending[irq_buserror] = 1; + end else + cpu_state <= cpu_state_trap; + end + end + if (CATCH_MISALIGN && resetn && mem_do_rinst && (COMPRESSED_ISA ? reg_pc[0] : |reg_pc[1:0])) begin + `debug($display("MISALIGNED INSTRUCTION: 0x%08x", reg_pc);) + if (ENABLE_IRQ && !irq_mask[irq_buserror] && !irq_active) begin + next_irq_pending[irq_buserror] = 1; + end else + cpu_state <= cpu_state_trap; + end + if (!CATCH_ILLINSN && decoder_trigger_q && !decoder_pseudo_trigger_q && instr_ecall_ebreak) begin + cpu_state <= cpu_state_trap; + end + + if (!resetn || mem_done) begin + mem_do_prefetch <= 0; + mem_do_rinst <= 0; + mem_do_rdata <= 0; + mem_do_wdata <= 0; + end + + if (set_mem_do_rinst) + mem_do_rinst <= 1; + if (set_mem_do_rdata) + mem_do_rdata <= 1; + if (set_mem_do_wdata) + mem_do_wdata <= 1; + + irq_pending <= next_irq_pending & ~MASKED_IRQ; + + if (!CATCH_MISALIGN) begin + if (COMPRESSED_ISA) begin + reg_pc[0] <= 0; + reg_next_pc[0] <= 0; + end else begin + reg_pc[1:0] <= 0; + reg_next_pc[1:0] <= 0; + end + end + current_pc = 'bx; + end + +`ifdef RISCV_FORMAL + reg dbg_irq_call; + reg dbg_irq_enter; + reg [31:0] dbg_irq_ret; + always @(posedge clk) begin + rvfi_valid <= resetn && (launch_next_insn || trap) && dbg_valid_insn; + rvfi_order <= resetn ? rvfi_order + rvfi_valid : 0; + + rvfi_insn <= dbg_insn_opcode; + rvfi_rs1_addr <= dbg_rs1val_valid ? dbg_insn_rs1 : 0; + rvfi_rs2_addr <= dbg_rs2val_valid ? dbg_insn_rs2 : 0; + rvfi_pc_rdata <= dbg_insn_addr; + rvfi_rs1_rdata <= dbg_rs1val_valid ? dbg_rs1val : 0; + rvfi_rs2_rdata <= dbg_rs2val_valid ? dbg_rs2val : 0; + rvfi_trap <= trap; + rvfi_halt <= trap; + rvfi_intr <= dbg_irq_enter; + rvfi_mode <= 3; + + if (!resetn) begin + dbg_irq_call <= 0; + dbg_irq_enter <= 0; + end else + if (rvfi_valid) begin + dbg_irq_call <= 0; + dbg_irq_enter <= dbg_irq_call; + end else + if (irq_state == 1) begin + dbg_irq_call <= 1; + dbg_irq_ret <= next_pc; + end + + if (!resetn) begin + rvfi_rd_addr <= 0; + rvfi_rd_wdata <= 0; + end else + if (cpuregs_write && !irq_state) begin + rvfi_rd_addr <= latched_rd; + rvfi_rd_wdata <= latched_rd ? cpuregs_wrdata : 0; + end else + if (rvfi_valid) begin + rvfi_rd_addr <= 0; + rvfi_rd_wdata <= 0; + end + + casez (dbg_insn_opcode) + 32'b 0000000_?????_000??_???_?????_0001011: begin // getq + rvfi_rs1_addr <= 0; + rvfi_rs1_rdata <= 0; + end + 32'b 0000001_?????_?????_???_000??_0001011: begin // setq + rvfi_rd_addr <= 0; + rvfi_rd_wdata <= 0; + end + 32'b 0000010_?????_00000_???_00000_0001011: begin // retirq + rvfi_rs1_addr <= 0; + rvfi_rs1_rdata <= 0; + end + endcase + + if (!dbg_irq_call) begin + if (dbg_mem_instr) begin + rvfi_mem_addr <= 0; + rvfi_mem_rmask <= 0; + rvfi_mem_wmask <= 0; + rvfi_mem_rdata <= 0; + rvfi_mem_wdata <= 0; + end else + if (dbg_mem_valid && dbg_mem_ready) begin + rvfi_mem_addr <= dbg_mem_addr; + rvfi_mem_rmask <= dbg_mem_wstrb ? 0 : ~0; + rvfi_mem_wmask <= dbg_mem_wstrb; + rvfi_mem_rdata <= dbg_mem_rdata; + rvfi_mem_wdata <= dbg_mem_wdata; + end + end + end + + always @* begin + rvfi_pc_wdata = dbg_irq_call ? dbg_irq_ret : dbg_insn_addr; + end +`endif + + // Formal Verification +`ifdef FORMAL + reg [3:0] last_mem_nowait; + always @(posedge clk) + last_mem_nowait <= {last_mem_nowait, mem_ready || !mem_valid}; + + // stall the memory interface for max 4 cycles + restrict property (|last_mem_nowait || mem_ready || !mem_valid); + + // resetn low in first cycle, after that resetn high + restrict property (resetn != $initstate); + + // this just makes it much easier to read traces. uncomment as needed. + // assume property (mem_valid || !mem_ready); + + reg ok; + always @* begin + if (resetn) begin + // instruction fetches are read-only + if (mem_valid && mem_instr) + assert (mem_wstrb == 0); + + // cpu_state must be valid + ok = 0; + if (cpu_state == cpu_state_trap) ok = 1; + if (cpu_state == cpu_state_fetch) ok = 1; + if (cpu_state == cpu_state_ld_rs1) ok = 1; + if (cpu_state == cpu_state_ld_rs2) ok = !ENABLE_REGS_DUALPORT; + if (cpu_state == cpu_state_exec) ok = 1; + if (cpu_state == cpu_state_shift) ok = 1; + if (cpu_state == cpu_state_stmem) ok = 1; + if (cpu_state == cpu_state_ldmem) ok = 1; + assert (ok); + end + end + + reg last_mem_la_read = 0; + reg last_mem_la_write = 0; + reg [31:0] last_mem_la_addr; + reg [31:0] last_mem_la_wdata; + reg [3:0] last_mem_la_wstrb = 0; + + always @(posedge clk) begin + last_mem_la_read <= mem_la_read; + last_mem_la_write <= mem_la_write; + last_mem_la_addr <= mem_la_addr; + last_mem_la_wdata <= mem_la_wdata; + last_mem_la_wstrb <= mem_la_wstrb; + + if (last_mem_la_read) begin + assert(mem_valid); + assert(mem_addr == last_mem_la_addr); + assert(mem_wstrb == 0); + end + if (last_mem_la_write) begin + assert(mem_valid); + assert(mem_addr == last_mem_la_addr); + assert(mem_wdata == last_mem_la_wdata); + assert(mem_wstrb == last_mem_la_wstrb); + end + if (mem_la_read || mem_la_write) begin + assert(!mem_valid || mem_ready); + end + end +`endif +endmodule + +// This is a simple example implementation of PICORV32_REGS. +// Use the PICORV32_REGS mechanism if you want to use custom +// memory resources to implement the processor register file. +// Note that your implementation must match the requirements of +// the PicoRV32 configuration. (e.g. QREGS, etc) +module picorv32_regs ( + input clk, wen, + input [5:0] waddr, + input [5:0] raddr1, + input [5:0] raddr2, + input [31:0] wdata, + output [31:0] rdata1, + output [31:0] rdata2 +); + reg [31:0] regs [0:30]; + + always @(posedge clk) + if (wen) regs[~waddr[4:0]] <= wdata; + + assign rdata1 = regs[~raddr1[4:0]]; + assign rdata2 = regs[~raddr2[4:0]]; +endmodule + + +/*************************************************************** + * picorv32_pcpi_mul + ***************************************************************/ + +module picorv32_pcpi_mul #( + parameter STEPS_AT_ONCE = 1, + parameter CARRY_CHAIN = 4 +) ( + input clk, resetn, + + input pcpi_valid, + input [31:0] pcpi_insn, + input [31:0] pcpi_rs1, + input [31:0] pcpi_rs2, + output reg pcpi_wr, + output reg [31:0] pcpi_rd, + output reg pcpi_wait, + output reg pcpi_ready +); + reg instr_mul, instr_mulh, instr_mulhsu, instr_mulhu; + wire instr_any_mul = |{instr_mul, instr_mulh, instr_mulhsu, instr_mulhu}; + wire instr_any_mulh = |{instr_mulh, instr_mulhsu, instr_mulhu}; + wire instr_rs1_signed = |{instr_mulh, instr_mulhsu}; + wire instr_rs2_signed = |{instr_mulh}; + + reg pcpi_wait_q; + wire mul_start = pcpi_wait && !pcpi_wait_q; + + always @(posedge clk) begin + instr_mul <= 0; + instr_mulh <= 0; + instr_mulhsu <= 0; + instr_mulhu <= 0; + + if (resetn && pcpi_valid && pcpi_insn[6:0] == 7'b0110011 && pcpi_insn[31:25] == 7'b0000001) begin + case (pcpi_insn[14:12]) + 3'b000: instr_mul <= 1; + 3'b001: instr_mulh <= 1; + 3'b010: instr_mulhsu <= 1; + 3'b011: instr_mulhu <= 1; + endcase + end + + pcpi_wait <= instr_any_mul; + pcpi_wait_q <= pcpi_wait; + end + + reg [63:0] rs1, rs2, rd, rdx; + reg [63:0] next_rs1, next_rs2, this_rs2; + reg [63:0] next_rd, next_rdx, next_rdt; + reg [6:0] mul_counter; + reg mul_waiting; + reg mul_finish; + integer i, j; + + // carry save accumulator + always @* begin + next_rd = rd; + next_rdx = rdx; + next_rs1 = rs1; + next_rs2 = rs2; + + for (i = 0; i < STEPS_AT_ONCE; i=i+1) begin + this_rs2 = next_rs1[0] ? next_rs2 : 0; + if (CARRY_CHAIN == 0) begin + next_rdt = next_rd ^ next_rdx ^ this_rs2; + next_rdx = ((next_rd & next_rdx) | (next_rd & this_rs2) | (next_rdx & this_rs2)) << 1; + next_rd = next_rdt; + end else begin + next_rdt = 0; + for (j = 0; j < 64; j = j + CARRY_CHAIN) + {next_rdt[j+CARRY_CHAIN-1], next_rd[j +: CARRY_CHAIN]} = + next_rd[j +: CARRY_CHAIN] + next_rdx[j +: CARRY_CHAIN] + this_rs2[j +: CARRY_CHAIN]; + next_rdx = next_rdt << 1; + end + next_rs1 = next_rs1 >> 1; + next_rs2 = next_rs2 << 1; + end + end + + always @(posedge clk) begin + mul_finish <= 0; + if (!resetn) begin + mul_waiting <= 1; + end else + if (mul_waiting) begin + if (instr_rs1_signed) + rs1 <= $signed(pcpi_rs1); + else + rs1 <= $unsigned(pcpi_rs1); + + if (instr_rs2_signed) + rs2 <= $signed(pcpi_rs2); + else + rs2 <= $unsigned(pcpi_rs2); + + rd <= 0; + rdx <= 0; + mul_counter <= (instr_any_mulh ? 63 - STEPS_AT_ONCE : 31 - STEPS_AT_ONCE); + mul_waiting <= !mul_start; + end else begin + rd <= next_rd; + rdx <= next_rdx; + rs1 <= next_rs1; + rs2 <= next_rs2; + + mul_counter <= mul_counter - STEPS_AT_ONCE; + if (mul_counter[6]) begin + mul_finish <= 1; + mul_waiting <= 1; + end + end + end + + always @(posedge clk) begin + pcpi_wr <= 0; + pcpi_ready <= 0; + if (mul_finish && resetn) begin + pcpi_wr <= 1; + pcpi_ready <= 1; + pcpi_rd <= instr_any_mulh ? rd >> 32 : rd; + end + end +endmodule + +module picorv32_pcpi_fast_mul #( + parameter EXTRA_MUL_FFS = 0, + parameter EXTRA_INSN_FFS = 0, + parameter MUL_CLKGATE = 0 +) ( + input clk, resetn, + + input pcpi_valid, + input [31:0] pcpi_insn, + input [31:0] pcpi_rs1, + input [31:0] pcpi_rs2, + output pcpi_wr, + output [31:0] pcpi_rd, + output pcpi_wait, + output pcpi_ready +); + reg instr_mul, instr_mulh, instr_mulhsu, instr_mulhu; + wire instr_any_mul = |{instr_mul, instr_mulh, instr_mulhsu, instr_mulhu}; + wire instr_any_mulh = |{instr_mulh, instr_mulhsu, instr_mulhu}; + wire instr_rs1_signed = |{instr_mulh, instr_mulhsu}; + wire instr_rs2_signed = |{instr_mulh}; + + reg shift_out; + reg [3:0] active; + reg [32:0] rs1, rs2, rs1_q, rs2_q; + reg [63:0] rd, rd_q; + + wire pcpi_insn_valid = pcpi_valid && pcpi_insn[6:0] == 7'b0110011 && pcpi_insn[31:25] == 7'b0000001; + reg pcpi_insn_valid_q; + + always @* begin + instr_mul = 0; + instr_mulh = 0; + instr_mulhsu = 0; + instr_mulhu = 0; + + if (resetn && (EXTRA_INSN_FFS ? pcpi_insn_valid_q : pcpi_insn_valid)) begin + case (pcpi_insn[14:12]) + 3'b000: instr_mul = 1; + 3'b001: instr_mulh = 1; + 3'b010: instr_mulhsu = 1; + 3'b011: instr_mulhu = 1; + endcase + end + end + + always @(posedge clk) begin + pcpi_insn_valid_q <= pcpi_insn_valid; + if (!MUL_CLKGATE || active[0]) begin + rs1_q <= rs1; + rs2_q <= rs2; + end + if (!MUL_CLKGATE || active[1]) begin + rd <= $signed(EXTRA_MUL_FFS ? rs1_q : rs1) * $signed(EXTRA_MUL_FFS ? rs2_q : rs2); + end + if (!MUL_CLKGATE || active[2]) begin + rd_q <= rd; + end + end + + always @(posedge clk) begin + if (instr_any_mul && !(EXTRA_MUL_FFS ? active[3:0] : active[1:0])) begin + if (instr_rs1_signed) + rs1 <= $signed(pcpi_rs1); + else + rs1 <= $unsigned(pcpi_rs1); + + if (instr_rs2_signed) + rs2 <= $signed(pcpi_rs2); + else + rs2 <= $unsigned(pcpi_rs2); + active[0] <= 1; + end else begin + active[0] <= 0; + end + + active[3:1] <= active; + shift_out <= instr_any_mulh; + + if (!resetn) + active <= 0; + end + + assign pcpi_wr = active[EXTRA_MUL_FFS ? 3 : 1]; + assign pcpi_wait = 0; + assign pcpi_ready = active[EXTRA_MUL_FFS ? 3 : 1]; +`ifdef RISCV_FORMAL_ALTOPS + assign pcpi_rd = + instr_mul ? (pcpi_rs1 + pcpi_rs2) ^ 32'h5876063e : + instr_mulh ? (pcpi_rs1 + pcpi_rs2) ^ 32'hf6583fb7 : + instr_mulhsu ? (pcpi_rs1 - pcpi_rs2) ^ 32'hecfbe137 : + instr_mulhu ? (pcpi_rs1 + pcpi_rs2) ^ 32'h949ce5e8 : 1'bx; +`else + assign pcpi_rd = shift_out ? (EXTRA_MUL_FFS ? rd_q : rd) >> 32 : (EXTRA_MUL_FFS ? rd_q : rd); +`endif +endmodule + + +/*************************************************************** + * picorv32_pcpi_div + ***************************************************************/ + +module picorv32_pcpi_div ( + input clk, resetn, + + input pcpi_valid, + input [31:0] pcpi_insn, + input [31:0] pcpi_rs1, + input [31:0] pcpi_rs2, + output reg pcpi_wr, + output reg [31:0] pcpi_rd, + output reg pcpi_wait, + output reg pcpi_ready +); + reg instr_div, instr_divu, instr_rem, instr_remu; + wire instr_any_div_rem = |{instr_div, instr_divu, instr_rem, instr_remu}; + + reg pcpi_wait_q; + wire start = pcpi_wait && !pcpi_wait_q; + + always @(posedge clk) begin + instr_div <= 0; + instr_divu <= 0; + instr_rem <= 0; + instr_remu <= 0; + + if (resetn && pcpi_valid && !pcpi_ready && pcpi_insn[6:0] == 7'b0110011 && pcpi_insn[31:25] == 7'b0000001) begin + case (pcpi_insn[14:12]) + 3'b100: instr_div <= 1; + 3'b101: instr_divu <= 1; + 3'b110: instr_rem <= 1; + 3'b111: instr_remu <= 1; + endcase + end + + pcpi_wait <= instr_any_div_rem && resetn; + pcpi_wait_q <= pcpi_wait && resetn; + end + + reg [31:0] dividend; + reg [62:0] divisor; + reg [31:0] quotient; + reg [31:0] quotient_msk; + reg running; + reg outsign; + + always @(posedge clk) begin + pcpi_ready <= 0; + pcpi_wr <= 0; + pcpi_rd <= 'bx; + + if (!resetn) begin + running <= 0; + end else + if (start) begin + running <= 1; + dividend <= (instr_div || instr_rem) && pcpi_rs1[31] ? -pcpi_rs1 : pcpi_rs1; + divisor <= ((instr_div || instr_rem) && pcpi_rs2[31] ? -pcpi_rs2 : pcpi_rs2) << 31; + outsign <= (instr_div && (pcpi_rs1[31] != pcpi_rs2[31]) && |pcpi_rs2) || (instr_rem && pcpi_rs1[31]); + quotient <= 0; + quotient_msk <= 1 << 31; + end else + if (!quotient_msk && running) begin + running <= 0; + pcpi_ready <= 1; + pcpi_wr <= 1; +`ifdef RISCV_FORMAL_ALTOPS + case (1) + instr_div: pcpi_rd <= (pcpi_rs1 - pcpi_rs2) ^ 32'h7f8529ec; + instr_divu: pcpi_rd <= (pcpi_rs1 - pcpi_rs2) ^ 32'h10e8fd70; + instr_rem: pcpi_rd <= (pcpi_rs1 - pcpi_rs2) ^ 32'h8da68fa5; + instr_remu: pcpi_rd <= (pcpi_rs1 - pcpi_rs2) ^ 32'h3138d0e1; + endcase +`else + if (instr_div || instr_divu) + pcpi_rd <= outsign ? -quotient : quotient; + else + pcpi_rd <= outsign ? -dividend : dividend; +`endif + end else begin + if (divisor <= dividend) begin + dividend <= dividend - divisor; + quotient <= quotient | quotient_msk; + end + divisor <= divisor >> 1; +`ifdef RISCV_FORMAL_ALTOPS + quotient_msk <= quotient_msk >> 5; +`else + quotient_msk <= quotient_msk >> 1; +`endif + end + end +endmodule + + +/*************************************************************** + * picorv32_axi + ***************************************************************/ + +module picorv32_axi #( + parameter [ 0:0] ENABLE_COUNTERS = 1, + parameter [ 0:0] ENABLE_COUNTERS64 = 1, + parameter [ 0:0] ENABLE_REGS_16_31 = 1, + parameter [ 0:0] ENABLE_REGS_DUALPORT = 1, + parameter [ 0:0] TWO_STAGE_SHIFT = 1, + parameter [ 0:0] BARREL_SHIFTER = 0, + parameter [ 0:0] TWO_CYCLE_COMPARE = 0, + parameter [ 0:0] TWO_CYCLE_ALU = 0, + parameter [ 0:0] COMPRESSED_ISA = 0, + parameter [ 0:0] CATCH_MISALIGN = 1, + parameter [ 0:0] CATCH_ILLINSN = 1, + parameter [ 0:0] ENABLE_PCPI = 0, + parameter [ 0:0] ENABLE_MUL = 0, + parameter [ 0:0] ENABLE_FAST_MUL = 0, + parameter [ 0:0] ENABLE_DIV = 0, + parameter [ 0:0] ENABLE_IRQ = 0, + parameter [ 0:0] ENABLE_IRQ_QREGS = 1, + parameter [ 0:0] ENABLE_IRQ_TIMER = 1, + parameter [ 0:0] ENABLE_TRACE = 0, + parameter [ 0:0] REGS_INIT_ZERO = 0, + parameter [31:0] MASKED_IRQ = 32'h 0000_0000, + parameter [31:0] LATCHED_IRQ = 32'h ffff_ffff, + parameter [31:0] PROGADDR_RESET = 32'h 0000_0000, + parameter [31:0] PROGADDR_IRQ = 32'h 0000_0010, + parameter [31:0] STACKADDR = 32'h ffff_ffff +) ( + input clk, resetn, + output trap, + + // AXI4-lite master memory interface + + output mem_axi_awvalid, + input mem_axi_awready, + output [31:0] mem_axi_awaddr, + output [ 2:0] mem_axi_awprot, + + output mem_axi_wvalid, + input mem_axi_wready, + output [31:0] mem_axi_wdata, + output [ 3:0] mem_axi_wstrb, + + input mem_axi_bvalid, + output mem_axi_bready, + + output mem_axi_arvalid, + input mem_axi_arready, + output [31:0] mem_axi_araddr, + output [ 2:0] mem_axi_arprot, + + input mem_axi_rvalid, + output mem_axi_rready, + input [31:0] mem_axi_rdata, + + // Pico Co-Processor Interface (PCPI) + output pcpi_valid, + output [31:0] pcpi_insn, + output [31:0] pcpi_rs1, + output [31:0] pcpi_rs2, + input pcpi_wr, + input [31:0] pcpi_rd, + input pcpi_wait, + input pcpi_ready, + + // IRQ interface + input [31:0] irq, + output [31:0] eoi, + +`ifdef RISCV_FORMAL + output rvfi_valid, + output [63:0] rvfi_order, + output [31:0] rvfi_insn, + output rvfi_trap, + output rvfi_halt, + output rvfi_intr, + output [ 4:0] rvfi_rs1_addr, + output [ 4:0] rvfi_rs2_addr, + output [31:0] rvfi_rs1_rdata, + output [31:0] rvfi_rs2_rdata, + output [ 4:0] rvfi_rd_addr, + output [31:0] rvfi_rd_wdata, + output [31:0] rvfi_pc_rdata, + output [31:0] rvfi_pc_wdata, + output [31:0] rvfi_mem_addr, + output [ 3:0] rvfi_mem_rmask, + output [ 3:0] rvfi_mem_wmask, + output [31:0] rvfi_mem_rdata, + output [31:0] rvfi_mem_wdata, +`endif + + // Trace Interface + output trace_valid, + output [35:0] trace_data +); + wire mem_valid; + wire [31:0] mem_addr; + wire [31:0] mem_wdata; + wire [ 3:0] mem_wstrb; + wire mem_instr; + wire mem_ready; + wire [31:0] mem_rdata; + + picorv32_axi_adapter axi_adapter ( + .clk (clk ), + .resetn (resetn ), + .mem_axi_awvalid(mem_axi_awvalid), + .mem_axi_awready(mem_axi_awready), + .mem_axi_awaddr (mem_axi_awaddr ), + .mem_axi_awprot (mem_axi_awprot ), + .mem_axi_wvalid (mem_axi_wvalid ), + .mem_axi_wready (mem_axi_wready ), + .mem_axi_wdata (mem_axi_wdata ), + .mem_axi_wstrb (mem_axi_wstrb ), + .mem_axi_bvalid (mem_axi_bvalid ), + .mem_axi_bready (mem_axi_bready ), + .mem_axi_arvalid(mem_axi_arvalid), + .mem_axi_arready(mem_axi_arready), + .mem_axi_araddr (mem_axi_araddr ), + .mem_axi_arprot (mem_axi_arprot ), + .mem_axi_rvalid (mem_axi_rvalid ), + .mem_axi_rready (mem_axi_rready ), + .mem_axi_rdata (mem_axi_rdata ), + .mem_valid (mem_valid ), + .mem_instr (mem_instr ), + .mem_ready (mem_ready ), + .mem_addr (mem_addr ), + .mem_wdata (mem_wdata ), + .mem_wstrb (mem_wstrb ), + .mem_rdata (mem_rdata ) + ); + + picorv32 #( + .ENABLE_COUNTERS (ENABLE_COUNTERS ), + .ENABLE_COUNTERS64 (ENABLE_COUNTERS64 ), + .ENABLE_REGS_16_31 (ENABLE_REGS_16_31 ), + .ENABLE_REGS_DUALPORT(ENABLE_REGS_DUALPORT), + .TWO_STAGE_SHIFT (TWO_STAGE_SHIFT ), + .BARREL_SHIFTER (BARREL_SHIFTER ), + .TWO_CYCLE_COMPARE (TWO_CYCLE_COMPARE ), + .TWO_CYCLE_ALU (TWO_CYCLE_ALU ), + .COMPRESSED_ISA (COMPRESSED_ISA ), + .CATCH_MISALIGN (CATCH_MISALIGN ), + .CATCH_ILLINSN (CATCH_ILLINSN ), + .ENABLE_PCPI (ENABLE_PCPI ), + .ENABLE_MUL (ENABLE_MUL ), + .ENABLE_FAST_MUL (ENABLE_FAST_MUL ), + .ENABLE_DIV (ENABLE_DIV ), + .ENABLE_IRQ (ENABLE_IRQ ), + .ENABLE_IRQ_QREGS (ENABLE_IRQ_QREGS ), + .ENABLE_IRQ_TIMER (ENABLE_IRQ_TIMER ), + .ENABLE_TRACE (ENABLE_TRACE ), + .REGS_INIT_ZERO (REGS_INIT_ZERO ), + .MASKED_IRQ (MASKED_IRQ ), + .LATCHED_IRQ (LATCHED_IRQ ), + .PROGADDR_RESET (PROGADDR_RESET ), + .PROGADDR_IRQ (PROGADDR_IRQ ), + .STACKADDR (STACKADDR ) + ) picorv32_core ( + .clk (clk ), + .resetn (resetn), + .trap (trap ), + + .mem_valid(mem_valid), + .mem_addr (mem_addr ), + .mem_wdata(mem_wdata), + .mem_wstrb(mem_wstrb), + .mem_instr(mem_instr), + .mem_ready(mem_ready), + .mem_rdata(mem_rdata), + + .pcpi_valid(pcpi_valid), + .pcpi_insn (pcpi_insn ), + .pcpi_rs1 (pcpi_rs1 ), + .pcpi_rs2 (pcpi_rs2 ), + .pcpi_wr (pcpi_wr ), + .pcpi_rd (pcpi_rd ), + .pcpi_wait (pcpi_wait ), + .pcpi_ready(pcpi_ready), + + .irq(irq), + .eoi(eoi), + +`ifdef RISCV_FORMAL + .rvfi_valid (rvfi_valid ), + .rvfi_order (rvfi_order ), + .rvfi_insn (rvfi_insn ), + .rvfi_trap (rvfi_trap ), + .rvfi_halt (rvfi_halt ), + .rvfi_intr (rvfi_intr ), + .rvfi_rs1_addr (rvfi_rs1_addr ), + .rvfi_rs2_addr (rvfi_rs2_addr ), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_rd_addr (rvfi_rd_addr ), + .rvfi_rd_wdata (rvfi_rd_wdata ), + .rvfi_pc_rdata (rvfi_pc_rdata ), + .rvfi_pc_wdata (rvfi_pc_wdata ), + .rvfi_mem_addr (rvfi_mem_addr ), + .rvfi_mem_rmask(rvfi_mem_rmask), + .rvfi_mem_wmask(rvfi_mem_wmask), + .rvfi_mem_rdata(rvfi_mem_rdata), + .rvfi_mem_wdata(rvfi_mem_wdata), +`endif + + .trace_valid(trace_valid), + .trace_data (trace_data) + ); +endmodule + + +/*************************************************************** + * picorv32_axi_adapter + ***************************************************************/ + +module picorv32_axi_adapter ( + input clk, resetn, + + // AXI4-lite master memory interface + + output mem_axi_awvalid, + input mem_axi_awready, + output [31:0] mem_axi_awaddr, + output [ 2:0] mem_axi_awprot, + + output mem_axi_wvalid, + input mem_axi_wready, + output [31:0] mem_axi_wdata, + output [ 3:0] mem_axi_wstrb, + + input mem_axi_bvalid, + output mem_axi_bready, + + output mem_axi_arvalid, + input mem_axi_arready, + output [31:0] mem_axi_araddr, + output [ 2:0] mem_axi_arprot, + + input mem_axi_rvalid, + output mem_axi_rready, + input [31:0] mem_axi_rdata, + + // Native PicoRV32 memory interface + + input mem_valid, + input mem_instr, + output mem_ready, + input [31:0] mem_addr, + input [31:0] mem_wdata, + input [ 3:0] mem_wstrb, + output [31:0] mem_rdata +); + reg ack_awvalid; + reg ack_arvalid; + reg ack_wvalid; + reg xfer_done; + + assign mem_axi_awvalid = mem_valid && |mem_wstrb && !ack_awvalid; + assign mem_axi_awaddr = mem_addr; + assign mem_axi_awprot = 0; + + assign mem_axi_arvalid = mem_valid && !mem_wstrb && !ack_arvalid; + assign mem_axi_araddr = mem_addr; + assign mem_axi_arprot = mem_instr ? 3'b100 : 3'b000; + + assign mem_axi_wvalid = mem_valid && |mem_wstrb && !ack_wvalid; + assign mem_axi_wdata = mem_wdata; + assign mem_axi_wstrb = mem_wstrb; + + assign mem_ready = mem_axi_bvalid || mem_axi_rvalid; + assign mem_axi_bready = mem_valid && |mem_wstrb; + assign mem_axi_rready = mem_valid && !mem_wstrb; + assign mem_rdata = mem_axi_rdata; + + always @(posedge clk) begin + if (!resetn) begin + ack_awvalid <= 0; + end else begin + xfer_done <= mem_valid && mem_ready; + if (mem_axi_awready && mem_axi_awvalid) + ack_awvalid <= 1; + if (mem_axi_arready && mem_axi_arvalid) + ack_arvalid <= 1; + if (mem_axi_wready && mem_axi_wvalid) + ack_wvalid <= 1; + if (xfer_done || !mem_valid) begin + ack_awvalid <= 0; + ack_arvalid <= 0; + ack_wvalid <= 0; + end + end + end +endmodule + + +/*************************************************************** + * picorv32_wb + ***************************************************************/ + +module picorv32_wb #( + parameter [ 0:0] ENABLE_COUNTERS = 1, + parameter [ 0:0] ENABLE_COUNTERS64 = 1, + parameter [ 0:0] ENABLE_REGS_16_31 = 1, + parameter [ 0:0] ENABLE_REGS_DUALPORT = 1, + parameter [ 0:0] TWO_STAGE_SHIFT = 1, + parameter [ 0:0] BARREL_SHIFTER = 0, + parameter [ 0:0] TWO_CYCLE_COMPARE = 0, + parameter [ 0:0] TWO_CYCLE_ALU = 0, + parameter [ 0:0] COMPRESSED_ISA = 0, + parameter [ 0:0] CATCH_MISALIGN = 1, + parameter [ 0:0] CATCH_ILLINSN = 1, + parameter [ 0:0] ENABLE_PCPI = 0, + parameter [ 0:0] ENABLE_MUL = 0, + parameter [ 0:0] ENABLE_FAST_MUL = 0, + parameter [ 0:0] ENABLE_DIV = 0, + parameter [ 0:0] ENABLE_IRQ = 0, + parameter [ 0:0] ENABLE_IRQ_QREGS = 1, + parameter [ 0:0] ENABLE_IRQ_TIMER = 1, + parameter [ 0:0] ENABLE_TRACE = 0, + parameter [ 0:0] REGS_INIT_ZERO = 0, + parameter [31:0] MASKED_IRQ = 32'h 0000_0000, + parameter [31:0] LATCHED_IRQ = 32'h ffff_ffff, + parameter [31:0] PROGADDR_RESET = 32'h 0000_0000, + parameter [31:0] PROGADDR_IRQ = 32'h 0000_0010, + parameter [31:0] STACKADDR = 32'h ffff_ffff +) ( + output trap, + + // Wishbone interfaces + input wb_rst_i, + input wb_clk_i, + + output reg [31:0] wbm_adr_o, + output reg [31:0] wbm_dat_o, + input [31:0] wbm_dat_i, + output reg wbm_we_o, + output reg [3:0] wbm_sel_o, + output reg wbm_stb_o, + input wbm_ack_i, + output reg wbm_cyc_o, + + // Pico Co-Processor Interface (PCPI) + output pcpi_valid, + output [31:0] pcpi_insn, + output [31:0] pcpi_rs1, + output [31:0] pcpi_rs2, + input pcpi_wr, + input [31:0] pcpi_rd, + input pcpi_wait, + input pcpi_ready, + + // IRQ interface + input [31:0] irq, + output [31:0] eoi, + +`ifdef RISCV_FORMAL + output rvfi_valid, + output [63:0] rvfi_order, + output [31:0] rvfi_insn, + output rvfi_trap, + output rvfi_halt, + output rvfi_intr, + output [ 4:0] rvfi_rs1_addr, + output [ 4:0] rvfi_rs2_addr, + output [31:0] rvfi_rs1_rdata, + output [31:0] rvfi_rs2_rdata, + output [ 4:0] rvfi_rd_addr, + output [31:0] rvfi_rd_wdata, + output [31:0] rvfi_pc_rdata, + output [31:0] rvfi_pc_wdata, + output [31:0] rvfi_mem_addr, + output [ 3:0] rvfi_mem_rmask, + output [ 3:0] rvfi_mem_wmask, + output [31:0] rvfi_mem_rdata, + output [31:0] rvfi_mem_wdata, +`endif + + // Trace Interface + output trace_valid, + output [35:0] trace_data, + + output mem_instr +); + wire mem_valid; + wire [31:0] mem_addr; + wire [31:0] mem_wdata; + wire [ 3:0] mem_wstrb; + reg mem_ready; + reg [31:0] mem_rdata; + + wire clk; + wire resetn; + + assign clk = wb_clk_i; + assign resetn = ~wb_rst_i; + + picorv32 #( + .ENABLE_COUNTERS (ENABLE_COUNTERS ), + .ENABLE_COUNTERS64 (ENABLE_COUNTERS64 ), + .ENABLE_REGS_16_31 (ENABLE_REGS_16_31 ), + .ENABLE_REGS_DUALPORT(ENABLE_REGS_DUALPORT), + .TWO_STAGE_SHIFT (TWO_STAGE_SHIFT ), + .BARREL_SHIFTER (BARREL_SHIFTER ), + .TWO_CYCLE_COMPARE (TWO_CYCLE_COMPARE ), + .TWO_CYCLE_ALU (TWO_CYCLE_ALU ), + .COMPRESSED_ISA (COMPRESSED_ISA ), + .CATCH_MISALIGN (CATCH_MISALIGN ), + .CATCH_ILLINSN (CATCH_ILLINSN ), + .ENABLE_PCPI (ENABLE_PCPI ), + .ENABLE_MUL (ENABLE_MUL ), + .ENABLE_FAST_MUL (ENABLE_FAST_MUL ), + .ENABLE_DIV (ENABLE_DIV ), + .ENABLE_IRQ (ENABLE_IRQ ), + .ENABLE_IRQ_QREGS (ENABLE_IRQ_QREGS ), + .ENABLE_IRQ_TIMER (ENABLE_IRQ_TIMER ), + .ENABLE_TRACE (ENABLE_TRACE ), + .REGS_INIT_ZERO (REGS_INIT_ZERO ), + .MASKED_IRQ (MASKED_IRQ ), + .LATCHED_IRQ (LATCHED_IRQ ), + .PROGADDR_RESET (PROGADDR_RESET ), + .PROGADDR_IRQ (PROGADDR_IRQ ), + .STACKADDR (STACKADDR ) + ) picorv32_core ( + .clk (clk ), + .resetn (resetn), + .trap (trap ), + + .mem_valid(mem_valid), + .mem_addr (mem_addr ), + .mem_wdata(mem_wdata), + .mem_wstrb(mem_wstrb), + .mem_instr(mem_instr), + .mem_ready(mem_ready), + .mem_rdata(mem_rdata), + + .pcpi_valid(pcpi_valid), + .pcpi_insn (pcpi_insn ), + .pcpi_rs1 (pcpi_rs1 ), + .pcpi_rs2 (pcpi_rs2 ), + .pcpi_wr (pcpi_wr ), + .pcpi_rd (pcpi_rd ), + .pcpi_wait (pcpi_wait ), + .pcpi_ready(pcpi_ready), + + .irq(irq), + .eoi(eoi), + +`ifdef RISCV_FORMAL + .rvfi_valid (rvfi_valid ), + .rvfi_order (rvfi_order ), + .rvfi_insn (rvfi_insn ), + .rvfi_trap (rvfi_trap ), + .rvfi_halt (rvfi_halt ), + .rvfi_intr (rvfi_intr ), + .rvfi_rs1_addr (rvfi_rs1_addr ), + .rvfi_rs2_addr (rvfi_rs2_addr ), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_rd_addr (rvfi_rd_addr ), + .rvfi_rd_wdata (rvfi_rd_wdata ), + .rvfi_pc_rdata (rvfi_pc_rdata ), + .rvfi_pc_wdata (rvfi_pc_wdata ), + .rvfi_mem_addr (rvfi_mem_addr ), + .rvfi_mem_rmask(rvfi_mem_rmask), + .rvfi_mem_wmask(rvfi_mem_wmask), + .rvfi_mem_rdata(rvfi_mem_rdata), + .rvfi_mem_wdata(rvfi_mem_wdata), +`endif + + .trace_valid(trace_valid), + .trace_data (trace_data) + ); + + localparam IDLE = 2'b00; + localparam WBSTART = 2'b01; + localparam WBEND = 2'b10; + + reg [1:0] state; + + wire we; + assign we = (mem_wstrb[0] | mem_wstrb[1] | mem_wstrb[2] | mem_wstrb[3]); + + always @(posedge wb_clk_i) begin + if (wb_rst_i) begin + wbm_adr_o <= 0; + wbm_dat_o <= 0; + wbm_we_o <= 0; + wbm_sel_o <= 0; + wbm_stb_o <= 0; + wbm_cyc_o <= 0; + state <= IDLE; + end else begin + case (state) + IDLE: begin + if (mem_valid) begin + wbm_adr_o <= mem_addr; + wbm_dat_o <= mem_wdata; + wbm_we_o <= we; + wbm_sel_o <= mem_wstrb; + + wbm_stb_o <= 1'b1; + wbm_cyc_o <= 1'b1; + state <= WBSTART; + end else begin + mem_ready <= 1'b0; + + wbm_stb_o <= 1'b0; + wbm_cyc_o <= 1'b0; + wbm_we_o <= 1'b0; + end + end + WBSTART:begin + if (wbm_ack_i) begin + mem_rdata <= wbm_dat_i; + mem_ready <= 1'b1; + + state <= WBEND; + + wbm_stb_o <= 1'b0; + wbm_cyc_o <= 1'b0; + wbm_we_o <= 1'b0; + end + end + WBEND: begin + mem_ready <= 1'b0; + + state <= IDLE; + end + default: + state <= IDLE; + endcase + end + end +endmodule diff --git a/ice40/smoketest/attosoc/smoketest.sh b/ice40/smoketest/attosoc/smoketest.sh new file mode 100755 index 00000000..05408ab1 --- /dev/null +++ b/ice40/smoketest/attosoc/smoketest.sh @@ -0,0 +1,9 @@ +#!/usr/bin/env bash +set -ex +yosys -q -p 'synth_ice40 -json attosoc.json -top attosoc' attosoc.v picorv32.v +$NEXTPNR --hx8k --json attosoc.json --pcf attosoc.pcf --asc attosoc.asc --freq 50 +icetime -tmd hx8k -c 50 attosoc.asc +icebox_vlog -L -l -p attosoc.pcf -c -n attosoc attosoc.asc > attosoc_pnr.v +iverilog -o attosoc_pnr_tb attosoc_pnr.v attosoc_tb.v `yosys-config --datdir/ice40/cells_sim.v` +vvp attosoc_pnr_tb +diff output.txt golden.txt diff --git a/json/jsonparse.cc b/json/jsonparse.cc index b953fc7c..a0479c2e 100644 --- a/json/jsonparse.cc +++ b/json/jsonparse.cc @@ -627,7 +627,9 @@ static void insert_iobuf(Context *ctx, NetInfo *net, PortType type, const string iobuf->ports[ctx->id("O")] = PortInfo{ctx->id("O"), net, PORT_OUT}; // Special case: input, etc, directly drives inout if (net->driver.cell != nullptr) { - assert(net->driver.cell->type == ctx->id("$nextpnr_iobuf")); + if (net->driver.cell->type != ctx->id("$nextpnr_iobuf")) + log_error("Top-level input '%s' also driven by %s.%s.\n", name.c_str(), + net->driver.cell->name.c_str(ctx), net->driver.port.c_str(ctx)); net = net->driver.cell->ports.at(ctx->id("I")).net; } assert(net->driver.cell == nullptr); @@ -690,8 +692,28 @@ void json_import(Context *ctx, string modname, JsonNode *node) log_info("Importing module %s\n", modname.c_str()); + // Multiple labels might refer to the same net. For now we resolve conflicts thus: + // - names with fewer $ are always prefered + // - between equal $ counts, fewer .s are prefered + // - ties are resolved alphabetically + auto prefer_netlabel = [](const std::string &a, const std::string &b) { + if (b.empty()) + return true; + long a_dollars = std::count(a.begin(), a.end(), '$'), b_dollars = std::count(b.begin(), b.end(), '$'); + if (a_dollars < b_dollars) + return true; + else if (a_dollars > b_dollars) + return false; + long a_dots = std::count(a.begin(), a.end(), '.'), b_dots = std::count(b.begin(), b.end(), '.'); + if (a_dots < b_dots) + return true; + else if (a_dots > b_dots) + return false; + return a < b; + }; + // Import netnames - std::vector<IdString> netnames; + std::vector<std::string> netlabels; if (node->data_dict.count("netnames")) { JsonNode *cell_parent = node->data_dict.at("netnames"); for (int nnid = 0; nnid < GetSize(cell_parent->data_dict_keys); nnid++) { @@ -705,15 +727,19 @@ void json_import(Context *ctx, string modname, JsonNode *node) size_t num_bits = bits->data_array.size(); for (size_t i = 0; i < num_bits; i++) { int netid = bits->data_array.at(i)->data_number; - if (netid >= int(netnames.size())) - netnames.resize(netid + 1); - netnames.at(netid) = ctx->id( - basename + (num_bits == 1 ? "" : std::string("[") + std::to_string(i) + std::string("]"))); + if (netid >= int(netlabels.size())) + netlabels.resize(netid + 1); + std::string name = + basename + (num_bits == 1 ? "" : std::string("[") + std::to_string(i) + std::string("]")); + if (prefer_netlabel(name, netlabels.at(netid))) + netlabels.at(netid) = name; } } } } - + std::vector<IdString> netids; + std::transform(netlabels.begin(), netlabels.end(), std::back_inserter(netids), + [ctx](const std::string &s) { return ctx->id(s); }); if (node->data_dict.count("cells")) { JsonNode *cell_parent = node->data_dict.at("cells"); // @@ -723,7 +749,7 @@ void json_import(Context *ctx, string modname, JsonNode *node) // for (int cellid = 0; cellid < GetSize(cell_parent->data_dict_keys); cellid++) { JsonNode *here = cell_parent->data_dict.at(cell_parent->data_dict_keys[cellid]); - json_import_cell(ctx, modname, netnames, here, cell_parent->data_dict_keys[cellid]); + json_import_cell(ctx, modname, netids, here, cell_parent->data_dict_keys[cellid]); } } @@ -732,12 +758,27 @@ void json_import(Context *ctx, string modname, JsonNode *node) // N.B. ports must be imported after cells for tristate behaviour // to be correct - // Loop through all ports + // Loop through all ports, first non-tristate then tristate to handle + // interconnected ports correctly for (int portid = 0; portid < GetSize(ports_parent->data_dict_keys); portid++) { JsonNode *here; here = ports_parent->data_dict.at(ports_parent->data_dict_keys[portid]); - json_import_toplevel_port(ctx, modname, netnames, ports_parent->data_dict_keys[portid], here); + JsonNode *dir_node = here->data_dict.at("direction"); + NPNR_ASSERT(dir_node->type == 'S'); + if (dir_node->data_string == "inout") + continue; + json_import_toplevel_port(ctx, modname, netids, ports_parent->data_dict_keys[portid], here); + } + for (int portid = 0; portid < GetSize(ports_parent->data_dict_keys); portid++) { + JsonNode *here; + + here = ports_parent->data_dict.at(ports_parent->data_dict_keys[portid]); + JsonNode *dir_node = here->data_dict.at("direction"); + NPNR_ASSERT(dir_node->type == 'S'); + if (dir_node->data_string != "inout") + continue; + json_import_toplevel_port(ctx, modname, netids, ports_parent->data_dict_keys[portid], here); } } check_all_nets_driven(ctx); diff --git a/tests b/tests new file mode 160000 +Subproject 0d369eb3fe3425fa74c0f6309268a012aac5040 diff --git a/tests/gui/quadtree.cc b/tests/gui/quadtree.cc deleted file mode 100644 index 6711e906..00000000 --- a/tests/gui/quadtree.cc +++ /dev/null @@ -1,122 +0,0 @@ -/* - * nextpnr -- Next Generation Place and Route - * - * Copyright (C) 2018 Serge Bazanski <q3k@symbioticeda.com> - * - * Permission to use, copy, modify, and/or distribute this software for any - * purpose with or without fee is hereby granted, provided that the above - * copyright notice and this permission notice appear in all copies. - * - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF - * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - * - */ - -#include "gtest/gtest.h" -#include "nextpnr.h" - -#include "quadtree.h" - -USING_NEXTPNR_NAMESPACE - -using QT = QuadTree<int, int>; - -class QuadTreeTest : public ::testing::Test -{ - protected: - virtual void SetUp() { qt_ = new QT(QT::BoundingBox(0, 0, width_, height_)); } - virtual void TearDown() { delete qt_; } - - int width_ = 100; - int height_ = 100; - QT *qt_; -}; - -// Test that we're doing bound checking correctly. -TEST_F(QuadTreeTest, insert_bound_checking) -{ - ASSERT_TRUE(qt_->insert(QT::BoundingBox(10, 10, 20, 20), 10)); - ASSERT_TRUE(qt_->insert(QT::BoundingBox(0, 0, 100, 100), 10)); - ASSERT_FALSE(qt_->insert(QT::BoundingBox(10, 10, 101, 20), 10)); - ASSERT_FALSE(qt_->insert(QT::BoundingBox(-1, 10, 101, 20), 10)); - ASSERT_FALSE(qt_->insert(QT::BoundingBox(-1, -1, 20, 20), 10)); -} - -// Test whether we are not losing any elements. -TEST_F(QuadTreeTest, insert_count) -{ - auto rng = NEXTPNR_NAMESPACE::DeterministicRNG(); - - // Add 10000 random rectangles. - for (unsigned int i = 0; i < 10000; i++) { - int x0 = rng.rng(width_); - int y0 = rng.rng(height_); - int w = rng.rng(width_ - x0); - int h = rng.rng(width_ - y0); - int x1 = x0 + w; - int y1 = y0 + h; - ASSERT_TRUE(qt_->insert(QT::BoundingBox(x0, y0, x1, y1), i)); - ASSERT_EQ(qt_->size(), i + 1); - } - // Add 100000 random points. - for (unsigned int i = 0; i < 100000; i++) { - int x0 = rng.rng(width_); - int y0 = rng.rng(height_); - int x1 = x0; - int y1 = y0; - ASSERT_TRUE(qt_->insert(QT::BoundingBox(x0, y0, x1, y1), i)); - ASSERT_EQ(qt_->size(), i + 10001); - } -} - -// Test that we can insert and retrieve the same element. -TEST_F(QuadTreeTest, insert_retrieve_same) -{ - auto rng = NEXTPNR_NAMESPACE::DeterministicRNG(); - - // Add 10000 small random rectangles. - rng.rngseed(0); - for (int i = 0; i < 10000; i++) { - int x0 = rng.rng(width_); - int y0 = rng.rng(height_); - int w = rng.rng(width_ - x0); - int h = rng.rng(width_ - y0); - int x1 = x0 + w / 4; - int y1 = y0 + h / 4; - ASSERT_TRUE(qt_->insert(QT::BoundingBox(x0, y0, x1, y1), i)); - } - - // Restart RNG, make sure we get the same rectangles back. - rng.rngseed(0); - for (int i = 0; i < 10000; i++) { - int x0 = rng.rng(width_); - int y0 = rng.rng(height_); - int w = rng.rng(width_ - x0); - int h = rng.rng(width_ - y0); - int x1 = x0 + w / 4; - int y1 = y0 + h / 4; - - // try to find something in the middle of the square - int x = (x1 - x0) / 2 + x0; - int y = (y1 - y0) / 2 + y0; - - auto res = qt_->get(x, y); - // Somewhat arbirary test to make sure we don't return obscene - // amounts of data. - ASSERT_LT(res.size(), 200UL); - bool found = false; - for (auto elem : res) { - // Is this what we're looking for? - if (elem == i) { - found = true; - break; - } - } - ASSERT_TRUE(found); - } -} diff --git a/tests/ice40/hx1k.cc b/tests/ice40/hx1k.cc deleted file mode 100644 index 741c954b..00000000 --- a/tests/ice40/hx1k.cc +++ /dev/null @@ -1,106 +0,0 @@ -/* - * nextpnr -- Next Generation Place and Route - * - * Copyright (C) 2018 Clifford Wolf <clifford@symbioticeda.com> - * Copyright (C) 2018 Miodrag Milanovic <miodrag@symbioticeda.com> - * - * Permission to use, copy, modify, and/or distribute this software for any - * purpose with or without fee is hereby granted, provided that the above - * copyright notice and this permission notice appear in all copies. - * - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF - * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - * - */ - -#include <vector> -#include "gtest/gtest.h" -#include "nextpnr.h" - -USING_NEXTPNR_NAMESPACE - -class HX1KTest : public ::testing::Test -{ - protected: - virtual void SetUp() - { - chipArgs.type = ArchArgs::HX1K; - chipArgs.package = "tq144"; - ctx = new Context(chipArgs); - } - - virtual void TearDown() { delete ctx; } - - ArchArgs chipArgs; - Context *ctx; -}; - -TEST_F(HX1KTest, bel_names) -{ - int bel_count = 0; - for (auto bel : ctx->getBels()) { - auto name = ctx->getBelName(bel); - ASSERT_EQ(bel, ctx->getBelByName(name)); - bel_count++; - } - ASSERT_EQ(bel_count, 1418); -} - -TEST_F(HX1KTest, wire_names) -{ - int wire_count = 0; - for (auto wire : ctx->getWires()) { - auto name = ctx->getWireName(wire); - assert(wire == ctx->getWireByName(name)); - wire_count++; - } - ASSERT_EQ(wire_count, 32802); -} - -TEST_F(HX1KTest, pip_names) -{ - int pip_count = 0; - for (auto pip : ctx->getPips()) { - auto name = ctx->getPipName(pip); - assert(pip == ctx->getPipByName(name)); - pip_count++; - } - ASSERT_EQ(pip_count, 345504); -} - -TEST_F(HX1KTest, uphill_to_downhill) -{ - for (auto dst : ctx->getWires()) { - for (auto uphill_pip : ctx->getPipsUphill(dst)) { - bool found_downhill = false; - for (auto downhill_pip : ctx->getPipsDownhill(ctx->getPipSrcWire(uphill_pip))) { - if (uphill_pip == downhill_pip) { - ASSERT_FALSE(found_downhill); - found_downhill = true; - } - } - ASSERT_TRUE(found_downhill); - } - } -} - -TEST_F(HX1KTest, downhill_to_uphill) -{ - for (auto dst : ctx->getWires()) { - for (auto downhill_pip : ctx->getPipsDownhill(dst)) { - bool found_uphill = false; - for (auto uphill_pip : ctx->getPipsUphill(ctx->getPipDstWire(downhill_pip))) { - if (uphill_pip == downhill_pip) { - ASSERT_FALSE(found_uphill); - found_uphill = true; - } - } - ASSERT_TRUE(found_uphill); - } - } -} diff --git a/tests/ice40/hx8k.cc b/tests/ice40/hx8k.cc deleted file mode 100644 index 517df0d6..00000000 --- a/tests/ice40/hx8k.cc +++ /dev/null @@ -1,106 +0,0 @@ -/* - * nextpnr -- Next Generation Place and Route - * - * Copyright (C) 2018 Clifford Wolf <clifford@symbioticeda.com> - * Copyright (C) 2018 Miodrag Milanovic <miodrag@symbioticeda.com> - * - * Permission to use, copy, modify, and/or distribute this software for any - * purpose with or without fee is hereby granted, provided that the above - * copyright notice and this permission notice appear in all copies. - * - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF - * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - * - */ - -#include <vector> -#include "gtest/gtest.h" -#include "nextpnr.h" - -USING_NEXTPNR_NAMESPACE - -class HX8KTest : public ::testing::Test -{ - protected: - virtual void SetUp() - { - chipArgs.type = ArchArgs::HX8K; - chipArgs.package = "ct256"; - ctx = new Context(chipArgs); - } - - virtual void TearDown() { delete ctx; } - - ArchArgs chipArgs; - Context *ctx; -}; - -TEST_F(HX8KTest, bel_names) -{ - int bel_count = 0; - for (auto bel : ctx->getBels()) { - auto name = ctx->getBelName(bel); - ASSERT_EQ(bel, ctx->getBelByName(name)); - bel_count++; - } - ASSERT_EQ(bel_count, 7979); -} - -TEST_F(HX8KTest, wire_names) -{ - int wire_count = 0; - for (auto wire : ctx->getWires()) { - auto name = ctx->getWireName(wire); - assert(wire == ctx->getWireByName(name)); - wire_count++; - } - ASSERT_EQ(wire_count, 165894); -} - -TEST_F(HX8KTest, pip_names) -{ - int pip_count = 0; - for (auto pip : ctx->getPips()) { - auto name = ctx->getPipName(pip); - assert(pip == ctx->getPipByName(name)); - pip_count++; - } - ASSERT_EQ(pip_count, 1806080); -} - -TEST_F(HX8KTest, uphill_to_downhill) -{ - for (auto dst : ctx->getWires()) { - for (auto uphill_pip : ctx->getPipsUphill(dst)) { - bool found_downhill = false; - for (auto downhill_pip : ctx->getPipsDownhill(ctx->getPipSrcWire(uphill_pip))) { - if (uphill_pip == downhill_pip) { - ASSERT_FALSE(found_downhill); - found_downhill = true; - } - } - ASSERT_TRUE(found_downhill); - } - } -} - -TEST_F(HX8KTest, downhill_to_uphill) -{ - for (auto dst : ctx->getWires()) { - for (auto downhill_pip : ctx->getPipsDownhill(dst)) { - bool found_uphill = false; - for (auto uphill_pip : ctx->getPipsUphill(ctx->getPipDstWire(downhill_pip))) { - if (uphill_pip == downhill_pip) { - ASSERT_FALSE(found_uphill); - found_uphill = true; - } - } - ASSERT_TRUE(found_uphill); - } - } -} diff --git a/tests/ice40/lp1k.cc b/tests/ice40/lp1k.cc deleted file mode 100644 index 2fdba08b..00000000 --- a/tests/ice40/lp1k.cc +++ /dev/null @@ -1,106 +0,0 @@ -/* - * nextpnr -- Next Generation Place and Route - * - * Copyright (C) 2018 Clifford Wolf <clifford@symbioticeda.com> - * Copyright (C) 2018 Miodrag Milanovic <miodrag@symbioticeda.com> - * - * Permission to use, copy, modify, and/or distribute this software for any - * purpose with or without fee is hereby granted, provided that the above - * copyright notice and this permission notice appear in all copies. - * - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF - * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - * - */ - -#include <vector> -#include "gtest/gtest.h" -#include "nextpnr.h" - -USING_NEXTPNR_NAMESPACE - -class LP1KTest : public ::testing::Test -{ - protected: - virtual void SetUp() - { - chipArgs.type = ArchArgs::LP1K; - chipArgs.package = "tq144"; - ctx = new Context(chipArgs); - } - - virtual void TearDown() { delete ctx; } - - ArchArgs chipArgs; - Context *ctx; -}; - -TEST_F(LP1KTest, bel_names) -{ - int bel_count = 0; - for (auto bel : ctx->getBels()) { - auto name = ctx->getBelName(bel); - ASSERT_EQ(bel, ctx->getBelByName(name)); - bel_count++; - } - ASSERT_EQ(bel_count, 1418); -} - -TEST_F(LP1KTest, wire_names) -{ - int wire_count = 0; - for (auto wire : ctx->getWires()) { - auto name = ctx->getWireName(wire); - assert(wire == ctx->getWireByName(name)); - wire_count++; - } - ASSERT_EQ(wire_count, 32802); -} - -TEST_F(LP1KTest, pip_names) -{ - int pip_count = 0; - for (auto pip : ctx->getPips()) { - auto name = ctx->getPipName(pip); - assert(pip == ctx->getPipByName(name)); - pip_count++; - } - ASSERT_EQ(pip_count, 345504); -} - -TEST_F(LP1KTest, uphill_to_downhill) -{ - for (auto dst : ctx->getWires()) { - for (auto uphill_pip : ctx->getPipsUphill(dst)) { - bool found_downhill = false; - for (auto downhill_pip : ctx->getPipsDownhill(ctx->getPipSrcWire(uphill_pip))) { - if (uphill_pip == downhill_pip) { - ASSERT_FALSE(found_downhill); - found_downhill = true; - } - } - ASSERT_TRUE(found_downhill); - } - } -} - -TEST_F(LP1KTest, downhill_to_uphill) -{ - for (auto dst : ctx->getWires()) { - for (auto downhill_pip : ctx->getPipsDownhill(dst)) { - bool found_uphill = false; - for (auto uphill_pip : ctx->getPipsUphill(ctx->getPipDstWire(downhill_pip))) { - if (uphill_pip == downhill_pip) { - ASSERT_FALSE(found_uphill); - found_uphill = true; - } - } - ASSERT_TRUE(found_uphill); - } - } -} diff --git a/tests/ice40/lp384.cc b/tests/ice40/lp384.cc deleted file mode 100644 index a030b77b..00000000 --- a/tests/ice40/lp384.cc +++ /dev/null @@ -1,106 +0,0 @@ -/* - * nextpnr -- Next Generation Place and Route - * - * Copyright (C) 2018 Clifford Wolf <clifford@symbioticeda.com> - * Copyright (C) 2018 Miodrag Milanovic <miodrag@symbioticeda.com> - * - * Permission to use, copy, modify, and/or distribute this software for any - * purpose with or without fee is hereby granted, provided that the above - * copyright notice and this permission notice appear in all copies. - * - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF - * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - * - */ - -#include <vector> -#include "gtest/gtest.h" -#include "nextpnr.h" - -USING_NEXTPNR_NAMESPACE - -class LP384Test : public ::testing::Test -{ - protected: - virtual void SetUp() - { - chipArgs.type = ArchArgs::LP384; - chipArgs.package = "qn32"; - ctx = new Context(chipArgs); - } - - virtual void TearDown() { delete ctx; } - - ArchArgs chipArgs; - Context *ctx; -}; - -TEST_F(LP384Test, bel_names) -{ - int bel_count = 0; - for (auto bel : ctx->getBels()) { - auto name = ctx->getBelName(bel); - ASSERT_EQ(bel, ctx->getBelByName(name)); - bel_count++; - } - ASSERT_EQ(bel_count, 449); -} - -TEST_F(LP384Test, wire_names) -{ - int wire_count = 0; - for (auto wire : ctx->getWires()) { - auto name = ctx->getWireName(wire); - assert(wire == ctx->getWireByName(name)); - wire_count++; - } - ASSERT_EQ(wire_count, 9830); -} - -TEST_F(LP384Test, pip_names) -{ - int pip_count = 0; - for (auto pip : ctx->getPips()) { - auto name = ctx->getPipName(pip); - assert(pip == ctx->getPipByName(name)); - pip_count++; - } - ASSERT_EQ(pip_count, 94544); -} - -TEST_F(LP384Test, uphill_to_downhill) -{ - for (auto dst : ctx->getWires()) { - for (auto uphill_pip : ctx->getPipsUphill(dst)) { - bool found_downhill = false; - for (auto downhill_pip : ctx->getPipsDownhill(ctx->getPipSrcWire(uphill_pip))) { - if (uphill_pip == downhill_pip) { - ASSERT_FALSE(found_downhill); - found_downhill = true; - } - } - ASSERT_TRUE(found_downhill); - } - } -} - -TEST_F(LP384Test, downhill_to_uphill) -{ - for (auto dst : ctx->getWires()) { - for (auto downhill_pip : ctx->getPipsDownhill(dst)) { - bool found_uphill = false; - for (auto uphill_pip : ctx->getPipsUphill(ctx->getPipDstWire(downhill_pip))) { - if (uphill_pip == downhill_pip) { - ASSERT_FALSE(found_uphill); - found_uphill = true; - } - } - ASSERT_TRUE(found_uphill); - } - } -} diff --git a/tests/ice40/lp8k.cc b/tests/ice40/lp8k.cc deleted file mode 100644 index 7fe6ac37..00000000 --- a/tests/ice40/lp8k.cc +++ /dev/null @@ -1,106 +0,0 @@ -/* - * nextpnr -- Next Generation Place and Route - * - * Copyright (C) 2018 Clifford Wolf <clifford@symbioticeda.com> - * Copyright (C) 2018 Miodrag Milanovic <miodrag@symbioticeda.com> - * - * Permission to use, copy, modify, and/or distribute this software for any - * purpose with or without fee is hereby granted, provided that the above - * copyright notice and this permission notice appear in all copies. - * - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF - * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - * - */ - -#include <vector> -#include "gtest/gtest.h" -#include "nextpnr.h" - -USING_NEXTPNR_NAMESPACE - -class LP8KTest : public ::testing::Test -{ - protected: - virtual void SetUp() - { - chipArgs.type = ArchArgs::LP8K; - chipArgs.package = "ct256"; - ctx = new Context(chipArgs); - } - - virtual void TearDown() { delete ctx; } - - ArchArgs chipArgs; - Context *ctx; -}; - -TEST_F(LP8KTest, bel_names) -{ - int bel_count = 0; - for (auto bel : ctx->getBels()) { - auto name = ctx->getBelName(bel); - ASSERT_EQ(bel, ctx->getBelByName(name)); - bel_count++; - } - ASSERT_EQ(bel_count, 7979); -} - -TEST_F(LP8KTest, wire_names) -{ - int wire_count = 0; - for (auto wire : ctx->getWires()) { - auto name = ctx->getWireName(wire); - assert(wire == ctx->getWireByName(name)); - wire_count++; - } - ASSERT_EQ(wire_count, 165894); -} - -TEST_F(LP8KTest, pip_names) -{ - int pip_count = 0; - for (auto pip : ctx->getPips()) { - auto name = ctx->getPipName(pip); - assert(pip == ctx->getPipByName(name)); - pip_count++; - } - ASSERT_EQ(pip_count, 1806080); -} - -TEST_F(LP8KTest, uphill_to_downhill) -{ - for (auto dst : ctx->getWires()) { - for (auto uphill_pip : ctx->getPipsUphill(dst)) { - bool found_downhill = false; - for (auto downhill_pip : ctx->getPipsDownhill(ctx->getPipSrcWire(uphill_pip))) { - if (uphill_pip == downhill_pip) { - ASSERT_FALSE(found_downhill); - found_downhill = true; - } - } - ASSERT_TRUE(found_downhill); - } - } -} - -TEST_F(LP8KTest, downhill_to_uphill) -{ - for (auto dst : ctx->getWires()) { - for (auto downhill_pip : ctx->getPipsDownhill(dst)) { - bool found_uphill = false; - for (auto uphill_pip : ctx->getPipsUphill(ctx->getPipDstWire(downhill_pip))) { - if (uphill_pip == downhill_pip) { - ASSERT_FALSE(found_uphill); - found_uphill = true; - } - } - ASSERT_TRUE(found_uphill); - } - } -} diff --git a/tests/ice40/up5k.cc b/tests/ice40/up5k.cc deleted file mode 100644 index 582876e8..00000000 --- a/tests/ice40/up5k.cc +++ /dev/null @@ -1,106 +0,0 @@ -/* - * nextpnr -- Next Generation Place and Route - * - * Copyright (C) 2018 Clifford Wolf <clifford@symbioticeda.com> - * Copyright (C) 2018 Miodrag Milanovic <miodrag@symbioticeda.com> - * - * Permission to use, copy, modify, and/or distribute this software for any - * purpose with or without fee is hereby granted, provided that the above - * copyright notice and this permission notice appear in all copies. - * - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF - * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - * - */ - -#include <vector> -#include "gtest/gtest.h" -#include "nextpnr.h" - -USING_NEXTPNR_NAMESPACE - -class UP5KTest : public ::testing::Test -{ - protected: - virtual void SetUp() - { - chipArgs.type = ArchArgs::UP5K; - chipArgs.package = "sg48"; - ctx = new Context(chipArgs); - } - - virtual void TearDown() { delete ctx; } - - ArchArgs chipArgs; - Context *ctx; -}; - -TEST_F(UP5KTest, bel_names) -{ - int bel_count = 0; - for (auto bel : ctx->getBels()) { - auto name = ctx->getBelName(bel); - ASSERT_EQ(bel, ctx->getBelByName(name)); - bel_count++; - } - ASSERT_EQ(bel_count, 5438); -} - -TEST_F(UP5KTest, wire_names) -{ - int wire_count = 0; - for (auto wire : ctx->getWires()) { - auto name = ctx->getWireName(wire); - assert(wire == ctx->getWireByName(name)); - wire_count++; - } - ASSERT_EQ(wire_count, 124503); -} - -TEST_F(UP5KTest, pip_names) -{ - int pip_count = 0; - for (auto pip : ctx->getPips()) { - auto name = ctx->getPipName(pip); - assert(pip == ctx->getPipByName(name)); - pip_count++; - } - ASSERT_EQ(pip_count, 1324704); -} - -TEST_F(UP5KTest, uphill_to_downhill) -{ - for (auto dst : ctx->getWires()) { - for (auto uphill_pip : ctx->getPipsUphill(dst)) { - bool found_downhill = false; - for (auto downhill_pip : ctx->getPipsDownhill(ctx->getPipSrcWire(uphill_pip))) { - if (uphill_pip == downhill_pip) { - ASSERT_FALSE(found_downhill); - found_downhill = true; - } - } - ASSERT_TRUE(found_downhill); - } - } -} - -TEST_F(UP5KTest, downhill_to_uphill) -{ - for (auto dst : ctx->getWires()) { - for (auto downhill_pip : ctx->getPipsDownhill(dst)) { - bool found_uphill = false; - for (auto uphill_pip : ctx->getPipsUphill(ctx->getPipDstWire(downhill_pip))) { - if (uphill_pip == downhill_pip) { - ASSERT_FALSE(found_uphill); - found_uphill = true; - } - } - ASSERT_TRUE(found_uphill); - } - } -} |
