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-rw-r--r--README.md4
-rw-r--r--common/router1.cc203
-rw-r--r--common/router1.h9
-rw-r--r--ecp5/arch.cc17
-rw-r--r--ecp5/arch.h45
-rw-r--r--ecp5/bitstream.cc98
-rw-r--r--ecp5/bitstream.h3
-rw-r--r--ecp5/config.cc304
-rw-r--r--ecp5/config.h116
-rw-r--r--ecp5/family.cmake8
-rw-r--r--ecp5/main.cc13
-rw-r--r--ecp5/resource/chipdb.rc5
-rw-r--r--ecp5/resource/embed.cc28
-rw-r--r--ecp5/resource/resource.h4
-rw-r--r--ecp5/synth/.gitignore2
-rwxr-xr-xecp5/trellis_import.py21
-rw-r--r--generic/arch.cc2
-rw-r--r--gui/basewindow.cc5
-rw-r--r--gui/treemodel.h2
-rw-r--r--ice40/arch.cc45
-rw-r--r--ice40/arch.h15
-rw-r--r--ice40/chipdb.py73
-rw-r--r--ice40/main.cc9
23 files changed, 877 insertions, 154 deletions
diff --git a/README.md b/README.md
index f9658677..e9f197cd 100644
--- a/README.md
+++ b/README.md
@@ -90,9 +90,9 @@ sudo make install
```
- For an ECP5 blinky on the 45k ULX3S board, first synthesise using `yosys blinky.ys` in `ecp5/synth`.
- - Then run ECP5 place-and route using `./nextpnr-ecp5 --json ecp5/synth/blinky.json --basecfg ecp5/synth/ulx3s_empty.config --bit ecp5/synth/ulx3s.bit`
+ - Then run ECP5 place-and route using `./nextpnr-ecp5 --json ecp5/synth/blinky.json --basecfg ecp5/synth/ulx3s_empty.config --textcfg ecp5/synth/ulx3s_out.config`
+ - Create a bitstream using `ecppack ulx3s_out.config ulx3s.bit`
- Note that `ulx3s_empty.config` contains fixed/unknown bits to be copied to the output bitstream
- - You can also use `--textcfg out.config` to write a text file describing the bitstream for debugging
- More examples of the ECP5 flow for a range of boards can be found in the [Project Trellis Examples](https://github.com/SymbiFlow/prjtrellis/tree/master/examples).
diff --git a/common/router1.cc b/common/router1.cc
index 46be444e..6e352866 100644
--- a/common/router1.cc
+++ b/common/router1.cc
@@ -105,6 +105,7 @@ void ripup_net(Context *ctx, IdString net_name)
struct Router
{
Context *ctx;
+ const Router1Cfg &cfg;
RipupScoreboard scores;
IdString net_name;
@@ -128,7 +129,7 @@ struct Router
QueuedWire qw;
qw.wire = it.first;
qw.pip = PipId();
- qw.delay = it.second;
+ qw.delay = it.second - (it.second / 16);
qw.togo = ctx->estimateDelay(qw.wire, dst_wire);
qw.randtag = ctx->rng();
@@ -200,8 +201,7 @@ struct Router
continue;
#if 0 // FIXME
if (ctx->debug)
- log("Found better route to %s. Old vs new delay "
- "estimate: %.3f %.3f\n",
+ log("Found better route to %s. Old vs new delay estimate: %.3f %.3f\n",
ctx->getWireName(next_wire).c_str(),
ctx->getDelayNS(visited.at(next_wire).delay),
ctx->getDelayNS(next_delay));
@@ -227,9 +227,9 @@ struct Router
visitCnt += thisVisitCnt;
}
- Router(Context *ctx, RipupScoreboard &scores, WireId src_wire, WireId dst_wire, bool ripup = false,
- delay_t ripup_penalty = 0)
- : ctx(ctx), scores(scores), ripup(ripup), ripup_penalty(ripup_penalty)
+ Router(Context *ctx, const Router1Cfg &cfg, RipupScoreboard &scores, WireId src_wire, WireId dst_wire,
+ bool ripup = false, delay_t ripup_penalty = 0)
+ : ctx(ctx), cfg(cfg), scores(scores), ripup(ripup), ripup_penalty(ripup_penalty)
{
std::unordered_map<WireId, delay_t> src_wires;
src_wires[src_wire] = ctx->getWireDelay(src_wire).maxDelay();
@@ -252,9 +252,9 @@ struct Router
}
}
- Router(Context *ctx, RipupScoreboard &scores, IdString net_name, int user_idx = -1, bool reroute = false,
- bool ripup = false, delay_t ripup_penalty = 0)
- : ctx(ctx), scores(scores), net_name(net_name), ripup(ripup), ripup_penalty(ripup_penalty)
+ Router(Context *ctx, const Router1Cfg &cfg, RipupScoreboard &scores, IdString net_name, int user_idx = -1,
+ bool reroute = false, bool ripup = false, delay_t ripup_penalty = 0)
+ : ctx(ctx), cfg(cfg), scores(scores), net_name(net_name), ripup(ripup), ripup_penalty(ripup_penalty)
{
auto net_info = ctx->nets.at(net_name).get();
@@ -274,16 +274,19 @@ struct Router
log(" Source wire: %s\n", ctx->getWireName(src_wire).c_str(ctx));
std::unordered_map<WireId, delay_t> src_wires;
- std::vector<int> users_array;
+ std::vector<std::pair<delay_t, int>> users_array;
if (user_idx < 0) {
- // route all users
- for (int user_idx = 0; user_idx < int(net_info->users.size()); user_idx++)
- users_array.push_back(user_idx);
- ctx->shuffle(users_array);
+ // route all users, from worst to best slack
+ for (int user_idx = 0; user_idx < int(net_info->users.size()); user_idx++) {
+ auto dst_wire = ctx->getNetinfoSinkWire(net_info, net_info->users[user_idx]);
+ delay_t slack = net_info->users[user_idx].budget - ctx->estimateDelay(src_wire, dst_wire);
+ users_array.push_back(std::pair<delay_t, int>(slack, user_idx));
+ }
+ std::sort(users_array.begin(), users_array.end());
} else {
// route only the selected user
- users_array.push_back(user_idx);
+ users_array.push_back(std::pair<delay_t, int>(delay_t(), user_idx));
}
if (reroute) {
@@ -315,7 +318,6 @@ struct Router
delay_t delay = register_existing_path(ctx->getPipSrcWire(pip));
delay += ctx->getPipDelay(pip).maxDelay();
delay += ctx->getWireDelay(wire).maxDelay();
- delay -= 2 * ctx->getDelayEpsilon();
src_wires[wire] = delay;
return delay;
@@ -347,7 +349,9 @@ struct Router
}
}
- for (int user_idx : users_array) {
+ for (auto user_idx_it : users_array) {
+ int user_idx = user_idx_it.second;
+
if (ctx->debug)
log(" Route to: %s.%s.\n", net_info->users[user_idx].cell->name.c_str(ctx),
net_info->users[user_idx].port.c_str(ctx));
@@ -452,7 +456,8 @@ struct RouteJob
};
};
-void addFullNetRouteJob(Context *ctx, IdString net_name, std::unordered_map<IdString, std::vector<bool>> &cache,
+void addFullNetRouteJob(Context *ctx, const Router1Cfg &cfg, IdString net_name,
+ std::unordered_map<IdString, std::vector<bool>> &cache,
std::priority_queue<RouteJob, std::vector<RouteJob>, RouteJob::Greater> &queue)
{
NetInfo *net_info = ctx->nets.at(net_name).get();
@@ -517,7 +522,8 @@ void addFullNetRouteJob(Context *ctx, IdString net_name, std::unordered_map<IdSt
net_cache[user_idx] = true;
}
-void addNetRouteJobs(Context *ctx, IdString net_name, std::unordered_map<IdString, std::vector<bool>> &cache,
+void addNetRouteJobs(Context *ctx, const Router1Cfg &cfg, IdString net_name,
+ std::unordered_map<IdString, std::vector<bool>> &cache,
std::priority_queue<RouteJob, std::vector<RouteJob>, RouteJob::Greater> &queue)
{
NetInfo *net_info = ctx->nets.at(net_name).get();
@@ -565,11 +571,114 @@ void addNetRouteJobs(Context *ctx, IdString net_name, std::unordered_map<IdStrin
}
}
+void cleanupReroute(Context *ctx, const Router1Cfg &cfg, RipupScoreboard &scores,
+ std::unordered_set<IdString> &cleanupQueue,
+ std::priority_queue<RouteJob, std::vector<RouteJob>, RouteJob::Greater> &jobQueue,
+ int &totalVisitCnt, int &totalRevisitCnt, int &totalOvertimeRevisitCnt)
+{
+ std::priority_queue<RouteJob, std::vector<RouteJob>, RouteJob::Greater> cleanupJobs;
+ std::vector<NetInfo *> allNetinfos;
+
+ for (auto net_name : cleanupQueue) {
+ NetInfo *net_info = ctx->nets.at(net_name).get();
+ auto src_wire = ctx->getNetinfoSourceWire(net_info);
+
+ if (ctx->verbose)
+ allNetinfos.push_back(net_info);
+
+ std::unordered_map<WireId, int> useCounters;
+ std::vector<int> candidateArcs;
+
+ for (int user_idx = 0; user_idx < int(net_info->users.size()); user_idx++) {
+ auto dst_wire = ctx->getNetinfoSinkWire(net_info, net_info->users[user_idx]);
+
+ if (dst_wire == src_wire)
+ continue;
+
+ auto cursor = dst_wire;
+ useCounters[cursor]++;
+
+ while (cursor != src_wire) {
+ auto it = net_info->wires.find(cursor);
+ if (it == net_info->wires.end())
+ break;
+ cursor = ctx->getPipSrcWire(it->second.pip);
+ useCounters[cursor]++;
+ }
+
+ if (cursor != src_wire)
+ continue;
+
+ candidateArcs.push_back(user_idx);
+ }
+
+ for (int user_idx : candidateArcs) {
+ auto dst_wire = ctx->getNetinfoSinkWire(net_info, net_info->users[user_idx]);
+
+ if (useCounters.at(dst_wire) != 1)
+ continue;
+
+ RouteJob job;
+ job.net = net_name;
+ job.user_idx = user_idx;
+ job.slack = net_info->users[user_idx].budget - ctx->estimateDelay(src_wire, dst_wire);
+ job.randtag = ctx->rng();
+ cleanupJobs.push(job);
+ }
+ }
+
+ log_info("running cleanup re-route of %d nets (%d arcs).\n", int(cleanupQueue.size()), int(cleanupJobs.size()));
+
+ cleanupQueue.clear();
+
+ int visitCnt = 0, revisitCnt = 0, overtimeRevisitCnt = 0;
+ int totalWireCountDelta = 0;
+
+ if (ctx->verbose) {
+ for (auto it : allNetinfos)
+ totalWireCountDelta -= it->wires.size();
+ }
+
+ while (!cleanupJobs.empty()) {
+ RouteJob job = cleanupJobs.top();
+ cleanupJobs.pop();
+
+ auto net_name = job.net;
+ auto user_idx = job.user_idx;
+
+ NetInfo *net_info = ctx->nets.at(net_name).get();
+ auto dst_wire = ctx->getNetinfoSinkWire(net_info, net_info->users[user_idx]);
+
+ ctx->unbindWire(dst_wire);
+
+ Router router(ctx, cfg, scores, net_name, user_idx, false, false);
+
+ if (!router.routedOkay)
+ log_error("Failed to re-route arc %d of net %s.\n", user_idx, net_name.c_str(ctx));
+
+ visitCnt += router.visitCnt;
+ revisitCnt += router.revisitCnt;
+ overtimeRevisitCnt += router.overtimeRevisitCnt;
+ }
+
+ if (ctx->verbose) {
+ for (auto it : allNetinfos)
+ totalWireCountDelta += it->wires.size();
+
+ log_info(" visited %d PIPs (%.2f%% revisits, %.2f%% overtime), %+d wires.\n", visitCnt,
+ (100.0 * revisitCnt) / visitCnt, (100.0 * overtimeRevisitCnt) / visitCnt, totalWireCountDelta);
+ }
+
+ totalVisitCnt += visitCnt;
+ totalRevisitCnt += revisitCnt;
+ totalOvertimeRevisitCnt += overtimeRevisitCnt;
+}
+
} // namespace
NEXTPNR_NAMESPACE_BEGIN
-bool router1(Context *ctx)
+bool router1(Context *ctx, const Router1Cfg &cfg)
{
try {
int totalVisitCnt = 0, totalRevisitCnt = 0, totalOvertimeRevisitCnt = 0;
@@ -580,11 +689,12 @@ bool router1(Context *ctx)
log_info("Routing..\n");
ctx->lock();
+ std::unordered_set<IdString> cleanupQueue;
std::unordered_map<IdString, std::vector<bool>> jobCache;
std::priority_queue<RouteJob, std::vector<RouteJob>, RouteJob::Greater> jobQueue;
for (auto &net_it : ctx->nets)
- addNetRouteJobs(ctx, net_it.first, jobCache, jobQueue);
+ addNetRouteJobs(ctx, cfg, net_it.first, jobCache, jobQueue);
if (jobQueue.empty()) {
log_info("found no unrouted source-sink pairs. no routing necessary.\n");
@@ -597,7 +707,7 @@ bool router1(Context *ctx)
int iterCnt = 0;
while (!jobQueue.empty()) {
- if (iterCnt == 200) {
+ if (iterCnt == cfg.maxIterCnt) {
log_warning("giving up after %d iterations.\n", iterCnt);
log_info("Checksum: 0x%08x\n", ctx->checksum());
#ifndef NDEBUG
@@ -630,6 +740,9 @@ bool router1(Context *ctx)
auto user_idx = jobQueue.top().user_idx;
jobQueue.pop();
+ if (cfg.fullCleanupReroute)
+ cleanupQueue.insert(net_name);
+
if (printNets) {
if (user_idx < 0)
log_info(" routing all %d users of net %s\n", int(ctx->nets.at(net_name)->users.size()),
@@ -638,7 +751,7 @@ bool router1(Context *ctx)
log_info(" routing user %d of net %s\n", user_idx, net_name.c_str(ctx));
}
- Router router(ctx, scores, net_name, user_idx, false, false);
+ Router router(ctx, cfg, scores, net_name, user_idx, false, false);
jobCnt++;
visitCnt += router.visitCnt;
@@ -669,15 +782,12 @@ bool router1(Context *ctx)
}
if (ctx->verbose)
- log_info(" visited %d PIPs (%.2f%% revisits, %.2f%% overtime "
- "revisits).\n",
- visitCnt, (100.0 * revisitCnt) / visitCnt, (100.0 * overtimeRevisitCnt) / visitCnt);
+ log_info(" visited %d PIPs (%.2f%% revisits, %.2f%% overtime revisits).\n", visitCnt,
+ (100.0 * revisitCnt) / visitCnt, (100.0 * overtimeRevisitCnt) / visitCnt);
if (!ripupQueue.empty()) {
if (ctx->verbose || iterCnt == 1)
- log_info("failed to route %d nets. re-routing in ripup "
- "mode.\n",
- int(ripupQueue.size()));
+ log_info("failed to route %d nets. re-routing in ripup mode.\n", int(ripupQueue.size()));
printNets = ctx->verbose && (ripupQueue.size() < 10);
@@ -691,11 +801,14 @@ bool router1(Context *ctx)
ctx->sorted_shuffle(ripupArray);
for (auto net_name : ripupArray) {
+ if (cfg.cleanupReroute)
+ cleanupQueue.insert(net_name);
+
if (printNets)
log_info(" routing net %s. (%d users)\n", net_name.c_str(ctx),
int(ctx->nets.at(net_name)->users.size()));
- Router router(ctx, scores, net_name, -1, false, true, ripup_penalty);
+ Router router(ctx, cfg, scores, net_name, -1, false, true, ripup_penalty);
netCnt++;
visitCnt += router.visitCnt;
@@ -705,8 +818,11 @@ bool router1(Context *ctx)
if (!router.routedOkay)
log_error("Net %s is impossible to route.\n", net_name.c_str(ctx));
- for (auto it : router.rippedNets)
- addFullNetRouteJob(ctx, it, jobCache, jobQueue);
+ for (auto it : router.rippedNets) {
+ addFullNetRouteJob(ctx, cfg, it, jobCache, jobQueue);
+ if (cfg.cleanupReroute)
+ cleanupQueue.insert(it);
+ }
if (printNets) {
if (router.rippedNets.size() < 10) {
@@ -730,14 +846,11 @@ bool router1(Context *ctx)
log_info(" routed %d nets, ripped %d nets.\n", netCnt, ripCnt);
if (ctx->verbose)
- log_info(" visited %d PIPs (%.2f%% revisits, %.2f%% "
- "overtime revisits).\n",
- visitCnt, (100.0 * revisitCnt) / visitCnt, (100.0 * overtimeRevisitCnt) / visitCnt);
+ log_info(" visited %d PIPs (%.2f%% revisits, %.2f%% overtime revisits).\n", visitCnt,
+ (100.0 * revisitCnt) / visitCnt, (100.0 * overtimeRevisitCnt) / visitCnt);
if (ctx->verbose && !jobQueue.empty())
- log_info(" ripped up %d previously routed nets. continue "
- "routing.\n",
- int(jobQueue.size()));
+ log_info(" ripped up %d previously routed nets. continue routing.\n", int(jobQueue.size()));
}
if (!ctx->verbose)
@@ -751,15 +864,17 @@ bool router1(Context *ctx)
if (iterCnt == 8 || iterCnt == 16 || iterCnt == 32 || iterCnt == 64 || iterCnt == 128)
ripup_penalty += ctx->getRipupDelayPenalty();
+ if (jobQueue.empty() || (iterCnt % 5) == 0 || (cfg.fullCleanupReroute && iterCnt == 1))
+ cleanupReroute(ctx, cfg, scores, cleanupQueue, jobQueue, totalVisitCnt, totalRevisitCnt,
+ totalOvertimeRevisitCnt);
+
ctx->yield();
}
log_info("routing complete after %d iterations.\n", iterCnt);
- log_info("visited %d PIPs (%.2f%% revisits, %.2f%% "
- "overtime revisits).\n",
- totalVisitCnt, (100.0 * totalRevisitCnt) / totalVisitCnt,
- (100.0 * totalOvertimeRevisitCnt) / totalVisitCnt);
+ log_info("visited %d PIPs (%.2f%% revisits, %.2f%% overtime revisits).\n", totalVisitCnt,
+ (100.0 * totalRevisitCnt) / totalVisitCnt, (100.0 * totalOvertimeRevisitCnt) / totalVisitCnt);
{
float tns = 0;
@@ -798,7 +913,7 @@ bool router1(Context *ctx)
jobCache.clear();
for (auto &net_it : ctx->nets)
- addNetRouteJobs(ctx, net_it.first, jobCache, jobQueue);
+ addNetRouteJobs(ctx, cfg, net_it.first, jobCache, jobQueue);
#ifndef NDEBUG
if (!jobQueue.empty()) {
@@ -833,7 +948,7 @@ bool router1(Context *ctx)
bool Context::getActualRouteDelay(WireId src_wire, WireId dst_wire, delay_t &delay)
{
RipupScoreboard scores;
- Router router(this, scores, src_wire, dst_wire);
+ Router router(this, Router1Cfg(), scores, src_wire, dst_wire);
if (router.routedOkay)
delay = router.visited.at(dst_wire).delay;
return router.routedOkay;
diff --git a/common/router1.h b/common/router1.h
index 38552c58..a9e84b6b 100644
--- a/common/router1.h
+++ b/common/router1.h
@@ -24,7 +24,14 @@
NEXTPNR_NAMESPACE_BEGIN
-extern bool router1(Context *ctx);
+struct Router1Cfg
+{
+ int maxIterCnt = 200;
+ bool cleanupReroute = true;
+ bool fullCleanupReroute = true;
+};
+
+extern bool router1(Context *ctx, const Router1Cfg &cfg);
NEXTPNR_NAMESPACE_END
diff --git a/ecp5/arch.cc b/ecp5/arch.cc
index 6c3714cc..262f43fe 100644
--- a/ecp5/arch.cc
+++ b/ecp5/arch.cc
@@ -428,7 +428,11 @@ delay_t Arch::getBudgetOverride(const NetInfo *net_info, const PortRef &sink, de
bool Arch::place() { return placer1(getCtx()); }
-bool Arch::route() { return router1(getCtx()); }
+bool Arch::route()
+{
+ Router1Cfg cfg;
+ return router1(getCtx(), cfg);
+}
// -----------------------------------------------------------------------
@@ -496,4 +500,15 @@ IdString Arch::getPortClock(const CellInfo *cell, IdString port) const { return
bool Arch::isClockPort(const CellInfo *cell, IdString port) const { return false; }
+std::vector<std::pair<std::string, std::string>> Arch::getTilesAtLocation(int row, int col)
+{
+ std::vector<std::pair<std::string, std::string>> ret;
+ auto &tileloc = chip_info->tile_info[row * chip_info->width + col];
+ for (int i = 0; i < tileloc.num_tiles; i++) {
+ ret.push_back(std::make_pair(tileloc.tile_names[i].name.get(),
+ chip_info->tiletype_names[tileloc.tile_names[i].type_idx].get()));
+ }
+ return ret;
+}
+
NEXTPNR_NAMESPACE_END
diff --git a/ecp5/arch.h b/ecp5/arch.h
index 2e54276b..d450321d 100644
--- a/ecp5/arch.h
+++ b/ecp5/arch.h
@@ -22,6 +22,7 @@
#error Include "arch.h" via "nextpnr.h" only.
#endif
+#include <set>
#include <sstream>
NEXTPNR_NAMESPACE_BEGIN
@@ -117,6 +118,17 @@ NPNR_PACKED_STRUCT(struct PackageInfoPOD {
RelPtr<PackagePinPOD> pin_data;
});
+NPNR_PACKED_STRUCT(struct TileNamePOD {
+ RelPtr<char> name;
+ int16_t type_idx;
+ int16_t padding;
+});
+
+NPNR_PACKED_STRUCT(struct TileInfoPOD {
+ int32_t num_tiles;
+ RelPtr<TileNamePOD> tile_names;
+});
+
enum TapDirection : int8_t
{
TAP_DIR_LEFT = 0,
@@ -148,6 +160,7 @@ NPNR_PACKED_STRUCT(struct ChipInfoPOD {
RelPtr<RelPtr<char>> tiletype_names;
RelPtr<PackageInfoPOD> package_info;
RelPtr<PIOInfoPOD> pio_info;
+ RelPtr<TileInfoPOD> tile_info;
});
#if defined(_MSC_VER)
@@ -747,6 +760,16 @@ struct Arch : BaseCtx
return range;
}
+ std::string getPipTilename(PipId pip) const
+ {
+ auto &tileloc = chip_info->tile_info[pip.location.y * chip_info->width + pip.location.x];
+ for (int i = 0; i < tileloc.num_tiles; i++) {
+ if (tileloc.tile_names[i].type_idx == locInfo(pip)->pip_data[pip.index].tile_type)
+ return tileloc.tile_names[i].name.get();
+ }
+ NPNR_ASSERT_FALSE("failed to find Pip tile");
+ }
+
std::string getPipTiletype(PipId pip) const
{
return chip_info->tiletype_names[locInfo(pip)->pip_data[pip.index].tile_type].get();
@@ -818,6 +841,28 @@ struct Arch : BaseCtx
// Helper function for above
bool slicesCompatible(const std::vector<const CellInfo *> &cells) const;
+ std::vector<std::pair<std::string, std::string>> getTilesAtLocation(int row, int col);
+ std::string getTileByTypeAndLocation(int row, int col, std::string type) const
+ {
+ auto &tileloc = chip_info->tile_info[row * chip_info->width + col];
+ for (int i = 0; i < tileloc.num_tiles; i++) {
+ if (chip_info->tiletype_names[tileloc.tile_names[i].type_idx].get() == type)
+ return tileloc.tile_names[i].name.get();
+ }
+ NPNR_ASSERT_FALSE_STR("no tile at (" + std::to_string(col) + ", " + std::to_string(row) + ") with type " +
+ type);
+ }
+
+ std::string getTileByTypeAndLocation(int row, int col, const std::set<std::string> &type) const
+ {
+ auto &tileloc = chip_info->tile_info[row * chip_info->width + col];
+ for (int i = 0; i < tileloc.num_tiles; i++) {
+ if (type.count(chip_info->tiletype_names[tileloc.tile_names[i].type_idx].get()))
+ return tileloc.tile_names[i].name.get();
+ }
+ NPNR_ASSERT_FALSE_STR("no tile at (" + std::to_string(col) + ", " + std::to_string(row) + ") with type in set");
+ }
+
IdString id_trellis_slice;
IdString id_clk, id_lsr;
IdString id_clkmux, id_lsrmux;
diff --git a/ecp5/bitstream.cc b/ecp5/bitstream.cc
index bf580f44..f12e09b2 100644
--- a/ecp5/bitstream.cc
+++ b/ecp5/bitstream.cc
@@ -19,17 +19,10 @@
#include "bitstream.h"
-// From Project Trellis
-#include "BitDatabase.hpp"
-#include "Bitstream.hpp"
-#include "Chip.hpp"
-#include "ChipConfig.hpp"
-#include "Tile.hpp"
-#include "TileConfig.hpp"
-
#include <fstream>
#include <streambuf>
+#include "config.h"
#include "io.h"
#include "log.h"
#include "util.h"
@@ -49,13 +42,13 @@ static std::string get_trellis_wirename(Context *ctx, Location loc, WireId wire)
return basename;
std::string rel_prefix;
if (wire.location.y < loc.y)
- rel_prefix += "N" + to_string(loc.y - wire.location.y);
+ rel_prefix += "N" + std::to_string(loc.y - wire.location.y);
if (wire.location.y > loc.y)
- rel_prefix += "S" + to_string(wire.location.y - loc.y);
+ rel_prefix += "S" + std::to_string(wire.location.y - loc.y);
if (wire.location.x > loc.x)
- rel_prefix += "E" + to_string(wire.location.x - loc.x);
+ rel_prefix += "E" + std::to_string(wire.location.x - loc.x);
if (wire.location.x < loc.x)
- rel_prefix += "W" + to_string(loc.x - wire.location.x);
+ rel_prefix += "W" + std::to_string(loc.x - wire.location.x);
return rel_prefix + "_" + basename;
}
@@ -69,7 +62,7 @@ static std::vector<bool> int_to_bitvector(int val, int size)
}
// Get the PIO tile corresponding to a PIO bel
-static std::string get_pio_tile(Context *ctx, Trellis::Chip &chip, BelId bel)
+static std::string get_pio_tile(Context *ctx, BelId bel)
{
static const std::set<std::string> pioabcd_l = {"PICL1", "PICL1_DQS0", "PICL1_DQS3"};
static const std::set<std::string> pioabcd_r = {"PICR1", "PICR1_DQS0", "PICR1_DQS3"};
@@ -79,31 +72,31 @@ static std::string get_pio_tile(Context *ctx, Trellis::Chip &chip, BelId bel)
std::string pio_name = ctx->locInfo(bel)->bel_data[bel.index].name.get();
if (bel.location.y == 0) {
if (pio_name == "PIOA") {
- return chip.get_tile_by_position_and_type(0, bel.location.x, "PIOT0");
+ return ctx->getTileByTypeAndLocation(0, bel.location.x, "PIOT0");
} else if (pio_name == "PIOB") {
- return chip.get_tile_by_position_and_type(0, bel.location.x + 1, "PIOT1");
+ return ctx->getTileByTypeAndLocation(0, bel.location.x + 1, "PIOT1");
} else {
NPNR_ASSERT_FALSE("bad PIO location");
}
} else if (bel.location.y == ctx->chip_info->height - 1) {
if (pio_name == "PIOA") {
- return chip.get_tile_by_position_and_type(bel.location.y, bel.location.x, pioa_b);
+ return ctx->getTileByTypeAndLocation(bel.location.y, bel.location.x, pioa_b);
} else if (pio_name == "PIOB") {
- return chip.get_tile_by_position_and_type(bel.location.y, bel.location.x + 1, piob_b);
+ return ctx->getTileByTypeAndLocation(bel.location.y, bel.location.x + 1, piob_b);
} else {
NPNR_ASSERT_FALSE("bad PIO location");
}
} else if (bel.location.x == 0) {
- return chip.get_tile_by_position_and_type(bel.location.y + 1, bel.location.x, pioabcd_l);
+ return ctx->getTileByTypeAndLocation(bel.location.y + 1, bel.location.x, pioabcd_l);
} else if (bel.location.x == ctx->chip_info->width - 1) {
- return chip.get_tile_by_position_and_type(bel.location.y + 1, bel.location.x, pioabcd_r);
+ return ctx->getTileByTypeAndLocation(bel.location.y + 1, bel.location.x, pioabcd_r);
} else {
NPNR_ASSERT_FALSE("bad PIO location");
}
}
// Get the PIC tile corresponding to a PIO bel
-static std::string get_pic_tile(Context *ctx, Trellis::Chip &chip, BelId bel)
+static std::string get_pic_tile(Context *ctx, BelId bel)
{
static const std::set<std::string> picab_l = {"PICL0", "PICL0_DQS2"};
static const std::set<std::string> piccd_l = {"PICL2", "PICL2_DQS1", "MIB_CIB_LR"};
@@ -116,33 +109,33 @@ static std::string get_pic_tile(Context *ctx, Trellis::Chip &chip, BelId bel)
std::string pio_name = ctx->locInfo(bel)->bel_data[bel.index].name.get();
if (bel.location.y == 0) {
if (pio_name == "PIOA") {
- return chip.get_tile_by_position_and_type(1, bel.location.x, "PICT0");
+ return ctx->getTileByTypeAndLocation(1, bel.location.x, "PICT0");
} else if (pio_name == "PIOB") {
- return chip.get_tile_by_position_and_type(1, bel.location.x + 1, "PICT1");
+ return ctx->getTileByTypeAndLocation(1, bel.location.x + 1, "PICT1");
} else {
NPNR_ASSERT_FALSE("bad PIO location");
}
} else if (bel.location.y == ctx->chip_info->height - 1) {
if (pio_name == "PIOA") {
- return chip.get_tile_by_position_and_type(bel.location.y, bel.location.x, pica_b);
+ return ctx->getTileByTypeAndLocation(bel.location.y, bel.location.x, pica_b);
} else if (pio_name == "PIOB") {
- return chip.get_tile_by_position_and_type(bel.location.y, bel.location.x + 1, picb_b);
+ return ctx->getTileByTypeAndLocation(bel.location.y, bel.location.x + 1, picb_b);
} else {
NPNR_ASSERT_FALSE("bad PIO location");
}
} else if (bel.location.x == 0) {
if (pio_name == "PIOA" || pio_name == "PIOB") {
- return chip.get_tile_by_position_and_type(bel.location.y, bel.location.x, picab_l);
+ return ctx->getTileByTypeAndLocation(bel.location.y, bel.location.x, picab_l);
} else if (pio_name == "PIOC" || pio_name == "PIOD") {
- return chip.get_tile_by_position_and_type(bel.location.y + 2, bel.location.x, piccd_l);
+ return ctx->getTileByTypeAndLocation(bel.location.y + 2, bel.location.x, piccd_l);
} else {
NPNR_ASSERT_FALSE("bad PIO location");
}
} else if (bel.location.x == ctx->chip_info->width - 1) {
if (pio_name == "PIOA" || pio_name == "PIOB") {
- return chip.get_tile_by_position_and_type(bel.location.y, bel.location.x, picab_r);
+ return ctx->getTileByTypeAndLocation(bel.location.y, bel.location.x, picab_r);
} else if (pio_name == "PIOC" || pio_name == "PIOD") {
- return chip.get_tile_by_position_and_type(bel.location.y + 2, bel.location.x, piccd_r);
+ return ctx->getTileByTypeAndLocation(bel.location.y + 2, bel.location.x, piccd_r);
} else {
NPNR_ASSERT_FALSE("bad PIO location");
}
@@ -151,11 +144,9 @@ static std::string get_pic_tile(Context *ctx, Trellis::Chip &chip, BelId bel)
}
}
-void write_bitstream(Context *ctx, std::string base_config_file, std::string text_config_file,
- std::string bitstream_file)
+void write_bitstream(Context *ctx, std::string base_config_file, std::string text_config_file)
{
- Trellis::Chip empty_chip(ctx->getChipName());
- Trellis::ChipConfig cc;
+ ChipConfig cc;
std::set<std::string> cib_tiles = {"CIB", "CIB_LR", "CIB_LR_S", "CIB_EFB0", "CIB_EFB1"};
@@ -164,8 +155,7 @@ void write_bitstream(Context *ctx, std::string base_config_file, std::string tex
if (!config_file) {
log_error("failed to open base config file '%s'\n", base_config_file.c_str());
}
- std::string str((std::istreambuf_iterator<char>(config_file)), std::istreambuf_iterator<char>());
- cc = Trellis::ChipConfig::from_string(str);
+ config_file >> cc;
} else {
cc.chip_name = ctx->getChipName();
// TODO: .bit metadata
@@ -175,8 +165,7 @@ void write_bitstream(Context *ctx, std::string base_config_file, std::string tex
for (auto pip : ctx->getPips()) {
if (ctx->getBoundPipNet(pip) != IdString()) {
if (ctx->getPipClass(pip) == 0) { // ignore fixed pips
- std::string tile = empty_chip.get_tile_by_position_and_type(pip.location.y, pip.location.x,
- ctx->getPipTiletype(pip));
+ std::string tile = ctx->getPipTilename(pip);
std::string source = get_trellis_wirename(ctx, pip.location, ctx->getPipSrcWire(pip));
std::string sink = get_trellis_wirename(ctx, pip.location, ctx->getPipDstWire(pip));
cc.tiles[tile].add_arc(sink, source);
@@ -214,15 +203,20 @@ void write_bitstream(Context *ctx, std::string base_config_file, std::string tex
}
// Set all bankref tiles to appropriate VccIO
- for (const auto &tile : empty_chip.tiles) {
- std::string type = tile.second->info.type;
- if (type.find("BANKREF") != std::string::npos && type != "BANKREF8") {
- int bank = std::stoi(type.substr(7));
- if (bankVcc.find(bank) != bankVcc.end())
- cc.tiles[tile.first].add_enum("BANK.VCCIO", iovoltage_to_str(bankVcc[bank]));
- if (bankLvds[bank]) {
- cc.tiles[tile.first].add_enum("BANK.DIFF_REF", "ON");
- cc.tiles[tile.first].add_enum("BANK.LVDSO", "ON");
+ for (int y = 0; y < ctx->getGridDimY(); y++) {
+ for (int x = 0; x < ctx->getGridDimX(); x++) {
+ auto tiles = ctx->getTilesAtLocation(y, x);
+ for (auto tile : tiles) {
+ std::string type = tile.second;
+ if (type.find("BANKREF") != std::string::npos && type != "BANKREF8") {
+ int bank = std::stoi(type.substr(7));
+ if (bankVcc.find(bank) != bankVcc.end())
+ cc.tiles[tile.first].add_enum("BANK.VCCIO", iovoltage_to_str(bankVcc[bank]));
+ if (bankLvds[bank]) {
+ cc.tiles[tile.first].add_enum("BANK.DIFF_REF", "ON");
+ cc.tiles[tile.first].add_enum("BANK.LVDSO", "ON");
+ }
+ }
}
}
}
@@ -235,7 +229,7 @@ void write_bitstream(Context *ctx, std::string base_config_file, std::string tex
}
BelId bel = ci->bel;
if (ci->type == ctx->id("TRELLIS_SLICE")) {
- std::string tname = empty_chip.get_tile_by_position_and_type(bel.location.y, bel.location.x, "PLC2");
+ std::string tname = ctx->getTileByTypeAndLocation(bel.location.y, bel.location.x, "PLC2");
std::string slice = ctx->locInfo(bel)->bel_data[bel.index].name.get();
int lut0_init = int_or_default(ci->params, ctx->id("LUT0_INITVAL"));
int lut1_init = int_or_default(ci->params, ctx->id("LUT1_INITVAL"));
@@ -267,8 +261,8 @@ void write_bitstream(Context *ctx, std::string base_config_file, std::string tex
std::string pio = ctx->locInfo(bel)->bel_data[bel.index].name.get();
std::string iotype = str_or_default(ci->attrs, ctx->id("IO_TYPE"), "LVCMOS33");
std::string dir = str_or_default(ci->params, ctx->id("DIR"), "INPUT");
- std::string pio_tile = get_pio_tile(ctx, empty_chip, bel);
- std::string pic_tile = get_pic_tile(ctx, empty_chip, bel);
+ std::string pio_tile = get_pio_tile(ctx, bel);
+ std::string pic_tile = get_pic_tile(ctx, bel);
cc.tiles[pio_tile].add_enum(pio + ".BASE_TYPE", dir + "_" + iotype);
cc.tiles[pic_tile].add_enum(pio + ".BASE_TYPE", dir + "_" + iotype);
if (is_differential(ioType_from_str(iotype))) {
@@ -293,7 +287,7 @@ void write_bitstream(Context *ctx, std::string base_config_file, std::string tex
PipId jpt_pip = *ctx->getPipsUphill(jpt_wire).begin();
WireId cib_wire = ctx->getPipSrcWire(jpt_pip);
std::string cib_tile =
- empty_chip.get_tile_by_position_and_type(cib_wire.location.y, cib_wire.location.x, cib_tiles);
+ ctx->getTileByTypeAndLocation(cib_wire.location.y, cib_wire.location.x, cib_tiles);
std::string cib_wirename = ctx->locInfo(cib_wire)->wire_data[cib_wire.index].name.get();
cc.tiles[cib_tile].add_enum("CIB." + cib_wirename + "MUX", "0");
}
@@ -306,13 +300,9 @@ void write_bitstream(Context *ctx, std::string base_config_file, std::string tex
}
// Configure chip
- if (!bitstream_file.empty()) {
- Trellis::Chip cfg_chip = cc.to_chip();
- Trellis::Bitstream::serialise_chip(cfg_chip).write_bit_py(bitstream_file);
- }
if (!text_config_file.empty()) {
std::ofstream out_config(text_config_file);
- out_config << cc.to_string();
+ out_config << cc;
}
}
diff --git a/ecp5/bitstream.h b/ecp5/bitstream.h
index 62617470..f70abb35 100644
--- a/ecp5/bitstream.h
+++ b/ecp5/bitstream.h
@@ -24,8 +24,7 @@
NEXTPNR_NAMESPACE_BEGIN
-void write_bitstream(Context *ctx, std::string base_config_file = "", std::string text_config_file = "",
- std::string bitstream_file = "");
+void write_bitstream(Context *ctx, std::string base_config_file = "", std::string text_config_file = "");
NEXTPNR_NAMESPACE_END
diff --git a/ecp5/config.cc b/ecp5/config.cc
new file mode 100644
index 00000000..826c16a9
--- /dev/null
+++ b/ecp5/config.cc
@@ -0,0 +1,304 @@
+/*
+ * nextpnr -- Next Generation Place and Route
+ *
+ * Copyright (C) 2018 David Shah <david@symbioticeda.com>
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include "config.h"
+#include <boost/range/adaptor/reversed.hpp>
+#include "log.h"
+NEXTPNR_NAMESPACE_BEGIN
+
+#define fmt(x) (static_cast<const std::ostringstream &>(std::ostringstream() << x).str())
+
+inline std::string to_string(const std::vector<bool> &bv)
+{
+ std::ostringstream os;
+ for (auto bit : boost::adaptors::reverse(bv))
+ os << (bit ? '1' : '0');
+ return os.str();
+}
+
+inline std::istream &operator>>(std::istream &in, std::vector<bool> &bv)
+{
+ bv.clear();
+ std::string s;
+ in >> s;
+ for (auto c : boost::adaptors::reverse(s)) {
+ assert((c == '0') || (c == '1'));
+ bv.push_back((c == '1'));
+ }
+ return in;
+}
+
+struct ConfigBit
+{
+ int frame;
+ int bit;
+ bool inv;
+};
+
+static ConfigBit cbit_from_str(const std::string &s)
+{
+ size_t idx = 0;
+ ConfigBit b;
+ if (s[idx] == '!') {
+ b.inv = true;
+ ++idx;
+ } else {
+ b.inv = false;
+ }
+ NPNR_ASSERT(s[idx] == 'F');
+ ++idx;
+ size_t b_pos = s.find('B');
+ NPNR_ASSERT(b_pos != std::string::npos);
+ b.frame = stoi(s.substr(idx, b_pos - idx));
+ b.bit = stoi(s.substr(b_pos + 1));
+ return b;
+}
+
+inline std::string to_string(ConfigBit b)
+{
+ std::ostringstream ss;
+ if (b.inv)
+ ss << "!";
+ ss << "F" << b.frame;
+ ss << "B" << b.bit;
+ return ss.str();
+}
+
+// Skip whitespace, optionally including newlines
+inline void skip_blank(std::istream &in, bool nl = false)
+{
+ int c = in.peek();
+ while (in && (((c == ' ') || (c == '\t')) || (nl && ((c == '\n') || (c == '\r'))))) {
+ in.get();
+ c = in.peek();
+ }
+}
+// Return true if end of line (or file)
+inline bool skip_check_eol(std::istream &in)
+{
+ skip_blank(in, false);
+ if (!in)
+ return false;
+ int c = in.peek();
+ // Comments count as end of line
+ if (c == '#') {
+ in.get();
+ c = in.peek();
+ while (in && c != EOF && c != '\n') {
+ in.get();
+ c = in.peek();
+ }
+ return true;
+ }
+ return (c == EOF || c == '\n');
+}
+
+// Skip past blank lines and comments
+inline void skip(std::istream &in)
+{
+ skip_blank(in, true);
+ while (in && (in.peek() == '#')) {
+ // Skip comment line
+ skip_check_eol(in);
+ skip_blank(in, true);
+ }
+}
+
+// Return true if at the end of a record (or file)
+inline bool skip_check_eor(std::istream &in)
+{
+ skip(in);
+ int c = in.peek();
+ return (c == EOF || c == '.');
+}
+
+// Return true if at the end of file
+inline bool skip_check_eof(std::istream &in)
+{
+ skip(in);
+ int c = in.peek();
+ return (c == EOF);
+}
+
+std::ostream &operator<<(std::ostream &out, const ConfigArc &arc)
+{
+ out << "arc: " << arc.sink << " " << arc.source << std::endl;
+ return out;
+}
+
+std::istream &operator>>(std::istream &in, ConfigArc &arc)
+{
+ in >> arc.sink;
+ in >> arc.source;
+ return in;
+}
+
+std::ostream &operator<<(std::ostream &out, const ConfigWord &cw)
+{
+ out << "word: " << cw.name << " " << to_string(cw.value) << std::endl;
+ return out;
+}
+
+std::istream &operator>>(std::istream &in, ConfigWord &cw)
+{
+ in >> cw.name;
+ in >> cw.value;
+ return in;
+}
+
+std::ostream &operator<<(std::ostream &out, const ConfigEnum &cw)
+{
+ out << "enum: " << cw.name << " " << cw.value << std::endl;
+ return out;
+}
+
+std::istream &operator>>(std::istream &in, ConfigEnum &ce)
+{
+ in >> ce.name;
+ in >> ce.value;
+ return in;
+}
+
+std::ostream &operator<<(std::ostream &out, const ConfigUnknown &cu)
+{
+ out << "unknown: " << to_string(ConfigBit{cu.frame, cu.bit, false}) << std::endl;
+ return out;
+}
+
+std::istream &operator>>(std::istream &in, ConfigUnknown &cu)
+{
+ std::string s;
+ in >> s;
+ ConfigBit c = cbit_from_str(s);
+ cu.frame = c.frame;
+ cu.bit = c.bit;
+ assert(!c.inv);
+ return in;
+}
+
+std::ostream &operator<<(std::ostream &out, const TileConfig &tc)
+{
+ for (const auto &arc : tc.carcs)
+ out << arc;
+ for (const auto &cword : tc.cwords)
+ out << cword;
+ for (const auto &cenum : tc.cenums)
+ out << cenum;
+ for (const auto &cunk : tc.cunknowns)
+ out << cunk;
+ return out;
+}
+
+std::istream &operator>>(std::istream &in, TileConfig &tc)
+{
+ tc.carcs.clear();
+ tc.cwords.clear();
+ tc.cenums.clear();
+ while (!skip_check_eor(in)) {
+ std::string type;
+ in >> type;
+ if (type == "arc:") {
+ ConfigArc a;
+ in >> a;
+ tc.carcs.push_back(a);
+ } else if (type == "word:") {
+ ConfigWord w;
+ in >> w;
+ tc.cwords.push_back(w);
+ } else if (type == "enum:") {
+ ConfigEnum e;
+ in >> e;
+ tc.cenums.push_back(e);
+ } else if (type == "unknown:") {
+ ConfigUnknown u;
+ in >> u;
+ tc.cunknowns.push_back(u);
+ } else {
+ NPNR_ASSERT_FALSE_STR("unexpected token " + type + " while reading config text");
+ }
+ }
+ return in;
+}
+
+void TileConfig::add_arc(const std::string &sink, const std::string &source) { carcs.push_back({sink, source}); }
+
+void TileConfig::add_word(const std::string &name, const std::vector<bool> &value) { cwords.push_back({name, value}); }
+
+void TileConfig::add_enum(const std::string &name, const std::string &value) { cenums.push_back({name, value}); }
+
+void TileConfig::add_unknown(int frame, int bit) { cunknowns.push_back({frame, bit}); }
+
+std::string TileConfig::to_string() const
+{
+ std::stringstream ss;
+ ss << *this;
+ return ss.str();
+}
+
+TileConfig TileConfig::from_string(const std::string &str)
+{
+ std::stringstream ss(str);
+ TileConfig tc;
+ ss >> tc;
+ return tc;
+}
+
+bool TileConfig::empty() const { return carcs.empty() && cwords.empty() && cenums.empty() && cunknowns.empty(); }
+
+std::ostream &operator<<(std::ostream &out, const ChipConfig &cc)
+{
+ out << ".device " << cc.chip_name << std::endl << std::endl;
+ for (const auto &meta : cc.metadata)
+ out << ".comment " << meta << std::endl;
+ out << std::endl;
+ for (const auto &tile : cc.tiles) {
+ if (!tile.second.empty()) {
+ out << ".tile " << tile.first << std::endl;
+ out << tile.second;
+ out << std::endl;
+ }
+ }
+ return out;
+}
+
+std::istream &operator>>(std::istream &in, ChipConfig &cc)
+{
+ while (!skip_check_eof(in)) {
+ std::string verb;
+ in >> verb;
+ if (verb == ".device") {
+ in >> cc.chip_name;
+ } else if (verb == ".comment") {
+ std::string line;
+ getline(in, line);
+ cc.metadata.push_back(line);
+ } else if (verb == ".tile") {
+ std::string tilename;
+ in >> tilename;
+ TileConfig tc;
+ in >> tc;
+ cc.tiles[tilename] = tc;
+ } else {
+ log_error("unrecognised config entry %s\n", verb.c_str());
+ }
+ }
+ return in;
+}
+
+NEXTPNR_NAMESPACE_END
diff --git a/ecp5/config.h b/ecp5/config.h
new file mode 100644
index 00000000..038ddbf0
--- /dev/null
+++ b/ecp5/config.h
@@ -0,0 +1,116 @@
+/*
+ * nextpnr -- Next Generation Place and Route
+ *
+ * Copyright (C) 2018 David Shah <david@symbioticeda.com>
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#ifndef ECP5_CONFIG_H
+#define ECP5_CONFIG_H
+
+#include "nextpnr.h"
+#include <map>
+
+NEXTPNR_NAMESPACE_BEGIN
+
+// This represents configuration at "FASM" level, in terms of routing arcs and non-routing configuration settings -
+// either words or enums.
+
+// A connection in a tile
+struct ConfigArc
+{
+ std::string sink;
+ std::string source;
+ inline bool operator==(const ConfigArc &other) const { return other.source == source && other.sink == sink; }
+};
+
+std::ostream &operator<<(std::ostream &out, const ConfigArc &arc);
+
+std::istream &operator>>(std::istream &in, ConfigArc &arc);
+
+// A configuration setting in a tile that takes one or more bits (such as LUT init)
+struct ConfigWord
+{
+ std::string name;
+ std::vector<bool> value;
+ inline bool operator==(const ConfigWord &other) const { return other.name == name && other.value == value; }
+};
+
+std::ostream &operator<<(std::ostream &out, const ConfigWord &cw);
+
+std::istream &operator>>(std::istream &in, ConfigWord &cw);
+
+// A configuration setting in a tile that takes an enumeration value (such as IO type)
+struct ConfigEnum
+{
+ std::string name;
+ std::string value;
+ inline bool operator==(const ConfigEnum &other) const { return other.name == name && other.value == value; }
+};
+
+std::ostream &operator<<(std::ostream &out, const ConfigEnum &ce);
+
+std::istream &operator>>(std::istream &in, ConfigEnum &ce);
+
+// An unknown bit, specified by position only
+struct ConfigUnknown
+{
+ int frame, bit;
+ inline bool operator==(const ConfigUnknown &other) const { return other.frame == frame && other.bit == bit; }
+};
+
+std::ostream &operator<<(std::ostream &out, const ConfigUnknown &tc);
+
+std::istream &operator>>(std::istream &in, ConfigUnknown &ce);
+
+struct TileConfig
+{
+ std::vector<ConfigArc> carcs;
+ std::vector<ConfigWord> cwords;
+ std::vector<ConfigEnum> cenums;
+ std::vector<ConfigUnknown> cunknowns;
+ int total_known_bits = 0;
+
+ void add_arc(const std::string &sink, const std::string &source);
+ void add_word(const std::string &name, const std::vector<bool> &value);
+ void add_enum(const std::string &name, const std::string &value);
+ void add_unknown(int frame, int bit);
+
+ std::string to_string() const;
+ static TileConfig from_string(const std::string &str);
+
+ bool empty() const;
+};
+
+std::ostream &operator<<(std::ostream &out, const TileConfig &tc);
+
+std::istream &operator>>(std::istream &in, TileConfig &ce);
+
+// This represents the configuration of a chip at a high level
+class ChipConfig
+{
+ public:
+ std::string chip_name;
+ std::vector<std::string> metadata;
+ std::map<std::string, TileConfig> tiles;
+};
+
+std::ostream &operator<<(std::ostream &out, const ChipConfig &cc);
+
+std::istream &operator>>(std::istream &in, ChipConfig &cc);
+
+NEXTPNR_NAMESPACE_END
+
+#endif
diff --git a/ecp5/family.cmake b/ecp5/family.cmake
index 1c388e99..8315cf87 100644
--- a/ecp5/family.cmake
+++ b/ecp5/family.cmake
@@ -62,11 +62,3 @@ else()
endforeach (target)
endforeach (dev)
endif()
-
-find_library(TRELLIS_LIB trellis PATHS ${TRELLIS_ROOT}/libtrellis)
-
-foreach (target ${family_targets})
- target_compile_definitions(${target} PRIVATE TRELLIS_ROOT="${TRELLIS_ROOT}")
- target_include_directories(${target} PRIVATE ${TRELLIS_ROOT}/libtrellis/include)
- target_link_libraries(${target} PRIVATE ${TRELLIS_LIB})
-endforeach (target)
diff --git a/ecp5/main.cc b/ecp5/main.cc
index 68660ced..f40a5e61 100644
--- a/ecp5/main.cc
+++ b/ecp5/main.cc
@@ -32,10 +32,6 @@
#include <fstream>
#include <iostream>
-#include "Chip.hpp"
-#include "Database.hpp"
-#include "Tile.hpp"
-
#include "log.h"
#include "nextpnr.h"
#include "version.h"
@@ -75,7 +71,6 @@ int main(int argc, char *argv[])
options.add_options()("seed", po::value<int>(), "seed value for random number generator");
options.add_options()("basecfg", po::value<std::string>(), "base chip configuration in Trellis text format");
- options.add_options()("bit", po::value<std::string>(), "bitstream file to write");
options.add_options()("textcfg", po::value<std::string>(), "textual configuration in Trellis format to write");
po::positional_options_description pos;
@@ -115,8 +110,6 @@ int main(int argc, char *argv[])
return 1;
}
- Trellis::load_database(TRELLIS_ROOT "/database");
-
ArchArgs args;
args.type = ArchArgs::LFE5U_45F;
@@ -189,14 +182,10 @@ int main(int argc, char *argv[])
if (vm.count("basecfg"))
basecfg = vm["basecfg"].as<std::string>();
- std::string bitstream;
- if (vm.count("bit"))
- bitstream = vm["bit"].as<std::string>();
-
std::string textcfg;
if (vm.count("textcfg"))
textcfg = vm["textcfg"].as<std::string>();
- write_bitstream(ctx.get(), basecfg, textcfg, bitstream);
+ write_bitstream(ctx.get(), basecfg, textcfg);
}
#ifndef NO_PYTHON
diff --git a/ecp5/resource/chipdb.rc b/ecp5/resource/chipdb.rc
new file mode 100644
index 00000000..7191f581
--- /dev/null
+++ b/ecp5/resource/chipdb.rc
@@ -0,0 +1,5 @@
+#include "resource.h"
+
+IDR_CHIPDB_25K BINARYFILE "..\chipdbs\chipdb-25k.bin"
+IDR_CHIPDB_45K BINARYFILE "..\chipdbs\chipdb-45k.bin"
+IDR_CHIPDB_88K BINARYFILE "..\chipdbs\chipdb-85k.bin"
diff --git a/ecp5/resource/embed.cc b/ecp5/resource/embed.cc
new file mode 100644
index 00000000..adbb7781
--- /dev/null
+++ b/ecp5/resource/embed.cc
@@ -0,0 +1,28 @@
+#include <cstdio>
+#include <windows.h>
+#include "nextpnr.h"
+#include "resource.h"
+
+NEXTPNR_NAMESPACE_BEGIN
+
+const char *chipdb_blob_25k;
+const char *chipdb_blob_45k;
+const char *chipdb_blob_85k;
+
+const char *LoadFileInResource(int name, int type, DWORD &size)
+{
+ HMODULE handle = ::GetModuleHandle(NULL);
+ HRSRC rc = ::FindResource(handle, MAKEINTRESOURCE(name), MAKEINTRESOURCE(type));
+ HGLOBAL rcData = ::LoadResource(handle, rc);
+ size = ::SizeofResource(handle, rc);
+ return static_cast<const char *>(::LockResource(rcData));
+}
+void load_chipdb()
+{
+ DWORD size = 0;
+ chipdb_blob_25k = LoadFileInResource(IDR_CHIPDB_25K, BINARYFILE, size);
+ chipdb_blob_45k = LoadFileInResource(IDR_CHIPDB_45K, BINARYFILE, size);
+ chipdb_blob_85k = LoadFileInResource(IDR_CHIPDB_85K, BINARYFILE, size);
+}
+
+NEXTPNR_NAMESPACE_END \ No newline at end of file
diff --git a/ecp5/resource/resource.h b/ecp5/resource/resource.h
new file mode 100644
index 00000000..1a18bee2
--- /dev/null
+++ b/ecp5/resource/resource.h
@@ -0,0 +1,4 @@
+#define BINARYFILE 256
+#define IDR_CHIPDB_25K 101
+#define IDR_CHIPDB_45K 102
+#define IDR_CHIPDB_85K 103
diff --git a/ecp5/synth/.gitignore b/ecp5/synth/.gitignore
index 5b3bf578..f4dfa215 100644
--- a/ecp5/synth/.gitignore
+++ b/ecp5/synth/.gitignore
@@ -1 +1,3 @@
*.bit
+*_out.config
+
diff --git a/ecp5/trellis_import.py b/ecp5/trellis_import.py
index 9a4f30ab..99e9078f 100755
--- a/ecp5/trellis_import.py
+++ b/ecp5/trellis_import.py
@@ -136,7 +136,7 @@ def process_loc_globals(chip):
tapdrv = chip.global_data.get_tap_driver(y, x)
global_data[x, y] = (quadrants.index(quad), int(tapdrv.dir), tapdrv.col)
-def write_database(dev_name, ddrg, endianness):
+def write_database(dev_name, chip, ddrg, endianness):
def write_loc(loc, sym_name):
bba.u16(loc.x, "%s.x" % sym_name)
bba.u16(loc.y, "%s.y" % sym_name)
@@ -221,6 +221,20 @@ def write_database(dev_name, ddrg, endianness):
bba.r("loc%d_wires" % idx if len(loctype.wires) > 0 else None, "wire_data")
bba.r("loc%d_pips" % idx if len(loctype.arcs) > 0 else None, "pips_data")
+ for y in range(0, max_row+1):
+ for x in range(0, max_col+1):
+ bba.l("tile_info_%d_%d" % (x, y), "TileNamePOD")
+ for tile in chip.get_tiles_by_position(y, x):
+ bba.s(tile.info.name, "name")
+ bba.u16(get_tiletype_index(tile.info.type), "type_idx")
+ bba.u16(0, "padding")
+
+ bba.l("tiles_info", "TileInfoPOD")
+ for y in range(0, max_row+1):
+ for x in range(0, max_col+1):
+ bba.u32(len(chip.get_tiles_by_position(y, x)), "num_tiles")
+ bba.r("tile_info_%d_%d" % (x, y), "tile_names")
+
bba.l("location_types", "int32_t")
for y in range(0, max_row+1):
for x in range(0, max_col+1):
@@ -261,7 +275,7 @@ def write_database(dev_name, ddrg, endianness):
bba.l("tiletype_names", "RelPtr<char>")
- for tt in tiletype_names:
+ for tt, idx in sorted(tiletype_names.items(), key=lambda x: x[1]):
bba.s(tt, "name")
bba.l("chip_info")
@@ -278,6 +292,7 @@ def write_database(dev_name, ddrg, endianness):
bba.r("tiletype_names", "tiletype_names")
bba.r("package_data", "package_info")
bba.r("pio_info", "pio_info")
+ bba.r("tiles_info", "tile_info")
bba.pop()
return bba
@@ -311,7 +326,7 @@ def main():
process_pio_db(ddrg, args.device)
process_loc_globals(chip)
# print("{} unique location types".format(len(ddrg.locationTypes)))
- bba = write_database(args.device, ddrg, "le")
+ bba = write_database(args.device, chip, ddrg, "le")
diff --git a/generic/arch.cc b/generic/arch.cc
index 66fbd1ff..cff638df 100644
--- a/generic/arch.cc
+++ b/generic/arch.cc
@@ -420,7 +420,7 @@ delay_t getBudgetOverride(const NetInfo *net_info, const PortRef &sink, delay_t
bool Arch::place() { return placer1(getCtx()); }
-bool Arch::route() { return router1(getCtx()); }
+bool Arch::route() { return router1(getCtx(), Router1Cfg()); }
// ---------------------------------------------------------------
diff --git a/gui/basewindow.cc b/gui/basewindow.cc
index 6d5e97f5..685a205f 100644
--- a/gui/basewindow.cc
+++ b/gui/basewindow.cc
@@ -77,8 +77,9 @@ BaseMainWindow::BaseMainWindow(std::unique_ptr<Context> context, QWidget *parent
connect(centralTabWidget, SIGNAL(tabCloseRequested(int)), this, SLOT(closeTab(int)));
fpgaView = new FPGAViewWidget();
- centralTabWidget->addTab(fpgaView, "Graphics");
- centralTabWidget->tabBar()->tabButton(0, QTabBar::RightSide)->resize(0, 0);
+ centralTabWidget->addTab(fpgaView, "Device");
+ centralTabWidget->tabBar()->setTabButton(0, QTabBar::RightSide, 0);
+ centralTabWidget->tabBar()->setTabButton(0, QTabBar::LeftSide, 0);
connect(this, SIGNAL(contextChanged(Context *)), fpgaView, SLOT(newContext(Context *)));
connect(designview, SIGNAL(selected(std::vector<DecalXY>, bool)), fpgaView,
diff --git a/gui/treemodel.h b/gui/treemodel.h
index c3f9fe88..0236a715 100644
--- a/gui/treemodel.h
+++ b/gui/treemodel.h
@@ -102,7 +102,7 @@ class Item
virtual bool canFetchMore() const { return false; }
virtual void fetchMore() {}
- ~Item()
+ virtual ~Item()
{
if (parent_ != nullptr) {
parent_->deleteChild(this);
diff --git a/ice40/arch.cc b/ice40/arch.cc
index b3d514b5..eff1d9b9 100644
--- a/ice40/arch.cc
+++ b/ice40/arch.cc
@@ -661,7 +661,11 @@ delay_t Arch::getBudgetOverride(const NetInfo *net_info, const PortRef &sink, de
bool Arch::place() { return placer1(getCtx()); }
-bool Arch::route() { return router1(getCtx()); }
+bool Arch::route()
+{
+ Router1Cfg cfg;
+ return router1(getCtx(), cfg);
+}
// -----------------------------------------------------------------------
@@ -830,28 +834,23 @@ std::vector<GraphicElement> Arch::getDecalGraphics(DecalId decal) const
bool Arch::getCellDelay(const CellInfo *cell, IdString fromPort, IdString toPort, DelayInfo &delay) const
{
- if (cell->type == id_icestorm_lc) {
- if ((fromPort == id_i0 || fromPort == id_i1 || fromPort == id_i2 || fromPort == id_i3) &&
- (toPort == id_o || toPort == id_lo)) {
- delay.delay = 450;
- return true;
- } else if (fromPort == id_cin && toPort == id_cout) {
- delay.delay = 120;
- return true;
- } else if (fromPort == id_i1 && toPort == id_cout) {
- delay.delay = 260;
- return true;
- } else if (fromPort == id_i2 && toPort == id_cout) {
- delay.delay = 230;
- return true;
- } else if (fromPort == id_clk && toPort == id_o) {
- delay.delay = 540;
- return true;
- }
- } else if (cell->type == id_icestorm_ram) {
- if (fromPort == id_rclk) {
- delay.delay = 2140;
- return true;
+ BelType type = belTypeFromId(cell->type);
+ for (int i = 0; i < chip_info->num_timing_cells; i++) {
+ const auto &tc = chip_info->cell_timing[i];
+ if (tc.type == type) {
+ PortPin fromPin = portPinFromId(fromPort);
+ PortPin toPin = portPinFromId(toPort);
+ for (int j = 0; j < tc.num_paths; j++) {
+ const auto &path = tc.path_delays[j];
+ if (path.from_port == fromPin && path.to_port == toPin) {
+ if (fast_part)
+ delay.delay = path.fast_delay;
+ else
+ delay.delay = path.slow_delay;
+ return true;
+ }
+ }
+ break;
}
}
return false;
diff --git a/ice40/arch.h b/ice40/arch.h
index bfec7c16..e67f2aa9 100644
--- a/ice40/arch.h
+++ b/ice40/arch.h
@@ -172,10 +172,24 @@ NPNR_PACKED_STRUCT(struct BelConfigPOD {
RelPtr<BelConfigEntryPOD> entries;
});
+NPNR_PACKED_STRUCT(struct CellPathDelayPOD {
+ PortPin from_port;
+ PortPin to_port;
+ int32_t fast_delay;
+ int32_t slow_delay;
+});
+
+NPNR_PACKED_STRUCT(struct CellTimingPOD {
+ int32_t type;
+ int32_t num_paths;
+ RelPtr<CellPathDelayPOD> path_delays;
+});
+
NPNR_PACKED_STRUCT(struct ChipInfoPOD {
int32_t width, height;
int32_t num_bels, num_wires, num_pips;
int32_t num_switches, num_belcfgs, num_packages;
+ int32_t num_timing_cells;
RelPtr<BelInfoPOD> bel_data;
RelPtr<WireInfoPOD> wire_data;
RelPtr<PipInfoPOD> pip_data;
@@ -183,6 +197,7 @@ NPNR_PACKED_STRUCT(struct ChipInfoPOD {
RelPtr<BitstreamInfoPOD> bits_info;
RelPtr<BelConfigPOD> bel_config;
RelPtr<PackageInfoPOD> packages_data;
+ RelPtr<CellTimingPOD> cell_timing;
});
#if defined(_MSC_VER)
diff --git a/ice40/chipdb.py b/ice40/chipdb.py
index 97ccbe48..3f9f4e65 100644
--- a/ice40/chipdb.py
+++ b/ice40/chipdb.py
@@ -663,6 +663,60 @@ def add_bel_ec(ec):
else:
extra_cell_config[bel].append(entry)
+cell_timings = {}
+tmport_to_portpin = {
+ "posedge:clk": "CLK",
+ "ce": "CEN",
+ "sr": "SR",
+ "in0": "I0",
+ "in1": "I1",
+ "in2": "I2",
+ "in3": "I3",
+ "carryin": "CIN",
+ "carryout": "COUT",
+ "lcout": "O",
+ "ltout": "LO",
+ "posedge:RCLK": "RCLK",
+ "posedge:WCLK": "WCLK",
+ "RCLKE": "RCLKE",
+ "RE": "RE",
+ "WCLKE": "WCLKE",
+ "WE": "WE",
+ "posedge:CLOCK": "CLOCK",
+ "posedge:SLEEP": "SLEEP"
+}
+
+for i in range(16):
+ tmport_to_portpin["RDATA[%d]" % i] = "RDATA_%d" % i
+ tmport_to_portpin["WDATA[%d]" % i] = "WDATA_%d" % i
+ tmport_to_portpin["MASK[%d]" % i] = "MASK_%d" % i
+ tmport_to_portpin["DATAOUT[%d]" % i] = "DATAOUT_%d" % i
+
+for i in range(11):
+ tmport_to_portpin["RADDR[%d]" % i] = "RADDR_%d" % i
+ tmport_to_portpin["WADDR[%d]" % i] = "WADDR_%d" % i
+
+def add_cell_timingdata(bel_type, timing_cell, fast_db, slow_db):
+ timing_entries = []
+ database = slow_db if slow_db is not None else fast_db
+ for key in database.keys():
+ skey = key.split(".")
+ if skey[0] == timing_cell:
+ if skey[1] in tmport_to_portpin and skey[2] in tmport_to_portpin:
+ iport = tmport_to_portpin[skey[1]]
+ oport = tmport_to_portpin[skey[2]]
+ fastdel = fast_db[key] if fast_db is not None else 0
+ slowdel = slow_db[key] if slow_db is not None else 0
+ timing_entries.append((iport, oport, fastdel, slowdel))
+ cell_timings[bel_type] = timing_entries
+
+add_cell_timingdata("ICESTORM_LC", "LogicCell40", fast_timings, slow_timings)
+if dev_name != "384":
+ add_cell_timingdata("ICESTORM_RAM", "SB_RAM40_4K", fast_timings, slow_timings)
+if dev_name == "5k":
+ add_cell_timingdata("SPRAM", "SB_SPRAM256KA", fast_timings, slow_timings)
+
+
for tile_xy, tile_type in sorted(tiles.items()):
if tile_type == "logic":
for i in range(8):
@@ -1074,6 +1128,23 @@ for info in packageinfo:
bba.u32(info[1], "num_pins")
bba.r(info[2], "pins")
+for cell, timings in sorted(cell_timings.items()):
+ beltype = beltypes[cell]
+ bba.l("cell_paths_%d" % beltype, "CellPathDelayPOD")
+ for entry in timings:
+ fromport, toport, fast, slow = entry
+ bba.u32(portpins[fromport], "from_port")
+ bba.u32(portpins[toport], "to_port")
+ bba.u32(fast, "fast_delay")
+ bba.u32(slow, "slow_delay")
+
+bba.l("cell_timings_%s" % dev_name, "CellTimingPOD")
+for cell, timings in sorted(cell_timings.items()):
+ beltype = beltypes[cell]
+ bba.u32(beltype, "type")
+ bba.u32(len(timings), "num_paths")
+ bba.r("cell_paths_%d" % beltype, "path_delays")
+
bba.l("chip_info_%s" % dev_name)
bba.u32(dev_width, "dev_width")
bba.u32(dev_height, "dev_height")
@@ -1083,6 +1154,7 @@ bba.u32(len(pipinfo), "num_pips")
bba.u32(len(switchinfo), "num_switches")
bba.u32(len(extra_cell_config), "num_belcfgs")
bba.u32(len(packageinfo), "num_packages")
+bba.u32(len(cell_timings), "num_timing_cells")
bba.r("bel_data_%s" % dev_name, "bel_data")
bba.r("wire_data_%s" % dev_name, "wire_data")
bba.r("pip_data_%s" % dev_name, "pip_data")
@@ -1090,5 +1162,6 @@ bba.r("tile_grid_%s" % dev_name, "tile_grid")
bba.r("bits_info_%s" % dev_name, "bits_info")
bba.r("bel_config_%s" % dev_name if len(extra_cell_config) > 0 else None, "bel_config")
bba.r("package_info_%s" % dev_name, "packages_data")
+bba.r("cell_timings_%s" % dev_name, "cell_timing")
bba.pop()
diff --git a/ice40/main.cc b/ice40/main.cc
index 0724acdf..358b46ba 100644
--- a/ice40/main.cc
+++ b/ice40/main.cc
@@ -168,6 +168,11 @@ int main(int argc, char *argv[])
pt::read_json(filename, root);
log_info("Loading project %s...\n", filename.c_str());
log_break();
+
+ bool isLoadingGui = vm.count("gui") > 0;
+ std::string ascOutput;
+ if (vm.count("asc"))
+ ascOutput = vm["asc"].as<std::string>();
vm.clear();
int version = root.get<int>("project.version");
@@ -199,6 +204,10 @@ int main(int argc, char *argv[])
if (params.count("seed"))
vm.insert(std::make_pair("seed", po::variable_value(params.get<int>("seed"), false)));
}
+ if (!ascOutput.empty())
+ vm.insert(std::make_pair("asc", po::variable_value(ascOutput, false)));
+ if (isLoadingGui)
+ vm.insert(std::make_pair("gui", po::variable_value()));
po::notify(vm);
} catch (...) {
log_error("Error loading project file.\n");
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-19 04:08:20 +0000