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-rw-r--r--README.md5
-rw-r--r--common/nextpnr.h1
-rw-r--r--common/placer1.cc11
-rw-r--r--common/router1.cc4
-rw-r--r--common/timing.cc177
-rw-r--r--common/timing.h8
-rw-r--r--ecp5/arch.cc64
-rw-r--r--ecp5/arch.h5
-rw-r--r--ecp5/archdefs.h13
-rw-r--r--ecp5/gfx.h35
-rw-r--r--ecp5/main.cc16
-rw-r--r--generic/arch.cc4
-rw-r--r--generic/arch.h5
-rw-r--r--gui/designwidget.cc26
-rw-r--r--gui/designwidget.h6
-rw-r--r--gui/ecp5/mainwindow.cc2
-rw-r--r--gui/generic/mainwindow.cc2
-rw-r--r--gui/treemodel.cc19
-rw-r--r--gui/treemodel.h1
-rw-r--r--ice40/arch.cc78
-rw-r--r--ice40/arch.h24
-rw-r--r--ice40/chipdb.py131
-rw-r--r--ice40/family.cmake25
-rw-r--r--ice40/main.cc6
-rw-r--r--ice40/place_legaliser.cc42
-rw-r--r--python/functions.py21
-rw-r--r--python/python_mod_test.py7
-rw-r--r--python/python_test.py2
28 files changed, 584 insertions, 156 deletions
diff --git a/README.md b/README.md
index 51141b09..c22579ba 100644
--- a/README.md
+++ b/README.md
@@ -162,3 +162,8 @@ Links and references
- [SymbiFlow](https://github.com/SymbiFlow/symbiflow-arch-defs)
- [Gaffe](https://github.com/kc8apf/gaffe)
- [KinglerPAR](https://github.com/rqou/KinglerPAR)
+
+> SymbiFlow is working with the Verilog to Routing tool to extend the current
+research tool to support real architectures. VtR is strongly focused on
+architecture research but having support for real architectures might enable
+research nextpnr zu providing documentation and explanation.
diff --git a/common/nextpnr.h b/common/nextpnr.h
index 908b8266..38a313fd 100644
--- a/common/nextpnr.h
+++ b/common/nextpnr.h
@@ -475,6 +475,7 @@ struct Context : Arch, DeterministicRNG
bool force = false;
bool timing_driven = true;
float target_freq = 12e6;
+ bool user_freq = false;
Context(ArchArgs args) : Arch(args) {}
diff --git a/common/placer1.cc b/common/placer1.cc
index ee7225b5..c677a22a 100644
--- a/common/placer1.cc
+++ b/common/placer1.cc
@@ -152,6 +152,7 @@ class SAPlacer
}
int n_no_progress = 0;
+ wirelen_t min_metric = curr_metric;
double avg_metric = curr_metric;
temp = 10000;
@@ -177,6 +178,11 @@ class SAPlacer
}
}
+ if (curr_metric < min_metric) {
+ min_metric = curr_metric;
+ improved = true;
+ }
+
// Heuristic to improve placement on the 8k
if (improved)
n_no_progress = 0;
@@ -230,6 +236,8 @@ class SAPlacer
diameter *= post_legalise_dia_scale;
ctx->shuffle(autoplaced);
assign_budget(ctx);
+ } else {
+ assign_budget(ctx, true /* quiet */);
}
// Recalculate total metric entirely to avoid rounding errors
@@ -264,6 +272,7 @@ class SAPlacer
}
}
}
+ timing_analysis(ctx, true /* print_fmax */);
ctx->unlock();
return true;
}
@@ -379,8 +388,6 @@ class SAPlacer
// SA acceptance criterea
if (delta < 0 || (temp > 1e-6 && (ctx->rng() / float(0x3fffffff)) <= std::exp(-delta / temp))) {
n_accept++;
- if (delta < 2)
- improved = true;
} else {
if (other != IdString())
ctx->unbindBel(oldBel);
diff --git a/common/router1.cc b/common/router1.cc
index 4ef7df64..0bd257fd 100644
--- a/common/router1.cc
+++ b/common/router1.cc
@@ -22,6 +22,7 @@
#include "log.h"
#include "router1.h"
+#include "timing.h"
namespace {
@@ -615,6 +616,8 @@ bool router1(Context *ctx)
if (ctx->verbose || iterCnt == 1)
log_info("routing queue contains %d jobs.\n", int(jobQueue.size()));
+ assign_budget(ctx, true /* quiet */);
+
bool printNets = ctx->verbose && (jobQueue.size() < 10);
while (!jobQueue.empty()) {
@@ -811,6 +814,7 @@ bool router1(Context *ctx)
#ifndef NDEBUG
ctx->check();
#endif
+ timing_analysis(ctx, true /* print_fmax */, true /* print_path */);
ctx->unlock();
return true;
} catch (log_execution_error_exception) {
diff --git a/common/timing.cc b/common/timing.cc
index d91dea20..f33a2ef1 100644
--- a/common/timing.cc
+++ b/common/timing.cc
@@ -22,99 +22,200 @@
#include <unordered_map>
#include <utility>
#include "log.h"
+#include "util.h"
NEXTPNR_NAMESPACE_BEGIN
-static delay_t follow_net(Context *ctx, NetInfo *net, int path_length, delay_t slack);
+typedef std::list<const PortRef *> PortRefList;
+
+static delay_t follow_net(Context *ctx, NetInfo *net, int path_length, delay_t slack, bool update, delay_t &min_slack,
+ PortRefList *current_path, PortRefList *crit_path);
// Follow a path, returning budget to annotate
-static delay_t follow_user_port(Context *ctx, PortRef &user, int path_length, delay_t slack)
+static delay_t follow_user_port(Context *ctx, PortRef &user, int path_length, delay_t slack, bool update,
+ delay_t &min_slack, PortRefList *current_path, PortRefList *crit_path)
{
delay_t value;
if (ctx->getPortClock(user.cell, user.port) != IdString()) {
// At the end of a timing path (arguably, should check setup time
// here too)
value = slack / path_length;
+ if (slack < min_slack) {
+ min_slack = slack;
+ if (crit_path)
+ *crit_path = *current_path;
+ }
} else {
// Default to the path ending here, if no further paths found
value = slack / path_length;
// Follow outputs of the user
for (auto port : user.cell->ports) {
if (port.second.type == PORT_OUT) {
- delay_t comb_delay;
+ DelayInfo comb_delay;
// Look up delay through this path
bool is_path = ctx->getCellDelay(user.cell, user.port, port.first, comb_delay);
if (is_path) {
NetInfo *net = port.second.net;
if (net) {
- delay_t path_budget = follow_net(ctx, net, path_length, slack - comb_delay);
+ delay_t path_budget = follow_net(ctx, net, path_length, slack - comb_delay.maxDelay(), update, min_slack,
+ current_path, crit_path);
value = std::min(value, path_budget);
}
}
}
}
}
-
- if (value < user.budget) {
- user.budget = value;
- }
return value;
}
-static delay_t follow_net(Context *ctx, NetInfo *net, int path_length, delay_t slack)
+static delay_t follow_net(Context *ctx, NetInfo *net, int path_length, delay_t slack, bool update, delay_t &min_slack,
+ PortRefList *current_path, PortRefList *crit_path)
{
delay_t net_budget = slack / (path_length + 1);
- for (auto &usr : net->users) {
- net_budget = std::min(net_budget, follow_user_port(ctx, usr, path_length + 1, slack));
+ for (unsigned i = 0; i < net->users.size(); ++i) {
+ auto &usr = net->users[i];
+ if (crit_path)
+ current_path->push_back(&usr);
+ // If budget override is less than existing budget, then do not increment path length
+ int pl = path_length + 1;
+ auto budget = ctx->getBudgetOverride(net, i, net_budget);
+ if (budget < net_budget) {
+ net_budget = budget;
+ pl = std::max(1, path_length);
+ }
+ auto delay = ctx->getNetinfoRouteDelay(net, i);
+ net_budget = std::min(
+ net_budget, follow_user_port(ctx, usr, pl, slack - delay, update, min_slack, current_path, crit_path));
+ if (update)
+ usr.budget = std::min(usr.budget, delay + net_budget);
+ if (crit_path)
+ current_path->pop_back();
}
return net_budget;
}
-void assign_budget(Context *ctx)
+static delay_t walk_paths(Context *ctx, bool update, PortRefList *crit_path)
{
- log_break();
- log_info("Annotating ports with timing budgets\n");
- // Clear delays to a very high value first
delay_t default_slack = delay_t(1.0e12 / ctx->target_freq);
- for (auto &net : ctx->nets) {
- for (auto &usr : net.second->users) {
- usr.budget = default_slack;
- }
- }
- // Go through all clocked drivers and set up paths
+ delay_t min_slack = default_slack;
+
+ PortRefList current_path;
+
+ // Go through all clocked drivers and distribute the available path
+ // slack evenly into the budget of every sink on the path ---
+ // record this value into the UpdateMap
for (auto &cell : ctx->cells) {
for (auto port : cell.second->ports) {
if (port.second.type == PORT_OUT) {
IdString clock_domain = ctx->getPortClock(cell.second.get(), port.first);
if (clock_domain != IdString()) {
- delay_t slack = delay_t(1.0e12 / ctx->target_freq); // TODO: clock constraints
- delay_t clkToQ;
+ delay_t slack = default_slack; // TODO: clock constraints
+ DelayInfo clkToQ;
if (ctx->getCellDelay(cell.second.get(), clock_domain, port.first, clkToQ))
- slack -= clkToQ;
+ slack -= clkToQ.maxDelay();
if (port.second.net)
- follow_net(ctx, port.second.net, 0, slack);
+ follow_net(ctx, port.second.net, 0, slack, update, min_slack, &current_path, crit_path);
}
}
}
}
- // Post-allocation check
+ return min_slack;
+}
+
+void assign_budget(Context *ctx, bool quiet)
+{
+ if (!quiet) {
+ log_break();
+ log_info("Annotating ports with timing budgets\n");
+ }
+
+ // Clear delays to a very high value first
+ delay_t default_slack = delay_t(1.0e12 / ctx->target_freq);
for (auto &net : ctx->nets) {
- for (auto user : net.second->users) {
- if (user.budget < 0)
- log_warning("port %s.%s, connected to net '%s', has negative "
- "timing budget of %fns\n",
- user.cell->name.c_str(ctx), user.port.c_str(ctx), net.first.c_str(ctx),
- ctx->getDelayNS(user.budget));
- if (ctx->verbose)
- log_info("port %s.%s, connected to net '%s', has "
- "timing budget of %fns\n",
- user.cell->name.c_str(ctx), user.port.c_str(ctx), net.first.c_str(ctx),
- ctx->getDelayNS(user.budget));
+ for (auto &usr : net.second->users) {
+ usr.budget = default_slack;
+ }
+ }
+
+ delay_t min_slack = walk_paths(ctx, true, nullptr);
+
+ if (!quiet || ctx->verbose) {
+ for (auto &net : ctx->nets) {
+ for (auto &user : net.second->users) {
+ // Post-update check
+ if (ctx->user_freq && user.budget < 0)
+ log_warning("port %s.%s, connected to net '%s', has negative "
+ "timing budget of %fns\n",
+ user.cell->name.c_str(ctx), user.port.c_str(ctx), net.first.c_str(ctx),
+ ctx->getDelayNS(user.budget));
+ else if (ctx->verbose)
+ log_info("port %s.%s, connected to net '%s', has "
+ "timing budget of %fns\n",
+ user.cell->name.c_str(ctx), user.port.c_str(ctx), net.first.c_str(ctx),
+ ctx->getDelayNS(user.budget));
+ }
}
}
- log_info("Checksum: 0x%08x\n", ctx->checksum());
+ // If user has not specified a frequency, dynamically adjust the target
+ // frequency to be the current maximum
+ if (!ctx->user_freq) {
+ ctx->target_freq = 1e12 / (default_slack - 1.2 * min_slack);
+ if (ctx->verbose)
+ log_info("minimum slack for this assign = %d, target Fmax for next update = %.2f MHz\n", min_slack,
+ ctx->target_freq / 1e6);
+ }
+
+ if (!quiet)
+ log_info("Checksum: 0x%08x\n", ctx->checksum());
+}
+
+delay_t timing_analysis(Context *ctx, bool print_fmax, bool print_path)
+{
+ delay_t default_slack = delay_t(1.0e12 / ctx->target_freq);
+ PortRefList crit_path;
+ delay_t min_slack = walk_paths(ctx, false, &crit_path);
+ if (print_path) {
+ delay_t total = 0;
+ log_break();
+ log_info("Critical path report:\n");
+ log_info("curr total\n");
+ auto &front = crit_path.front();
+ auto &front_port = front->cell->ports.at(front->port);
+ auto &front_driver = front_port.net->driver;
+ auto last_port = ctx->getPortClock(front_driver.cell, front_driver.port);
+ for (auto sink : crit_path) {
+ auto sink_cell = sink->cell;
+ auto &port = sink_cell->ports.at(sink->port);
+ auto net = port.net;
+ unsigned i = 0;
+ for (auto &usr : net->users)
+ if (&usr == sink)
+ break;
+ else
+ ++i;
+ auto &driver = net->driver;
+ auto driver_cell = driver.cell;
+ DelayInfo comb_delay;
+ ctx->getCellDelay(sink_cell, last_port, driver.port, comb_delay);
+ total += comb_delay.maxDelay();
+ log_info("%4d %4d Source %s.%s\n", comb_delay.maxDelay(), total, driver_cell->name.c_str(ctx),
+ driver.port.c_str(ctx));
+ delay_t net_delay = ctx->getNetinfoRouteDelay(net, i);
+ total += net_delay;
+ auto driver_loc = ctx->getBelLocation(driver_cell->bel);
+ auto sink_loc = ctx->getBelLocation(sink_cell->bel);
+ log_info("%4d %4d Net %s budget %d (%d,%d) -> (%d,%d)\n", net_delay, total, net->name.c_str(ctx),
+ sink->budget, driver_loc.x, driver_loc.y, sink_loc.x, sink_loc.y);
+ log_info(" Sink %s.%s\n", sink_cell->name.c_str(ctx), sink->port.c_str(ctx));
+ last_port = sink->port;
+ }
+ log_break();
+ }
+ if (print_fmax)
+ log_info("estimated Fmax = %.2f MHz\n", 1e6 / (default_slack - min_slack));
+ return min_slack;
}
NEXTPNR_NAMESPACE_END
diff --git a/common/timing.h b/common/timing.h
index 025e4a76..d0159d5c 100644
--- a/common/timing.h
+++ b/common/timing.h
@@ -24,8 +24,12 @@
NEXTPNR_NAMESPACE_BEGIN
-// Assign "budget" values for all user ports in the design
-void assign_budget(Context *ctx);
+// Evenly redistribute the total path slack amongst all sinks on each path
+void assign_budget(Context *ctx, bool quiet = false);
+
+// Perform timing analysis and return the minimum path slack,
+// optionally, print out the fmax and critical path
+delay_t timing_analysis(Context *ctx, bool print_fmax = false, bool print_path = false);
NEXTPNR_NAMESPACE_END
diff --git a/ecp5/arch.cc b/ecp5/arch.cc
index 23105df2..14b5b8f2 100644
--- a/ecp5/arch.cc
+++ b/ecp5/arch.cc
@@ -21,6 +21,7 @@
#include <algorithm>
#include <cmath>
#include <cstring>
+#include "gfx.h"
#include "log.h"
#include "nextpnr.h"
#include "placer1.h"
@@ -140,9 +141,8 @@ Arch::Arch(ArchArgs args) : args(args)
// -----------------------------------------------------------------------
-std::string Arch::getChipName()
+std::string Arch::getChipName() const
{
-
if (args.type == ArchArgs::LFE5U_25F) {
return "LFE5U-25F";
} else if (args.type == ArchArgs::LFE5U_45F) {
@@ -422,6 +422,8 @@ delay_t Arch::predictDelay(const NetInfo *net_info, const PortRef &sink) const;
return 200 * (abs(driver_loc.x - sink_loc.x) + abs(driver_loc.y - sink_loc.y));
}
+delay_t Arch::getBudgetOverride(NetInfo *net_info, int user_idx, delay_t budget) const { return budget; }
+
// -----------------------------------------------------------------------
bool Arch::place() { return placer1(getCtx()); }
@@ -430,16 +432,64 @@ bool Arch::route() { return router1(getCtx()); }
// -----------------------------------------------------------------------
-std::vector<GraphicElement> Arch::getDecalGraphics(DecalId decalId) const
+std::vector<GraphicElement> Arch::getDecalGraphics(DecalId decal) const
{
std::vector<GraphicElement> ret;
- // FIXME
+
+ if (decal.type == DecalId::TYPE_FRAME) {
+ /* nothing */
+ }
+
+ if (decal.type == DecalId::TYPE_BEL) {
+ BelId bel;
+ bel.index = decal.z;
+ bel.location = decal.location;
+ int z = locInfo(bel)->bel_data[bel.index].z;
+ auto bel_type = getBelType(bel);
+
+ if (bel_type == TYPE_TRELLIS_SLICE) {
+ GraphicElement el;
+ el.type = GraphicElement::TYPE_BOX;
+ el.style = decal.active ? GraphicElement::STYLE_ACTIVE : GraphicElement::STYLE_INACTIVE;
+ el.x1 = bel.location.x + logic_cell_x1;
+ el.x2 = bel.location.x + logic_cell_x2;
+ el.y1 = bel.location.y + logic_cell_y1 + (z)*logic_cell_pitch;
+ el.y2 = bel.location.y + logic_cell_y2 + (z)*logic_cell_pitch;
+ ret.push_back(el);
+ }
+
+ if (bel_type == TYPE_TRELLIS_IO) {
+ GraphicElement el;
+ el.type = GraphicElement::TYPE_BOX;
+ el.style = decal.active ? GraphicElement::STYLE_ACTIVE : GraphicElement::STYLE_INACTIVE;
+ el.x1 = bel.location.x + logic_cell_x1;
+ el.x2 = bel.location.x + logic_cell_x2;
+ el.y1 = bel.location.y + logic_cell_y1 + (2 * z) * logic_cell_pitch;
+ el.y2 = bel.location.y + logic_cell_y2 + (2 * z + 1) * logic_cell_pitch;
+ ret.push_back(el);
+ }
+ }
+
return ret;
}
-DecalXY Arch::getFrameDecal() const { return {}; }
+DecalXY Arch::getFrameDecal() const
+{
+ DecalXY decalxy;
+ decalxy.decal.type = DecalId::TYPE_FRAME;
+ decalxy.decal.active = true;
+ return decalxy;
+}
-DecalXY Arch::getBelDecal(BelId bel) const { return {}; }
+DecalXY Arch::getBelDecal(BelId bel) const
+{
+ DecalXY decalxy;
+ decalxy.decal.type = DecalId::TYPE_BEL;
+ decalxy.decal.location = bel.location;
+ decalxy.decal.z = bel.index;
+ decalxy.decal.active = bel_to_cell.count(bel) && (bel_to_cell.at(bel) != IdString());
+ return decalxy;
+}
DecalXY Arch::getWireDecal(WireId wire) const { return {}; }
@@ -449,7 +499,7 @@ DecalXY Arch::getGroupDecal(GroupId pip) const { return {}; };
// -----------------------------------------------------------------------
-bool Arch::getCellDelay(const CellInfo *cell, IdString fromPort, IdString toPort, delay_t &delay) const
+bool Arch::getCellDelay(const CellInfo *cell, IdString fromPort, IdString toPort, DelayInfo &delay) const
{
return false;
}
diff --git a/ecp5/arch.h b/ecp5/arch.h
index 400d6e55..255bafc7 100644
--- a/ecp5/arch.h
+++ b/ecp5/arch.h
@@ -399,7 +399,7 @@ struct Arch : BaseCtx
ArchArgs args;
Arch(ArchArgs args);
- std::string getChipName();
+ std::string getChipName() const;
IdString archId() const { return id("ecp5"); }
IdString archArgsToId(ArchArgs args) const;
@@ -781,6 +781,7 @@ struct Arch : BaseCtx
delay_t getRipupDelayPenalty() const { return 200; }
float getDelayNS(delay_t v) const { return v * 0.001; }
uint32_t getDelayChecksum(delay_t v) const { return v; }
+ delay_t getBudgetOverride(NetInfo *net_info, int user_idx, delay_t budget) const;
// -------------------------------------------------
@@ -802,7 +803,7 @@ struct Arch : BaseCtx
// Get the delay through a cell from one port to another, returning false
// if no path exists
- bool getCellDelay(const CellInfo *cell, IdString fromPort, IdString toPort, delay_t &delay) const;
+ bool getCellDelay(const CellInfo *cell, IdString fromPort, IdString toPort, DelayInfo &delay) const;
// Get the associated clock to a port, or empty if the port is combinational
IdString getPortClock(const CellInfo *cell, IdString port) const;
// Return true if a port is a clock
diff --git a/ecp5/archdefs.h b/ecp5/archdefs.h
index 40442e1b..829db683 100644
--- a/ecp5/archdefs.h
+++ b/ecp5/archdefs.h
@@ -120,17 +120,21 @@ struct GroupId
struct DecalId
{
- char type = 0; // Bel/Wire/Pip/Frame (b/w/p/f)
+ enum
+ {
+ TYPE_FRAME,
+ TYPE_BEL
+ } type;
Location location;
uint32_t z = 0;
-
+ bool active = false;
bool operator==(const DecalId &other) const
{
- return type == other.type && location == other.location && z == other.z;
+ return type == other.type && location == other.location && z == other.z && active == other.active;
}
bool operator!=(const DecalId &other) const
{
- return type != other.type || location != other.location || z != other.z;
+ return type != other.type || location != other.location || z != other.z || active != other.active;
}
};
@@ -200,6 +204,7 @@ template <> struct hash<NEXTPNR_NAMESPACE_PREFIX DecalId>
boost::hash_combine(seed, hash<int>()(decal.type));
boost::hash_combine(seed, hash<NEXTPNR_NAMESPACE_PREFIX Location>()(decal.location));
boost::hash_combine(seed, hash<int>()(decal.z));
+ boost::hash_combine(seed, hash<bool>()(decal.active));
return seed;
}
};
diff --git a/ecp5/gfx.h b/ecp5/gfx.h
new file mode 100644
index 00000000..0290d2f6
--- /dev/null
+++ b/ecp5/gfx.h
@@ -0,0 +1,35 @@
+/*
+ * nextpnr -- Next Generation Place and Route
+ *
+ * Copyright (C) 2018 David Shah <david@symbioticeda.com>
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#ifndef ECP5_GFX_H
+#define ECP5_GFX_H
+
+#include "nextpnr.h"
+
+NEXTPNR_NAMESPACE_BEGIN
+
+const float logic_cell_x1 = 0.76;
+const float logic_cell_x2 = 0.95;
+const float logic_cell_y1 = 0.05;
+const float logic_cell_y2 = 0.15;
+const float logic_cell_pitch = 0.125;
+
+NEXTPNR_NAMESPACE_END
+
+#endif
diff --git a/ecp5/main.cc b/ecp5/main.cc
index f2db74d7..68660ced 100644
--- a/ecp5/main.cc
+++ b/ecp5/main.cc
@@ -100,16 +100,18 @@ int main(int argc, char *argv[])
}
if (vm.count("help") || argc == 1) {
- std::cout << boost::filesystem::basename(argv[0]) << " -- Next Generation Place and Route (git "
- "sha1 " GIT_COMMIT_HASH_STR ")\n";
+ std::cout << boost::filesystem::basename(argv[0])
+ << " -- Next Generation Place and Route (git "
+ "sha1 " GIT_COMMIT_HASH_STR ")\n";
std::cout << "\n";
std::cout << options << "\n";
return argc != 1;
}
if (vm.count("version")) {
- std::cout << boost::filesystem::basename(argv[0]) << " -- Next Generation Place and Route (git "
- "sha1 " GIT_COMMIT_HASH_STR ")\n";
+ std::cout << boost::filesystem::basename(argv[0])
+ << " -- Next Generation Place and Route (git "
+ "sha1 " GIT_COMMIT_HASH_STR ")\n";
return 1;
}
@@ -167,8 +169,12 @@ int main(int argc, char *argv[])
if (!ctx->pack() && !ctx->force)
log_error("Packing design failed.\n");
- if (vm.count("freq"))
+ if (vm.count("freq")) {
ctx->target_freq = vm["freq"].as<double>() * 1e6;
+ ctx->user_freq = true;
+ } else {
+ log_warning("Target frequency not specified. Will optimise for max frequency.\n");
+ }
assign_budget(ctx.get());
ctx->check();
print_utilisation(ctx.get());
diff --git a/generic/arch.cc b/generic/arch.cc
index 4469a828..43015685 100644
--- a/generic/arch.cc
+++ b/generic/arch.cc
@@ -414,6 +414,8 @@ delay_t Arch::predictDelay(const NetInfo *net_info, const PortRef &sink) const;
return (dx + dy) * grid_distance_to_delay;
}
+delay_t Arch::getBudgetOverride(NetInfo *net_info, int user_idx, delay_t budget) const { return budget; }
+
// ---------------------------------------------------------------
bool Arch::place() { return placer1(getCtx()); }
@@ -436,7 +438,7 @@ DecalXY Arch::getGroupDecal(GroupId group) const { return groups.at(group).decal
// ---------------------------------------------------------------
-bool Arch::getCellDelay(const CellInfo *cell, IdString fromPort, IdString toPort, delay_t &delay) const
+bool Arch::getCellDelay(const CellInfo *cell, IdString fromPort, IdString toPort, DelayInfo &delay) const
{
return false;
}
diff --git a/generic/arch.h b/generic/arch.h
index f02649f6..154a2352 100644
--- a/generic/arch.h
+++ b/generic/arch.h
@@ -122,7 +122,7 @@ struct Arch : BaseCtx
Arch(ArchArgs args);
- std::string getChipName() { return chipName; }
+ std::string getChipName() const { return chipName; }
IdString archId() const { return id("generic"); }
IdString archArgsToId(ArchArgs args) const { return id("none"); }
@@ -199,6 +199,7 @@ struct Arch : BaseCtx
delay_t getRipupDelayPenalty() const { return 1.0; }
float getDelayNS(delay_t v) const { return v; }
uint32_t getDelayChecksum(delay_t v) const { return 0; }
+ delay_t getBudgetOverride(NetInfo *net_info, int user_idx, delay_t budget) const;
bool pack() { return true; }
bool place();
@@ -211,7 +212,7 @@ struct Arch : BaseCtx
DecalXY getPipDecal(PipId pip) const;
DecalXY getGroupDecal(GroupId group) const;
- bool getCellDelay(const CellInfo *cell, IdString fromPort, IdString toPort, delay_t &delay) const;
+ bool getCellDelay(const CellInfo *cell, IdString fromPort, IdString toPort, DelayInfo &delay) const;
IdString getPortClock(const CellInfo *cell, IdString port) const;
bool isClockPort(const CellInfo *cell, IdString port) const;
diff --git a/gui/designwidget.cc b/gui/designwidget.cc
index 5107fbee..e8c05ef9 100644
--- a/gui/designwidget.cc
+++ b/gui/designwidget.cc
@@ -51,10 +51,11 @@ DesignWidget::DesignWidget(QWidget *parent) : QWidget(parent), ctx(nullptr), sel
propertyEditor->treeWidget()->setContextMenuPolicy(Qt::CustomContextMenu);
propertyEditor->treeWidget()->setSelectionMode(QAbstractItemView::ExtendedSelection);
- QLineEdit *lineEdit = new QLineEdit();
- lineEdit->setClearButtonEnabled(true);
- lineEdit->addAction(QIcon(":/icons/resources/zoom.png"), QLineEdit::LeadingPosition);
- lineEdit->setPlaceholderText("Search...");
+ searchEdit = new QLineEdit();
+ searchEdit->setClearButtonEnabled(true);
+ searchEdit->addAction(QIcon(":/icons/resources/zoom.png"), QLineEdit::LeadingPosition);
+ searchEdit->setPlaceholderText("Search...");
+ connect(searchEdit, SIGNAL(returnPressed()), this, SLOT(onSearchInserted()));
actionFirst = new QAction("", this);
actionFirst->setIcon(QIcon(":/icons/resources/resultset_first.png"));
@@ -123,7 +124,7 @@ DesignWidget::DesignWidget(QWidget *parent) : QWidget(parent), ctx(nullptr), sel
topWidget->setLayout(vbox1);
vbox1->setSpacing(5);
vbox1->setContentsMargins(0, 0, 0, 0);
- vbox1->addWidget(lineEdit);
+ vbox1->addWidget(searchEdit);
vbox1->addWidget(treeView);
QWidget *toolbarWidget = new QWidget();
@@ -714,4 +715,19 @@ void DesignWidget::onItemDoubleClicked(QTreeWidgetItem *item, int column)
}
void DesignWidget::onDoubleClicked(const QModelIndex &index) { Q_EMIT zoomSelected(); }
+
+void DesignWidget::onSearchInserted()
+{
+ if (currentSearch == searchEdit->text()) {
+ currentIndex++;
+ if (currentIndex >= currentSearchIndexes.size())
+ currentIndex = 0;
+ } else {
+ currentSearch = searchEdit->text();
+ currentSearchIndexes = treeModel->search(searchEdit->text());
+ currentIndex = 0;
+ }
+ if (currentSearchIndexes.size() > 0 && currentIndex < currentSearchIndexes.size())
+ selectionModel->setCurrentIndex(currentSearchIndexes.at(currentIndex), QItemSelectionModel::ClearAndSelect);
+}
NEXTPNR_NAMESPACE_END
diff --git a/gui/designwidget.h b/gui/designwidget.h
index 27ead589..535fd0c3 100644
--- a/gui/designwidget.h
+++ b/gui/designwidget.h
@@ -64,6 +64,7 @@ class DesignWidget : public QWidget
void onSelectionChanged(const QItemSelection &selected, const QItemSelection &deselected);
void onItemDoubleClicked(QTreeWidgetItem *item, int column);
void onDoubleClicked(const QModelIndex &index);
+ void onSearchInserted();
public Q_SLOTS:
void newContext(Context *ctx);
void updateTree();
@@ -77,6 +78,7 @@ class DesignWidget : public QWidget
QTreeView *treeView;
QItemSelectionModel *selectionModel;
ContextTreeModel *treeModel;
+ QLineEdit *searchEdit;
QtVariantPropertyManager *variantManager;
QtVariantPropertyManager *readOnlyManager;
QtGroupPropertyManager *groupManager;
@@ -98,6 +100,10 @@ class DesignWidget : public QWidget
QColor highlightColors[8];
QMap<ContextTreeItem *, int> highlightSelected;
+
+ QString currentSearch;
+ QList<QModelIndex> currentSearchIndexes;
+ int currentIndex;
};
NEXTPNR_NAMESPACE_END
diff --git a/gui/ecp5/mainwindow.cc b/gui/ecp5/mainwindow.cc
index 1168a55c..4b1c7e3b 100644
--- a/gui/ecp5/mainwindow.cc
+++ b/gui/ecp5/mainwindow.cc
@@ -40,6 +40,8 @@ void MainWindow::createMenu()
{
QMenu *menu_Custom = new QMenu("&Generic", menuBar);
menuBar->addAction(menu_Custom->menuAction());
+
+ createGraphicsBar();
}
void MainWindow::new_proj() {}
diff --git a/gui/generic/mainwindow.cc b/gui/generic/mainwindow.cc
index 88e291e6..1efc73bb 100644
--- a/gui/generic/mainwindow.cc
+++ b/gui/generic/mainwindow.cc
@@ -40,6 +40,8 @@ void MainWindow::createMenu()
{
QMenu *menu_Custom = new QMenu("&Generic", menuBar);
menuBar->addAction(menu_Custom->menuAction());
+
+ createGraphicsBar();
}
void MainWindow::new_proj() {}
diff --git a/gui/treemodel.cc b/gui/treemodel.cc
index 59391f02..d42dc401 100644
--- a/gui/treemodel.cc
+++ b/gui/treemodel.cc
@@ -141,6 +141,7 @@ void ContextTreeModel::loadData(Context *ctx)
QMap<QString, ContextTreeItem *> pip_items;
// Add pips to tree
+#ifndef ARCH_ECP5
for (auto pip : ctx->getPips()) {
auto id = ctx->getPipName(pip);
QStringList items = QString(id.c_str(ctx)).split("/");
@@ -164,6 +165,7 @@ void ContextTreeModel::loadData(Context *ctx)
parent = pip_items[name];
}
}
+#endif
pip_root->sort();
nets_root = new ContextTreeItem("Nets");
@@ -326,4 +328,19 @@ Qt::ItemFlags ContextTreeModel::flags(const QModelIndex &index) const
ContextTreeItem *node = nodeFromIndex(index);
return Qt::ItemIsEnabled | (node->type() != ElementType::NONE ? Qt::ItemIsSelectable : Qt::NoItemFlags);
}
-NEXTPNR_NAMESPACE_END \ No newline at end of file
+
+QList<QModelIndex> ContextTreeModel::search(QString text)
+{
+ QList<QModelIndex> list;
+ for (int i = 0; i < 6; i++) {
+ for (auto key : nameToItem[i].keys()) {
+ if (key.contains(text, Qt::CaseInsensitive)) {
+ list.append(indexFromNode(nameToItem[i].value(key)));
+ if (list.count() > 500)
+ break; // limit to 500 results
+ }
+ }
+ }
+ return list;
+}
+NEXTPNR_NAMESPACE_END
diff --git a/gui/treemodel.h b/gui/treemodel.h
index a85c290a..c14efa90 100644
--- a/gui/treemodel.h
+++ b/gui/treemodel.h
@@ -72,6 +72,7 @@ class ContextTreeModel : public QAbstractItemModel
ContextTreeItem *nodeFromIndex(const QModelIndex &idx) const;
QModelIndex indexFromNode(ContextTreeItem *node);
ContextTreeItem *nodeForIdType(const ElementType type, const QString name) const;
+ QList<QModelIndex> search(QString text);
// Override QAbstractItemModel methods
int rowCount(const QModelIndex &parent = QModelIndex()) const Q_DECL_OVERRIDE;
int columnCount(const QModelIndex &parent = QModelIndex()) const Q_DECL_OVERRIDE;
diff --git a/ice40/arch.cc b/ice40/arch.cc
index 107bf56a..bdfb13fe 100644
--- a/ice40/arch.cc
+++ b/ice40/arch.cc
@@ -141,18 +141,23 @@ Arch::Arch(ArchArgs args) : args(args)
#ifdef ICE40_HX1K_ONLY
if (args.type == ArchArgs::HX1K) {
+ fast_part = true;
chip_info = get_chip_info(reinterpret_cast<const RelPtr<ChipInfoPOD> *>(chipdb_blob_1k));
} else {
log_error("Unsupported iCE40 chip type.\n");
}
#else
if (args.type == ArchArgs::LP384) {
+ fast_part = false;
chip_info = get_chip_info(reinterpret_cast<const RelPtr<ChipInfoPOD> *>(chipdb_blob_384));
} else if (args.type == ArchArgs::LP1K || args.type == ArchArgs::HX1K) {
+ fast_part = args.type == ArchArgs::HX1K;
chip_info = get_chip_info(reinterpret_cast<const RelPtr<ChipInfoPOD> *>(chipdb_blob_1k));
} else if (args.type == ArchArgs::UP5K) {
+ fast_part = false;
chip_info = get_chip_info(reinterpret_cast<const RelPtr<ChipInfoPOD> *>(chipdb_blob_5k));
} else if (args.type == ArchArgs::LP8K || args.type == ArchArgs::HX8K) {
+ fast_part = args.type == ArchArgs::HX8K;
chip_info = get_chip_info(reinterpret_cast<const RelPtr<ChipInfoPOD> *>(chipdb_blob_8k));
} else {
log_error("Unsupported iCE40 chip type.\n");
@@ -199,7 +204,7 @@ Arch::Arch(ArchArgs args) : args(args)
// -----------------------------------------------------------------------
-std::string Arch::getChipName()
+std::string Arch::getChipName() const
{
#ifdef ICE40_HX1K_ONLY
if (args.type == ArchArgs::HX1K) {
@@ -306,9 +311,23 @@ PortType Arch::getBelPinType(BelId bel, PortPin pin) const
int num_bel_wires = chip_info->bel_data[bel.index].num_bel_wires;
const BelWirePOD *bel_wires = chip_info->bel_data[bel.index].bel_wires.get();
- for (int i = 0; i < num_bel_wires; i++)
- if (bel_wires[i].port == pin)
- return PortType(bel_wires[i].type);
+ if (num_bel_wires < 7) {
+ for (int i = 0; i < num_bel_wires; i++) {
+ if (bel_wires[i].port == pin)
+ return PortType(bel_wires[i].type);
+ }
+ } else {
+ int b = 0, e = num_bel_wires-1;
+ while (b <= e) {
+ int i = (b+e) / 2;
+ if (bel_wires[i].port == pin)
+ return PortType(bel_wires[i].type);
+ if (bel_wires[i].port > pin)
+ e = i-1;
+ else
+ b = i+1;
+ }
+ }
return PORT_INOUT;
}
@@ -322,10 +341,25 @@ WireId Arch::getBelPinWire(BelId bel, PortPin pin) const
int num_bel_wires = chip_info->bel_data[bel.index].num_bel_wires;
const BelWirePOD *bel_wires = chip_info->bel_data[bel.index].bel_wires.get();
- for (int i = 0; i < num_bel_wires; i++) {
- if (bel_wires[i].port == pin) {
- ret.index = bel_wires[i].wire_index;
- break;
+ if (num_bel_wires < 7) {
+ for (int i = 0; i < num_bel_wires; i++) {
+ if (bel_wires[i].port == pin) {
+ ret.index = bel_wires[i].wire_index;
+ break;
+ }
+ }
+ } else {
+ int b = 0, e = num_bel_wires-1;
+ while (b <= e) {
+ int i = (b+e) / 2;
+ if (bel_wires[i].port == pin) {
+ ret.index = bel_wires[i].wire_index;
+ break;
+ }
+ if (bel_wires[i].port > pin)
+ e = i-1;
+ else
+ b = i+1;
}
}
@@ -608,6 +642,20 @@ delay_t Arch::predictDelay(const NetInfo *net_info, const PortRef &sink) const
return xscale * abs(xd) + yscale * abs(yd) + offset;
}
+delay_t Arch::getBudgetOverride(NetInfo *net_info, int user_idx, delay_t budget) const
+{
+ const auto &driver = net_info->driver;
+ if (driver.port == id_cout) {
+ const auto &sink = net_info->users[user_idx];
+ auto driver_loc = getBelLocation(driver.cell->bel);
+ auto sink_loc = getBelLocation(sink.cell->bel);
+ if (driver_loc.y == sink_loc.y)
+ return 0;
+ return 250;
+ }
+ return budget;
+}
+
// -----------------------------------------------------------------------
bool Arch::place() { return placer1(getCtx()); }
@@ -791,29 +839,29 @@ std::vector<GraphicElement> Arch::getDecalGraphics(DecalId decal) const
// -----------------------------------------------------------------------
-bool Arch::getCellDelay(const CellInfo *cell, IdString fromPort, IdString toPort, delay_t &delay) const
+bool Arch::getCellDelay(const CellInfo *cell, IdString fromPort, IdString toPort, DelayInfo &delay) const
{
if (cell->type == id_icestorm_lc) {
if ((fromPort == id_i0 || fromPort == id_i1 || fromPort == id_i2 || fromPort == id_i3) &&
(toPort == id_o || toPort == id_lo)) {
- delay = 450;
+ delay.delay = 450;
return true;
} else if (fromPort == id_cin && toPort == id_cout) {
- delay = 120;
+ delay.delay = 120;
return true;
} else if (fromPort == id_i1 && toPort == id_cout) {
- delay = 260;
+ delay.delay = 260;
return true;
} else if (fromPort == id_i2 && toPort == id_cout) {
- delay = 230;
+ delay.delay = 230;
return true;
} else if (fromPort == id_clk && toPort == id_o) {
- delay = 540;
+ delay.delay = 540;
return true;
}
} else if (cell->type == id_icestorm_ram) {
if (fromPort == id_rclk) {
- delay = 2140;
+ delay.delay = 2140;
return true;
}
}
diff --git a/ice40/arch.h b/ice40/arch.h
index 57089ed7..92698b4d 100644
--- a/ice40/arch.h
+++ b/ice40/arch.h
@@ -44,9 +44,9 @@ template <typename T> struct RelPtr
};
NPNR_PACKED_STRUCT(struct BelWirePOD {
- int32_t wire_index;
PortPin port;
int32_t type;
+ int32_t wire_index;
});
NPNR_PACKED_STRUCT(struct BelInfoPOD {
@@ -66,7 +66,8 @@ NPNR_PACKED_STRUCT(struct BelPortPOD {
NPNR_PACKED_STRUCT(struct PipInfoPOD {
// RelPtr<char> name;
int32_t src, dst;
- int32_t delay;
+ int32_t fast_delay;
+ int32_t slow_delay;
int8_t x, y;
int16_t src_seg, dst_seg;
int16_t switch_mask;
@@ -89,6 +90,9 @@ NPNR_PACKED_STRUCT(struct WireInfoPOD {
int32_t num_segments;
RelPtr<WireSegmentPOD> segments;
+ int32_t fast_delay;
+ int32_t slow_delay;
+
int8_t x, y;
WireType type;
int8_t padding_0;
@@ -344,6 +348,7 @@ struct ArchArgs
struct Arch : BaseCtx
{
+ bool fast_part;
const ChipInfoPOD *chip_info;
const PackageInfoPOD *package_info;
@@ -360,7 +365,7 @@ struct Arch : BaseCtx
ArchArgs args;
Arch(ArchArgs args);
- std::string getChipName();
+ std::string getChipName() const;
IdString archId() const { return id("ice40"); }
IdString archArgsToId(ArchArgs args) const;
@@ -524,6 +529,11 @@ struct Arch : BaseCtx
DelayInfo getWireDelay(WireId wire) const
{
DelayInfo delay;
+ NPNR_ASSERT(wire != WireId());
+ if (fast_part)
+ delay.delay = chip_info->wire_data[wire.index].fast_delay;
+ else
+ delay.delay = chip_info->wire_data[wire.index].slow_delay;
return delay;
}
@@ -637,7 +647,10 @@ struct Arch : BaseCtx
{
DelayInfo delay;
NPNR_ASSERT(pip != PipId());
- delay.delay = chip_info->pip_data[pip.index].delay;
+ if (fast_part)
+ delay.delay = chip_info->pip_data[pip.index].fast_delay;
+ else
+ delay.delay = chip_info->pip_data[pip.index].slow_delay;
return delay;
}
@@ -689,6 +702,7 @@ struct Arch : BaseCtx
delay_t getRipupDelayPenalty() const { return 200; }
float getDelayNS(delay_t v) const { return v * 0.001; }
uint32_t getDelayChecksum(delay_t v) const { return v; }
+ delay_t getBudgetOverride(NetInfo *net_info, int user_idx, delay_t budget) const;
// -------------------------------------------------
@@ -710,7 +724,7 @@ struct Arch : BaseCtx
// Get the delay through a cell from one port to another, returning false
// if no path exists
- bool getCellDelay(const CellInfo *cell, IdString fromPort, IdString toPort, delay_t &delay) const;
+ bool getCellDelay(const CellInfo *cell, IdString fromPort, IdString toPort, DelayInfo &delay) const;
// Get the associated clock to a port, or empty if the port is combinational
IdString getPortClock(const CellInfo *cell, IdString port) const;
// Return true if a port is a clock
diff --git a/ice40/chipdb.py b/ice40/chipdb.py
index b6af8fcf..97ccbe48 100644
--- a/ice40/chipdb.py
+++ b/ice40/chipdb.py
@@ -9,6 +9,8 @@ parser = argparse.ArgumentParser(description="convert ICE40 chip database")
parser.add_argument("filename", type=str, help="chipdb input filename")
parser.add_argument("-p", "--portspins", type=str, help="path to portpins.inc")
parser.add_argument("-g", "--gfxh", type=str, help="path to gfx.h")
+parser.add_argument("--fast", type=str, help="path to timing data for fast part")
+parser.add_argument("--slow", type=str, help="path to timing data for slow part")
args = parser.parse_args()
dev_name = None
@@ -51,6 +53,9 @@ wiretypes = dict()
gfx_wire_ids = dict()
wire_segments = dict()
+fast_timings = None
+slow_timings = None
+
with open(args.portspins) as f:
for line in f:
line = line.replace("(", " ")
@@ -77,6 +82,31 @@ with open(args.gfxh) as f:
name = line.strip().rstrip(",")
gfx_wire_ids[name] = idx
+def read_timings(filename):
+ db = dict()
+ with open(filename) as f:
+ cell = None
+ for line in f:
+ line = line.split()
+ if len(line) == 0:
+ continue
+ if line[0] == "CELL":
+ cell = line[1]
+ if line[0] == "IOPATH":
+ key = "%s.%s.%s" % (cell, line[1], line[2])
+ v1 = line[3].split(":")[2]
+ v2 = line[4].split(":")[2]
+ v1 = 0 if v1 == "*" else float(v1)
+ v2 = 0 if v2 == "*" else float(v2)
+ db[key] = max(v1, v2)
+ return db
+
+if args.fast is not None:
+ fast_timings = read_timings(args.fast)
+
+if args.slow is not None:
+ slow_timings = read_timings(args.slow)
+
beltypes["ICESTORM_LC"] = 1
beltypes["ICESTORM_RAM"] = 2
beltypes["SB_IO"] = 3
@@ -184,46 +214,75 @@ def wire_type(name):
assert 0
return wt
-def pipdelay(src, dst):
- src = wire_names_r[src]
- dst = wire_names_r[dst]
+def pipdelay(src_idx, dst_idx, db):
+ if db is None:
+ return 0
+
+ src = wire_names_r[src_idx]
+ dst = wire_names_r[dst_idx]
src_type = wire_type(src[2])
dst_type = wire_type(dst[2])
- if src_type == "LOCAL" and dst_type == "LOCAL":
- return 250
+ if dst[2].startswith("sp4_") or dst[2].startswith("span4_"):
+ if src[2].startswith("sp12_") or src[2].startswith("span12_"):
+ return db["Sp12to4.I.O"]
+
+ if src[2].startswith("span4_"):
+ return db["IoSpan4Mux.I.O"]
+
+ if dst[2].startswith("sp4_h_"):
+ return db["Span4Mux_h4.I.O"]
+ else:
+ return db["Span4Mux_v4.I.O"]
+
+ if dst[2].startswith("sp12_") or dst[2].startswith("span12_"):
+ if dst[2].startswith("sp12_h_"):
+ return db["Span12Mux_h12.I.O"]
+ else:
+ return db["Span12Mux_v12.I.O"]
- if src_type == "GLOBAL" and dst_type == "LOCAL":
- return 400
+ if dst[2] in ("fabout", "clk"):
+ return 0 # FIXME?
- # Local -> Span
+ if src[2].startswith("glb_netwk_") and dst[2].startswith("glb2local_"):
+ return 0 # FIXME?
- if src_type == "LOCAL" and dst_type in ("SP4_HORZ", "SP4_VERT"):
- return 350
+ if dst[2] == "carry_in_mux":
+ return db["ICE_CARRY_IN_MUX.carryinitin.carryinitout"]
- if src_type == "LOCAL" and dst_type in ("SP12_HORZ", "SP12_VERT"):
- return 500
+ if dst[2] in ("lutff_global/clk", "io_global/inclk", "io_global/outclk", "ram/RCLK", "ram/WCLK"):
+ return db["ClkMux.I.O"]
- # Span -> Local
+ if dst[2] in ("lutff_global/s_r", "io_global/latch", "ram/RE", "ram/WE"):
+ return db["SRMux.I.O"]
- if src_type in ("SP4_HORZ", "SP4_VERT", "SP12_HORZ", "SP12_VERT") and dst_type == "LOCAL":
- return 300
+ if dst[2] in ("lutff_global/cen", "io_global/cen", "ram/RCLKE", "ram/WCLKE"):
+ return db["CEMux.I.O"]
- # Span -> Span
+ if dst[2].startswith("local_"):
+ return db["LocalMux.I.O"]
- if src_type in ("SP12_HORZ", "SP12_VERT") and dst_type in ("SP12_HORZ", "SP12_VERT"):
- return 450
+ if src[2].startswith("local_") and dst[2] in ("io_0/D_OUT_0", "io_0/D_OUT_1", "io_0/OUT_ENB", "io_1/D_OUT_0", "io_1/D_OUT_1", "io_1/OUT_ENB"):
+ return db["IoInMux.I.O"]
- if src_type in ("SP4_HORZ", "SP4_VERT") and dst_type in ("SP4_HORZ", "SP4_VERT"):
- return 300
+ if re.match(r"lutff_\d+/in_\d+", dst[2]):
+ return db["InMux.I.O"]
- if src_type in ("SP12_HORZ", "SP12_VERT") and dst_type in ("SP4_HORZ", "SP4_VERT"):
- return 380
+ if re.match(r"ram/(MASK|RADDR|WADDR|WDATA)_", dst[2]):
+ return db["InMux.I.O"]
- # print(src, dst, src_type, dst_type, file=sys.stderr)
+ print(src, dst, src_idx, dst_idx, src_type, dst_type, file=sys.stderr)
assert 0
+def wiredelay(wire_idx, db):
+ if db is None:
+ return 0
+ wire = wire_names_r[wire_idx]
+ wtype = wire_type(wire[2])
+
+ # FIXME
+ return 0
def init_tiletypes(device):
global num_tile_types, tile_sizes, tile_bits
@@ -448,13 +507,13 @@ def add_bel_input(bel, wire, port):
if wire not in wire_belports:
wire_belports[wire] = set()
wire_belports[wire].add((bel, port))
- bel_wires[bel].append((wire, port, 0))
+ bel_wires[bel].append((portpins[port], 0, wire))
def add_bel_output(bel, wire, port):
if wire not in wire_belports:
wire_belports[wire] = set()
wire_belports[wire].add((bel, port))
- bel_wires[bel].append((wire, port, 1))
+ bel_wires[bel].append((portpins[port], 1, wire))
def add_bel_lc(x, y, z):
bel = len(bel_name)
@@ -715,14 +774,12 @@ bba.post('NEXTPNR_NAMESPACE_END')
bba.push("chipdb_blob_%s" % dev_name)
bba.r("chip_info_%s" % dev_name, "chip_info")
-index = 0
for bel in range(len(bel_name)):
bba.l("bel_wires_%d" % bel, "BelWirePOD")
- for i in range(len(bel_wires[bel])):
- bba.u32(bel_wires[bel][i][0], "wire_index")
- bba.u32(portpins[bel_wires[bel][i][1]], "port")
- bba.u32(bel_wires[bel][i][2], "type")
- index += 1
+ for data in sorted(bel_wires[bel]):
+ bba.u32(data[0], "port")
+ bba.u32(data[1], "type")
+ bba.u32(data[2], "wire_index")
bba.l("bel_data_%s" % dev_name, "BelInfoPOD")
for bel in range(len(bel_name)):
@@ -748,7 +805,8 @@ for wire in range(num_wires):
pi = dict()
pi["src"] = src
pi["dst"] = wire
- pi["delay"] = pipdelay(src, wire)
+ pi["fast_delay"] = pipdelay(src, wire, fast_timings)
+ pi["slow_delay"] = pipdelay(src, wire, slow_timings)
pi["x"] = pip_xy[(src, wire)][0]
pi["y"] = pip_xy[(src, wire)][1]
pi["switch_mask"] = pip_xy[(src, wire)][2]
@@ -772,7 +830,8 @@ for wire in range(num_wires):
pi = dict()
pi["src"] = wire
pi["dst"] = dst
- pi["delay"] = pipdelay(wire, dst)
+ pi["fast_delay"] = pipdelay(wire, dst, fast_timings)
+ pi["slow_delay"] = pipdelay(wire, dst, slow_timings)
pi["x"] = pip_xy[(wire, dst)][0]
pi["y"] = pip_xy[(wire, dst)][1]
pi["switch_mask"] = pip_xy[(wire, dst)][2]
@@ -891,6 +950,9 @@ for wire, info in enumerate(wireinfo):
else:
bba.u32(0, "segments")
+ bba.u32(wiredelay(wire, fast_timings), "fast_delay")
+ bba.u32(wiredelay(wire, slow_timings), "slow_delay")
+
bba.u8(info["x"], "x")
bba.u8(info["y"], "y")
bba.u8(wiretypes[wire_type(info["name"])], "type")
@@ -923,7 +985,8 @@ for info in pipinfo:
# bba.s("X%d/Y%d/%s->%s" % (info["x"], info["y"], src_segname, dst_segname), "name")
bba.u32(info["src"], "src")
bba.u32(info["dst"], "dst")
- bba.u32(info["delay"], "delay")
+ bba.u32(info["fast_delay"], "fast_delay")
+ bba.u32(info["slow_delay"], "slow_delay")
bba.u8(info["x"], "x")
bba.u8(info["y"], "y")
bba.u16(src_seg, "src_seg")
diff --git a/ice40/family.cmake b/ice40/family.cmake
index 75061f44..02d4b4d8 100644
--- a/ice40/family.cmake
+++ b/ice40/family.cmake
@@ -14,17 +14,28 @@ file(MAKE_DIRECTORY ice40/chipdbs/)
add_library(ice40_chipdb OBJECT ice40/chipdbs/)
target_compile_definitions(ice40_chipdb PRIVATE NEXTPNR_NAMESPACE=nextpnr_${family})
target_include_directories(ice40_chipdb PRIVATE ${family}/)
+
if (MSVC)
target_sources(ice40_chipdb PRIVATE ${CMAKE_CURRENT_SOURCE_DIR}/ice40/resource/embed.cc)
set_source_files_properties(${CMAKE_CURRENT_SOURCE_DIR}/ice40/resources/chipdb.rc PROPERTIES LANGUAGE RC)
foreach (dev ${devices})
+ if (dev EQUAL "5k")
+ set(OPT_FAST "")
+ set(OPT_SLOW --slow ${ICEBOX_ROOT}/timings-up5k.txt)
+ elseif(dev EQUAL "384")
+ set(OPT_FAST "")
+ set(OPT_SLOW --slow ${ICEBOX_ROOT}/timings-lp384.txt)
+ else()
+ set(OPT_FAST --fast ${ICEBOX_ROOT}/timings-hx${dev}.txt)
+ set(OPT_SLOW --slow ${ICEBOX_ROOT}/timings-lp${dev}.txt)
+ endif()
set(DEV_TXT_DB ${ICEBOX_ROOT}/chipdb-${dev}.txt)
set(DEV_CC_BBA_DB ${CMAKE_CURRENT_SOURCE_DIR}/ice40/chipdbs/chipdb-${dev}.bba)
set(DEV_CC_DB ${CMAKE_CURRENT_SOURCE_DIR}/ice40/chipdbs/chipdb-${dev}.bin)
set(DEV_PORTS_INC ${CMAKE_CURRENT_SOURCE_DIR}/ice40/portpins.inc)
set(DEV_GFXH ${CMAKE_CURRENT_SOURCE_DIR}/ice40/gfx.h)
add_custom_command(OUTPUT ${DEV_CC_BBA_DB}
- COMMAND ${PYTHON_EXECUTABLE} ${DB_PY} -p ${DEV_PORTS_INC} -g ${DEV_GFXH} ${DEV_TXT_DB} > ${DEV_CC_BBA_DB}
+ COMMAND ${PYTHON_EXECUTABLE} ${DB_PY} -p ${DEV_PORTS_INC} -g ${DEV_GFXH} ${OPT_FAST} ${OPT_SLOW} ${DEV_TXT_DB} > ${DEV_CC_BBA_DB}
DEPENDS ${DEV_TXT_DB} ${DB_PY}
)
add_custom_command(OUTPUT ${DEV_CC_DB}
@@ -40,13 +51,23 @@ if (MSVC)
else()
target_compile_options(ice40_chipdb PRIVATE -g0 -O0 -w)
foreach (dev ${devices})
+ if (dev EQUAL "5k")
+ set(OPT_FAST "")
+ set(OPT_SLOW --slow ${ICEBOX_ROOT}/timings_up5k.txt)
+ elseif(dev EQUAL "384")
+ set(OPT_FAST "")
+ set(OPT_SLOW --slow ${ICEBOX_ROOT}/timings_lp384.txt)
+ else()
+ set(OPT_FAST --fast ${ICEBOX_ROOT}/timings_hx${dev}.txt)
+ set(OPT_SLOW --slow ${ICEBOX_ROOT}/timings_lp${dev}.txt)
+ endif()
set(DEV_TXT_DB ${ICEBOX_ROOT}/chipdb-${dev}.txt)
set(DEV_CC_BBA_DB ${CMAKE_CURRENT_SOURCE_DIR}/ice40/chipdbs/chipdb-${dev}.bba)
set(DEV_CC_DB ${CMAKE_CURRENT_SOURCE_DIR}/ice40/chipdbs/chipdb-${dev}.cc)
set(DEV_PORTS_INC ${CMAKE_CURRENT_SOURCE_DIR}/ice40/portpins.inc)
set(DEV_GFXH ${CMAKE_CURRENT_SOURCE_DIR}/ice40/gfx.h)
add_custom_command(OUTPUT ${DEV_CC_BBA_DB}
- COMMAND ${PYTHON_EXECUTABLE} ${DB_PY} -p ${DEV_PORTS_INC} -g ${DEV_GFXH} ${DEV_TXT_DB} > ${DEV_CC_BBA_DB}.new
+ COMMAND ${PYTHON_EXECUTABLE} ${DB_PY} -p ${DEV_PORTS_INC} -g ${DEV_GFXH} ${OPT_FAST} ${OPT_SLOW} ${DEV_TXT_DB} > ${DEV_CC_BBA_DB}.new
COMMAND mv ${DEV_CC_BBA_DB}.new ${DEV_CC_BBA_DB}
DEPENDS ${DEV_TXT_DB} ${DB_PY}
)
diff --git a/ice40/main.cc b/ice40/main.cc
index 32815b26..865eea9e 100644
--- a/ice40/main.cc
+++ b/ice40/main.cc
@@ -363,8 +363,12 @@ int main(int argc, char *argv[])
}
}
- if (vm.count("freq"))
+ if (vm.count("freq")) {
ctx->target_freq = vm["freq"].as<double>() * 1e6;
+ ctx->user_freq = true;
+ } else {
+ log_warning("Target frequency not specified. Will optimise for max frequency.\n");
+ }
ctx->timing_driven = true;
if (vm.count("no-tmdriv"))
diff --git a/ice40/place_legaliser.cc b/ice40/place_legaliser.cc
index 9fde179d..0d14fb35 100644
--- a/ice40/place_legaliser.cc
+++ b/ice40/place_legaliser.cc
@@ -114,17 +114,58 @@ class PlacementLegaliser
public:
PlacementLegaliser(Context *ctx) : ctx(ctx){};
+ void print_stats(const char *point)
+ {
+ float distance_sum = 0;
+ float max_distance = 0;
+ int moved_cells = 0;
+ int unplaced_cells = 0;
+ for (auto orig : originalPositions) {
+ if (ctx->cells.at(orig.first)->bel == BelId()) {
+ unplaced_cells++;
+ continue;
+ }
+ Loc newLoc = ctx->getBelLocation(ctx->cells.at(orig.first)->bel);
+ if (newLoc != orig.second) {
+ float distance = std::sqrt(std::pow(newLoc.x - orig.second.x, 2) + pow(newLoc.y - orig.second.y, 2));
+ moved_cells++;
+ distance_sum += distance;
+ if (distance > max_distance)
+ max_distance = distance;
+ }
+ }
+ log_info(" moved %d cells, %d unplaced (after %s)\n", moved_cells, unplaced_cells, point);
+ if (moved_cells > 0) {
+ log_info(" average distance %f\n", (distance_sum / moved_cells));
+ log_info(" maximum distance %f\n", max_distance);
+ }
+ }
+
bool legalise()
{
log_info("Legalising design..\n");
+ for (auto &cell : ctx->cells) {
+ CellInfo *ci = cell.second.get();
+ if (!ctx->getBelGlobalBuf(ci->bel) && cell.second->type == ctx->id("ICESTORM_LC")) {
+ originalPositions[cell.first] = ctx->getBelLocation(ci->bel);
+ }
+ }
init_logic_cells();
bool legalised_carries = legalise_carries();
if (!legalised_carries && !ctx->force)
return false;
+ print_stats("carry legalisation");
legalise_others();
+ print_stats("misc. cell legalisation");
legalise_logic_tiles();
+ print_stats("logic cell legalisation");
bool replaced_cells = replace_cells();
+ print_stats("cell replacement");
+
ctx->assignArchInfo();
+
+
+
return legalised_carries && replaced_cells;
}
@@ -501,6 +542,7 @@ class PlacementLegaliser
Context *ctx;
std::unordered_set<IdString> rippedCells;
std::unordered_set<IdString> createdCells;
+ std::unordered_map<IdString, Loc> originalPositions;
// Go from X and Y position to logic cells, setting occupied to true if a Bel is unavailable
std::vector<std::vector<std::vector<std::pair<BelId, bool>>>> logic_bels;
};
diff --git a/python/functions.py b/python/functions.py
deleted file mode 100644
index 8d2e2fb8..00000000
--- a/python/functions.py
+++ /dev/null
@@ -1,21 +0,0 @@
-def get_drivers(wire):
- wid = chip.getWireByName(wire)
- assert not wid.nil(), "wire {} not found".format(wire)
- bp = chip.getBelPinUphill(wid)
- if not bp.bel.nil():
- print("Bel pin: {}.{}".format(chip.getBelName(bp.bel), str(bp.pin)))
- for pip in sorted(chip.getPipsUphill(wid), key=lambda x: x.index):
- print("Pip: {}".format(chip.getWireName(chip.getPipSrcWire(pip))))
-
-
-def get_loads(wire):
- wid = chip.getWireByName(wire)
- assert not wid.nil(), "wire {} not found".format(wire)
- for bp in sorted(chip.getBelPinsDownhill(wid), key=lambda x: (x.bel.index, x.pin)):
- print("Bel pin: {}.{}".format(chip.getBelName(bp.bel), str(bp.pin)))
- for pip in sorted(chip.getPipsDownhill(wid), key=lambda x: x.index):
- print("Pip: {}".format(chip.getWireName(chip.getPipDstWire(pip))))
-
-
-#get_drivers("12_14_lutff_7/in_3")
-#get_loads("12_14_lutff_global/clk")
diff --git a/python/python_mod_test.py b/python/python_mod_test.py
deleted file mode 100644
index e7a8de94..00000000
--- a/python/python_mod_test.py
+++ /dev/null
@@ -1,7 +0,0 @@
-# Run: PYTHONPATH=. python3 python/python_mod_test.py
-from nextpnrpy_ice40 import Chip, ChipArgs, iCE40Type
-args = ChipArgs()
-args.type = iCE40Type.HX1K
-chip = Chip(args)
-for wire in chip.getWires():
- print(chip.getWireName(wire))
diff --git a/python/python_test.py b/python/python_test.py
deleted file mode 100644
index 31d066b2..00000000
--- a/python/python_test.py
+++ /dev/null
@@ -1,2 +0,0 @@
-for wire in chip.getWires():
- print(chip.getWireName(wire))
generated by cgit v1.2.3 (git 2.25.1) at 2024-08-21 02:27:45 +0000