diff options
| -rw-r--r-- | ice40/blinky.v | 6 | ||||
| -rw-r--r-- | ice40/chipdb.py | 23 |
2 files changed, 1 insertions, 28 deletions
diff --git a/ice40/blinky.v b/ice40/blinky.v index a52a7e25..72bcd662 100644 --- a/ice40/blinky.v +++ b/ice40/blinky.v @@ -123,11 +123,6 @@ module blinky ( .D_IN_1() ); -`ifdef ALT_BLINKY - reg ff = 0; - always @(posedge clk) ff <= !ff; - assign led1 = clki, led2 = !clki, led3 = !clk, led4 = !clk, led5 = ff; -`else localparam BITS = 5; localparam LOG2DELAY = 22; @@ -140,5 +135,4 @@ module blinky ( end assign {led1, led2, led3, led4, led5} = outcnt ^ (outcnt >> 1); -`endif endmodule diff --git a/ice40/chipdb.py b/ice40/chipdb.py index 3c3dc078..a756203a 100644 --- a/ice40/chipdb.py +++ b/ice40/chipdb.py @@ -137,7 +137,7 @@ with open(sys.argv[1], "r") as f: wire_xy[mode[1]].append((int(line[0]), int(line[1]))) continue - if mode[0] == "buffer": + if mode[0] in ("buffer", "routing"): wire_a = int(line[1]) wire_b = mode[1] if wire_a not in wire_downhill: @@ -149,27 +149,6 @@ with open(sys.argv[1], "r") as f: pip_xy[(wire_a, wire_b)] = (mode[2], mode[3], int(line[0], 2), len(switches) - 1) continue - if mode[0] == "routing": - wire_a = int(line[1]) - wire_b = mode[1] - - if wire_a not in wire_downhill: - wire_downhill[wire_a] = set() - if wire_b not in wire_uphill: - wire_uphill[wire_b] = set() - wire_downhill[wire_a].add(wire_b) - wire_uphill[wire_b].add(wire_a) - pip_xy[(wire_a, wire_b)] = (mode[2], mode[3], int(line[0], 2), len(switches) - 1) - - if wire_b not in wire_downhill: - wire_downhill[wire_b] = set() - if wire_a not in wire_uphill: - wire_uphill[wire_a] = set() - wire_downhill[wire_b].add(wire_a) - wire_uphill[wire_a].add(wire_b) - pip_xy[(wire_b, wire_a)] = (mode[2], mode[3], int(line[0], 2), len(switches) - 1) - continue - if mode[0] == "bits": name = line[0] bits = [] |