diff options
| -rw-r--r-- | common/timing.cc | 8 | ||||
| -rw-r--r-- | ice40/arch.cc | 16 |
2 files changed, 20 insertions, 4 deletions
diff --git a/common/timing.cc b/common/timing.cc index afaddbdf..f720b772 100644 --- a/common/timing.cc +++ b/common/timing.cc @@ -160,10 +160,10 @@ void assign_budget(Context *ctx) for (size_t i = 0; i < net.second->users.size(); ++i) { auto &user = net.second->users[i]; auto pi = &user.cell->ports.at(user.port); + auto budget = ctx->getNetinfoRouteDelay(net.second.get(), i); auto it = updates.find(pi); - if (it == updates.end()) - continue; - auto budget = ctx->getNetinfoRouteDelay(net.second.get(), i) - it->second; + if (it != updates.end()) + budget += it->second; user.budget = ctx->getBudgetOverride(net.second.get(), i, budget); // Post-update check @@ -196,7 +196,7 @@ void update_budget(Context *ctx) auto budget = ctx->getNetinfoRouteDelay(net.second.get(), i); auto it = updates.find(pi); if (it != updates.end()) - budget -= it->second; + budget += it->second; user.budget = ctx->getBudgetOverride(net.second.get(), i, budget); // Post-update check diff --git a/ice40/arch.cc b/ice40/arch.cc index 4e9baf7e..cfafa2d8 100644 --- a/ice40/arch.cc +++ b/ice40/arch.cc @@ -584,6 +584,22 @@ delay_t Arch::estimateDelay(WireId src, WireId dst) const // offset = 500; // } + // Estimate for output mux + for (const auto& bp : getWireBelPins(src)) { + if (bp.pin == PIN_O && getBelType(bp.bel) == TYPE_ICESTORM_LC) { + offset += 330; + break; + } + } + + // Estimate for input mux + for (const auto& bp : getWireBelPins(dst)) { + if ((bp.pin == PIN_I0 || bp.pin == PIN_I1 || bp.pin == PIN_I2 || bp.pin == PIN_I3) && getBelType(bp.bel) == TYPE_ICESTORM_LC) { + offset += 260; + break; + } + } + return xscale * abs(xd) + yscale * abs(yd) + offset; } |