diff options
| -rw-r--r-- | ecp5/gfx.cc | 31 | ||||
| -rw-r--r-- | ecp5/gfx.h | 8 | ||||
| -rwxr-xr-x | ecp5/trellis_import.py | 9 |
3 files changed, 44 insertions, 4 deletions
diff --git a/ecp5/gfx.cc b/ecp5/gfx.cc index e06bcfa6..232b93d9 100644 --- a/ecp5/gfx.cc +++ b/ecp5/gfx.cc @@ -70,8 +70,8 @@ void gfxTileWire(std::vector<GraphicElement> &g, int x, int y, int w, int h, IdS el.type = GraphicElement::TYPE_LINE; el.style = style; bool top_bottom = (y == 0 || y == (h - 1)); - int gap = 3-(tilewire - TILE_WIRE_PADDOD_PIO)/6; - int num = (tilewire - TILE_WIRE_PADDOD_PIO)%6; + int gap = 3-(tilewire - TILE_WIRE_PADDOD_PIO)/7; + int num = (tilewire - TILE_WIRE_PADDOD_PIO)%7; if (top_bottom) { el.x1 = x + io_cell_h_x1 + (gap + 2) * 0.10 + 0.0017f * (num + 1); el.x2 = el.x1; @@ -95,6 +95,33 @@ void gfxTileWire(std::vector<GraphicElement> &g, int x, int y, int w, int h, IdS } g.push_back(el); } + if (wire_type == id_WIRE_TYPE_DDRDLL) { + GraphicElement el; + el.type = GraphicElement::TYPE_LINE; + el.style = style; + int num = (tilewire - TILE_WIRE_DDRDEL_DDRDLL); + el.x1 = x + io_cell_h_x1 + 0.2 + 0.0017f * (num + 1); + el.x2 = el.x1; + if (y == h - 1) { + el.y1 = y + 0.2; + el.y2 = el.y1 - 0.015f; + } else { + el.y1 = y + 0.8; + el.y2 = el.y1 + 0.015f; + } + g.push_back(el); + } + if (wire_type == id_WIRE_TYPE_CCLK) { + GraphicElement el; + el.type = GraphicElement::TYPE_LINE; + el.style = style; + int num = (tilewire - TILE_WIRE_JPADDI_CCLK); + el.x1 = x + slice_x1 + 0.0017f * (num + 1); + el.x2 = el.x1; + el.y1 = y + slice_y2 - 1*slice_pitch; + el.y2 = el.y1 - 0.015f; + g.push_back(el); + } if (wire_type == id_WIRE_TYPE_IOLOGIC) { GraphicElement el; @@ -499,7 +499,7 @@ enum GfxTileWireId TILE_WIRE_WRPNTR0D_IOLOGIC, TILE_WIRE_WRPNTR1D_IOLOGIC, TILE_WIRE_WRPNTR2D_IOLOGIC, - TILE_WIRE_DUMMYD1_IOLOGIC, + TILE_WIRE_JSLIPD_IOLOGIC, TILE_WIRE_DUMMYD2_IOLOGIC, TILE_WIRE_DUMMYD3_IOLOGIC, TILE_WIRE_DUMMYD4_IOLOGIC, @@ -585,7 +585,7 @@ enum GfxTileWireId TILE_WIRE_WRPNTR0B_IOLOGIC, TILE_WIRE_WRPNTR1B_IOLOGIC, TILE_WIRE_WRPNTR2B_IOLOGIC, - TILE_WIRE_DUMMYB1_IOLOGIC, + TILE_WIRE_JSLIPB_IOLOGIC, TILE_WIRE_DUMMYB2_IOLOGIC, TILE_WIRE_DUMMYB3_IOLOGIC, TILE_WIRE_DUMMYB4_IOLOGIC, @@ -683,24 +683,28 @@ enum GfxTileWireId TILE_WIRE_IOLDOD_PIO, TILE_WIRE_IOLTOD_PIO, TILE_WIRE_INRDD_PIO, + TILE_WIRE_LVDSD_PIO, TILE_WIRE_PADDOC_PIO, TILE_WIRE_PADDTC_PIO, TILE_WIRE_JPADDIC_PIO, TILE_WIRE_IOLDOC_PIO, TILE_WIRE_IOLTOC_PIO, TILE_WIRE_INRDC_PIO, + TILE_WIRE_LVDSC_PIO, TILE_WIRE_PADDOB_PIO, TILE_WIRE_PADDTB_PIO, TILE_WIRE_JPADDIB_PIO, TILE_WIRE_IOLDOB_PIO, TILE_WIRE_IOLTOB_PIO, TILE_WIRE_INRDB_PIO, + TILE_WIRE_LVDSB_PIO, TILE_WIRE_PADDOA_PIO, TILE_WIRE_PADDTA_PIO, TILE_WIRE_JPADDIA_PIO, TILE_WIRE_IOLDOA_PIO, TILE_WIRE_IOLTOA_PIO, TILE_WIRE_INRDA_PIO, + TILE_WIRE_LVDSA_PIO, TILE_WIRE_JADA0_EBR, TILE_WIRE_JADB0_EBR, diff --git a/ecp5/trellis_import.py b/ecp5/trellis_import.py index 0ae8dde5..fe342263 100755 --- a/ecp5/trellis_import.py +++ b/ecp5/trellis_import.py @@ -65,6 +65,15 @@ def wire_type(name): if name[0].endswith("_DDRDLL"): return "WIRE_TYPE_DDRDLL" + if name[0].endswith("_CCLK"): + return "WIRE_TYPE_CCLK" + + if name[0].endswith("_EXTREF"): + return "WIRE_TYPE_EXTREF" + + if name[0].endswith("_DCU"): + return "WIRE_TYPE_DCU" + if name[0].endswith("_EBR"): return "WIRE_TYPE_EBR" |