12 files changed, 482 insertions, 61 deletions

diff --git a/ecp5/arch.cc b/ecp5/arch.cc
index acf1b42e..82ebfba1 100644
--- a/ecp5/arch.cc
+++ b/ecp5/arch.cc
@@ -46,7 +46,9 @@ static std::tuple<int, int, std::string> split_identifier_name(const std::string
 void IdString::initialize_arch(const BaseCtx *ctx)
 {
 #define X(t) initialize_add(ctx, #t, ID_##t);
+
 #include "constids.inc"
+
 #undef X
 }
 
@@ -92,6 +94,8 @@ Arch::Arch(ArchArgs args) : args(args)
 
     if (!package_info)
         log_error("Unsupported package '%s' for '%s'.\n", args.package.c_str(), getChipName().c_str());
+
+    bel_to_cell.resize(chip_info->height * chip_info->width * max_loc_bels, nullptr);
 }
 
 // -----------------------------------------------------------------------
@@ -367,7 +371,7 @@ BelId Arch::getBelByLocation(Loc loc) const
 
 delay_t Arch::estimateDelay(WireId src, WireId dst) const
 {
-    return 50 * (abs(src.location.x - dst.location.x) + abs(src.location.y - dst.location.y));
+    return 100 * (abs(src.location.x - dst.location.x) + abs(src.location.y - dst.location.y));
 }
 
 delay_t Arch::predictDelay(const NetInfo *net_info, const PortRef &sink) const
@@ -376,7 +380,7 @@ delay_t Arch::predictDelay(const NetInfo *net_info, const PortRef &sink) const
     auto driver_loc = getBelLocation(driver.cell->bel);
     auto sink_loc = getBelLocation(sink.cell->bel);
 
-    return 50 * (abs(driver_loc.x - sink_loc.x) + abs(driver_loc.y - sink_loc.y));
+    return 100 * (abs(driver_loc.x - sink_loc.x) + abs(driver_loc.y - sink_loc.y));
 }
 
 bool Arch::getBudgetOverride(const NetInfo *net_info, const PortRef &sink, delay_t &budget) const { return false; }
@@ -432,7 +436,7 @@ DecalXY Arch::getBelDecal(BelId bel) const
     decalxy.decal.type = DecalId::TYPE_BEL;
     decalxy.decal.location = bel.location;
     decalxy.decal.z = bel.index;
-    decalxy.decal.active = bel_to_cell.count(bel) && (bel_to_cell.at(bel) != nullptr);
+    decalxy.decal.active = (bel_to_cell.at(getBelFlatIndex(bel)) != nullptr);
     return decalxy;
 }
 
@@ -446,12 +450,122 @@ DecalXY Arch::getGroupDecal(GroupId pip) const { return {}; };
 
 bool Arch::getCellDelay(const CellInfo *cell, IdString fromPort, IdString toPort, DelayInfo &delay) const
 {
-    return false;
+    // Data for -8 grade
+    if (cell->type == id_TRELLIS_SLICE) {
+        bool has_carry = str_or_default(cell->params, id("MODE"), "LOGIC") == "CCU2";
+        if (fromPort == id_A0 || fromPort == id_B0 || fromPort == id_C0 || fromPort == id_D0) {
+            if (toPort == id_F0) {
+                delay.delay = 180;
+                return true;
+            } else if (has_carry && toPort == id_F1) {
+                delay.delay = 500;
+                return true;
+            } else if (has_carry && toPort == id_FCO) {
+                delay.delay = 355;
+                return true;
+            } else if (toPort == id_OFX0) {
+                delay.delay = 306;
+                return true;
+            }
+        }
+
+        if (fromPort == id_A1 || fromPort == id_B1 || fromPort == id_C1 || fromPort == id_D1) {
+            if (toPort == id_F1) {
+                delay.delay = 180;
+                return true;
+            } else if (has_carry && toPort == id_FCO) {
+                delay.delay = 355;
+                return true;
+            } else if (toPort == id_OFX0) {
+                delay.delay = 306;
+                return true;
+            }
+        }
+
+        if (has_carry && fromPort == id_FCI) {
+            if (toPort == id_F0) {
+                delay.delay = 328;
+                return true;
+            } else if (toPort == id_F1) {
+                delay.delay = 349;
+                return true;
+            } else if (toPort == id_FCO) {
+                delay.delay = 56;
+                return true;
+            }
+        }
+
+        if (fromPort == id_CLK && (toPort == id_Q0 || toPort == id_Q1)) {
+            delay.delay = 395;
+            return true;
+        }
+
+        if (fromPort == id_M0 && toPort == id_OFX0) {
+            delay.delay = 193;
+            return true;
+        }
+
+        if (fromPort == id_WCK && (toPort == id_F0 || toPort == id_F1)) {
+            delay.delay = 717;
+            return true;
+        }
+
+        if ((fromPort == id_A0 && toPort == id_WADO3) || (fromPort == id_A1 && toPort == id_WDO1) ||
+            (fromPort == id_B0 && toPort == id_WADO1) || (fromPort == id_B1 && toPort == id_WDO3) ||
+            (fromPort == id_C0 && toPort == id_WADO2) || (fromPort == id_C1 && toPort == id_WDO0) ||
+            (fromPort == id_D0 && toPort == id_WADO0) || (fromPort == id_D1 && toPort == id_WDO2)) {
+            delay.delay = 0;
+            return true;
+        }
+        return false;
+    } else {
+        return false;
+    }
 }
 
 TimingPortClass Arch::getPortTimingClass(const CellInfo *cell, IdString port, IdString &clockPort) const
 {
-    return TMG_IGNORE;
+    if (cell->type == id_TRELLIS_SLICE) {
+        int sd0 = int_or_default(cell->params, id("REG0_SD"), 0), sd1 = int_or_default(cell->params, id("REG1_SD"), 0);
+        if (port == id_CLK || port == id_WCK)
+            return TMG_CLOCK_INPUT;
+        if (port == id_A0 || port == id_A1 || port == id_B0 || port == id_B1 || port == id_C0 || port == id_C1 ||
+            port == id_D0 || port == id_D1 || port == id_FCI || port == id_FXA || port == id_FXB)
+            return TMG_COMB_INPUT;
+        if (port == id_F0 || port == id_F1 || port == id_FCO || port == id_OFX0 || port == id_OFX1)
+            return TMG_COMB_OUTPUT;
+        if (port == id_DI0 || port == id_DI1 || port == id_CE || port == id_LSR || (sd0 == 1 && port == id_M0) ||
+            (sd1 == 1 && port == id_M1)) {
+            clockPort = id_CLK;
+            return TMG_REGISTER_INPUT;
+        }
+        if (port == id_M0 || port == id_M1)
+            return TMG_COMB_INPUT;
+        if (port == id_Q0 || port == id_Q1) {
+            clockPort = id_CLK;
+            return TMG_REGISTER_OUTPUT;
+        }
+
+        if (port == id_WDO0 || port == id_WDO1 || port == id_WDO2 || port == id_WDO3 || port == id_WADO0 ||
+            port == id_WADO1 || port == id_WADO2 || port == id_WADO3)
+            return TMG_COMB_OUTPUT;
+
+        if (port == id_WD0 || port == id_WD1 || port == id_WAD0 || port == id_WAD1 || port == id_WAD2 ||
+            port == id_WAD3 || port == id_WRE) {
+            clockPort = id_WCK;
+            return TMG_REGISTER_INPUT;
+        }
+
+        NPNR_ASSERT_FALSE_STR("no timing type for slice port '" + port.str(this) + "'");
+    } else if (cell->type == id_TRELLIS_IO) {
+        if (port == id_T || port == id_I)
+            return TMG_ENDPOINT;
+        if (port == id_O)
+            return TMG_STARTPOINT;
+        return TMG_IGNORE;
+    } else {
+        NPNR_ASSERT_FALSE_STR("no timing data for cell type '" + cell->type.str(this) + "'");
+    }
 }
 
 std::vector<std::pair<std::string, std::string>> Arch::getTilesAtLocation(int row, int col)
diff --git a/ecp5/arch.h b/ecp5/arch.h
index f5336e55..da86d4e2 100644
--- a/ecp5/arch.h
+++ b/ecp5/arch.h
@@ -404,7 +404,7 @@ struct Arch : BaseCtx
     mutable std::unordered_map<IdString, WireId> wire_by_name;
     mutable std::unordered_map<IdString, PipId> pip_by_name;
 
-    std::unordered_map<BelId, CellInfo *> bel_to_cell;
+    std::vector<CellInfo *> bel_to_cell;
     std::unordered_map<WireId, NetInfo *> wire_to_net;
     std::unordered_map<PipId, NetInfo *> pip_to_net;
 
@@ -443,11 +443,18 @@ struct Arch : BaseCtx
 
     uint32_t getBelChecksum(BelId bel) const { return bel.index; }
 
+    const int max_loc_bels = 20;
+    int getBelFlatIndex(BelId bel) const
+    {
+        return (bel.location.y * chip_info->width + bel.location.x) * max_loc_bels + bel.index;
+    }
+
     void bindBel(BelId bel, CellInfo *cell, PlaceStrength strength)
     {
         NPNR_ASSERT(bel != BelId());
-        NPNR_ASSERT(bel_to_cell[bel] == nullptr);
-        bel_to_cell[bel] = cell;
+        int idx = getBelFlatIndex(bel);
+        NPNR_ASSERT(bel_to_cell.at(idx) == nullptr);
+        bel_to_cell[idx] = cell;
         cell->bel = bel;
         cell->belStrength = strength;
         refreshUiBel(bel);
@@ -456,10 +463,11 @@ struct Arch : BaseCtx
     void unbindBel(BelId bel)
     {
         NPNR_ASSERT(bel != BelId());
-        NPNR_ASSERT(bel_to_cell[bel] != nullptr);
-        bel_to_cell[bel]->bel = BelId();
-        bel_to_cell[bel]->belStrength = STRENGTH_NONE;
-        bel_to_cell[bel] = nullptr;
+        int idx = getBelFlatIndex(bel);
+        NPNR_ASSERT(bel_to_cell.at(idx) != nullptr);
+        bel_to_cell[idx]->bel = BelId();
+        bel_to_cell[idx]->belStrength = STRENGTH_NONE;
+        bel_to_cell[idx] = nullptr;
         refreshUiBel(bel);
     }
 
@@ -480,25 +488,19 @@ struct Arch : BaseCtx
     bool checkBelAvail(BelId bel) const
     {
         NPNR_ASSERT(bel != BelId());
-        return bel_to_cell.find(bel) == bel_to_cell.end() || bel_to_cell.at(bel) == nullptr;
+        return bel_to_cell[getBelFlatIndex(bel)] == nullptr;
     }
 
     CellInfo *getBoundBelCell(BelId bel) const
     {
         NPNR_ASSERT(bel != BelId());
-        if (bel_to_cell.find(bel) == bel_to_cell.end())
-            return nullptr;
-        else
-            return bel_to_cell.at(bel);
+        return bel_to_cell[getBelFlatIndex(bel)];
     }
 
     CellInfo *getConflictingBelCell(BelId bel) const
     {
         NPNR_ASSERT(bel != BelId());
-        if (bel_to_cell.find(bel) == bel_to_cell.end())
-            return nullptr;
-        else
-            return bel_to_cell.at(bel);
+        return bel_to_cell[getBelFlatIndex(bel)];
     }
 
     BelRange getBels() const
@@ -743,7 +745,7 @@ struct Arch : BaseCtx
     {
         DelayInfo delay;
         NPNR_ASSERT(pip != PipId());
-        delay.delay = locInfo(pip)->pip_data[pip.index].delay * 100;
+        delay.delay = locInfo(pip)->pip_data[pip.index].delay;
         return delay;
     }
 
@@ -866,6 +868,8 @@ struct Arch : BaseCtx
     // Helper function for above
     bool slicesCompatible(const std::vector<const CellInfo *> &cells) const;
 
+    void assignArchInfo();
+
     std::vector<std::pair<std::string, std::string>> getTilesAtLocation(int row, int col);
     std::string getTileByTypeAndLocation(int row, int col, std::string type) const
     {
diff --git a/ecp5/arch_place.cc b/ecp5/arch_place.cc
index 83af6b5a..55fff73d 100644
--- a/ecp5/arch_place.cc
+++ b/ecp5/arch_place.cc
@@ -35,26 +35,26 @@ bool Arch::slicesCompatible(const std::vector<const CellInfo *> &cells) const
 {
     // TODO: allow different LSR/CLK and MUX/SRMODE settings once
     // routing details are worked out
-    NetInfo *clk_sig = nullptr, *lsr_sig = nullptr;
-    std::string CLKMUX, LSRMUX, SRMODE;
+    IdString clk_sig, lsr_sig;
+    IdString CLKMUX, LSRMUX, SRMODE;
     bool first = true;
     for (auto cell : cells) {
         if (first) {
-            clk_sig = port_or_nullptr(cell, id_CLK);
-            lsr_sig = port_or_nullptr(cell, id_LSR);
-            CLKMUX = str_or_default(cell->params, id_CLKMUX, "CLK");
-            LSRMUX = str_or_default(cell->params, id_LSRMUX, "LSR");
-            SRMODE = str_or_default(cell->params, id_SRMODE, "CE_OVER_LSR");
+            clk_sig = cell->sliceInfo.clk_sig;
+            lsr_sig = cell->sliceInfo.lsr_sig;
+            CLKMUX = cell->sliceInfo.clkmux;
+            LSRMUX = cell->sliceInfo.lsrmux;
+            SRMODE = cell->sliceInfo.srmode;
         } else {
-            if (port_or_nullptr(cell, id_CLK) != clk_sig)
+            if (cell->sliceInfo.clk_sig != clk_sig)
                 return false;
-            if (port_or_nullptr(cell, id_LSR) != lsr_sig)
+            if (cell->sliceInfo.lsr_sig != lsr_sig)
                 return false;
-            if (str_or_default(cell->params, id_CLKMUX, "CLK") != CLKMUX)
+            if (cell->sliceInfo.clkmux != CLKMUX)
                 return false;
-            if (str_or_default(cell->params, id_LSRMUX, "LSR") != LSRMUX)
+            if (cell->sliceInfo.lsrmux != LSRMUX)
                 return false;
-            if (str_or_default(cell->params, id_SRMODE, "CE_OVER_LSR") != SRMODE)
+            if (cell->sliceInfo.srmode != SRMODE)
                 return false;
         }
         first = false;
diff --git a/ecp5/archdefs.h b/ecp5/archdefs.h
index 1493c691..c4e1413f 100644
--- a/ecp5/archdefs.h
+++ b/ecp5/archdefs.h
@@ -139,6 +139,10 @@ struct ArchNetInfo
 };
 struct ArchCellInfo
 {
+    struct
+    {
+        IdString clk_sig, lsr_sig, clkmux, lsrmux, srmode;
+    } sliceInfo;
 };
 
 NEXTPNR_NAMESPACE_END
diff --git a/ecp5/pack.cc b/ecp5/pack.cc
index 786f543e..a2077204 100644
--- a/ecp5/pack.cc
+++ b/ecp5/pack.cc
@@ -536,10 +536,34 @@ bool Arch::pack()
         log_break();
         Ecp5Packer(ctx).pack();
         log_info("Checksum: 0x%08x\n", ctx->checksum());
+        assignArchInfo();
         return true;
     } catch (log_execution_error_exception) {
+        assignArchInfo();
         return false;
     }
 }
 
+void Arch::assignArchInfo()
+{
+    for (auto cell : sorted(cells)) {
+        CellInfo *ci = cell.second;
+        if (ci->type == id_TRELLIS_SLICE) {
+            if (ci->ports.count(id_CLK) && ci->ports[id_CLK].net != nullptr)
+                ci->sliceInfo.clk_sig = ci->ports[id_CLK].net->name;
+            else
+                ci->sliceInfo.clk_sig = IdString();
+
+            if (ci->ports.count(id_LSR) && ci->ports[id_LSR].net != nullptr)
+                ci->sliceInfo.lsr_sig = ci->ports[id_LSR].net->name;
+            else
+                ci->sliceInfo.lsr_sig = IdString();
+
+            ci->sliceInfo.clkmux = id(str_or_default(ci->params, id_CLKMUX, "CLK"));
+            ci->sliceInfo.lsrmux = id(str_or_default(ci->params, id_LSRMUX, "LSR"));
+            ci->sliceInfo.srmode = id(str_or_default(ci->params, id_SRMODE, "LSR_OVER_CE"));
+        }
+    }
+}
+
 NEXTPNR_NAMESPACE_END
diff --git a/ecp5/trellis_import.py b/ecp5/trellis_import.py
index 7c7c9e15..de8e9958 100755
--- a/ecp5/trellis_import.py
+++ b/ecp5/trellis_import.py
@@ -130,11 +130,54 @@ def process_loc_globals(chip):
             tapdrv = chip.global_data.get_tap_driver(y, x)
             global_data[x, y] = (quadrants.index(quad), int(tapdrv.dir), tapdrv.col)
 
+def get_wire_type(name):
+    if "H00" in name or "V00" in name:
+        return "X0"
+    if "H01" in name or "V01" in name:
+        return "X1"
+    if "H02" in name or "V02" in name:
+        return "X2"
+    if "H06" in name or "V06" in name:
+        return "X6"
+    if "_SLICE" in name or "_EBR" in name:
+        return "SLICE"
+    return "LOCAL"
+
+def get_pip_delay(wire_from, wire_to):
+    # ECP5 timings WIP!!!
+    type_from = get_wire_type(wire_from)
+    type_to = get_wire_type(wire_to)
+    if type_from == "X2" and type_to == "X2":
+        return 170
+    if type_from == "SLICE" or type_to == "SLICE":
+        return 205
+    if type_from in ("LOCAL", "X0") and type_to in ("X1", "X2", "X6"):
+        return 90
+    if type_from == "X6" or type_to == "X6":
+        return 200
+    if type_from in ("X1", "X2", "X6") and type_to in ("LOCAL", "X0"):
+        return 90
+    return 100
+
+
+
 def write_database(dev_name, chip, ddrg, endianness):
     def write_loc(loc, sym_name):
         bba.u16(loc.x, "%s.x" % sym_name)
         bba.u16(loc.y, "%s.y" % sym_name)
 
+    loctypes = list([_.key() for _ in ddrg.locationTypes])
+    loc_with_type = {}
+    for y in range(0, max_row+1):
+        for x in range(0, max_col+1):
+            loc_with_type[loctypes.index(ddrg.typeAtLocation[pytrellis.Location(x, y)])] = (x, y)
+
+    def get_wire_name(arc_loctype, rel, idx):
+        loc = loc_with_type[arc_loctype]
+        lt = ddrg.typeAtLocation[pytrellis.Location(loc[0] + rel.x, loc[1] + rel.y)]
+        wire = ddrg.locationTypes[lt].wires[idx]
+        return ddrg.to_str(wire.name)
+
     bba = BinaryBlobAssembler()
     bba.pre('#include "nextpnr.h"')
     bba.pre('NEXTPNR_NAMESPACE_BEGIN')
@@ -142,7 +185,6 @@ def write_database(dev_name, chip, ddrg, endianness):
     bba.push("chipdb_blob_%s" % dev_name)
     bba.r("chip_info", "chip_info")
 
-    loctypes = list([_.key() for _ in ddrg.locationTypes])
 
     for idx in range(len(loctypes)):
         loctype = ddrg.locationTypes[loctypes[idx]]
@@ -153,7 +195,7 @@ def write_database(dev_name, chip, ddrg, endianness):
                 write_loc(arc.sinkWire.rel, "dst")
                 bba.u32(arc.srcWire.id, "src_idx")
                 bba.u32(arc.sinkWire.id, "dst_idx")
-                bba.u32(arc.delay, "delay")  # TODO:delay
+                bba.u32(get_pip_delay(get_wire_name(idx, arc.srcWire.rel, arc.srcWire.id), get_wire_name(idx, arc.sinkWire.rel, arc.sinkWire.id)), "delay")  # TODO:delay
                 bba.u16(get_tiletype_index(ddrg.to_str(arc.tiletype)), "tile_type")
                 bba.u8(int(arc.cls), "pip_type")
                 bba.u8(0, "padding")
diff --git a/gui/fpgaviewwidget.cc b/gui/fpgaviewwidget.cc
index 66739b28..84a74587 100644
--- a/gui/fpgaviewwidget.cc
+++ b/gui/fpgaviewwidget.cc
@@ -736,7 +736,7 @@ void FPGAViewWidget::zoomOut() { zoom(-10); }
 
 void FPGAViewWidget::zoomToBB(const PickQuadTree::BoundingBox &bb, float margin)
 {
-    if (bb.w() < 0.00005 && bb.h() < 0.00005)
+    if (fabs(bb.w()) < 0.00005 && fabs(bb.h()) < 0.00005)
         return;
 
     viewMove_.setToIdentity();
diff --git a/ice40/arch.cc b/ice40/arch.cc
index 91dc5d66..3983a24e 100644
--- a/ice40/arch.cc
+++ b/ice40/arch.cc
@@ -226,9 +226,12 @@ PortType Arch::getBelPinType(BelId bel, IdString pin) const
     return PORT_INOUT;
 }
 
-std::vector<std::pair<IdString, std::string>> Arch::getBelAttrs(BelId) const
+std::vector<std::pair<IdString, std::string>> Arch::getBelAttrs(BelId bel) const
 {
     std::vector<std::pair<IdString, std::string>> ret;
+
+    ret.push_back(std::make_pair(id("INDEX"), stringf("%d", bel.index)));
+
     return ret;
 }
 
@@ -342,7 +345,7 @@ std::vector<std::pair<IdString, std::string>> Arch::getWireAttrs(WireId wire) co
     std::vector<std::pair<IdString, std::string>> ret;
     auto &wi = chip_info->wire_data[wire.index];
 
-    ret.push_back(std::make_pair(id("INDEX"), stringf("%d", wi.netidx)));
+    ret.push_back(std::make_pair(id("INDEX"), stringf("%d", wire.index)));
 
     ret.push_back(std::make_pair(id("GRID_X"), stringf("%d", wi.x)));
     ret.push_back(std::make_pair(id("GRID_Y"), stringf("%d", wi.y)));
@@ -402,9 +405,12 @@ IdString Arch::getPipName(PipId pip) const
 
 IdString Arch::getPipType(PipId pip) const { return IdString(); }
 
-std::vector<std::pair<IdString, std::string>> Arch::getPipAttrs(PipId) const
+std::vector<std::pair<IdString, std::string>> Arch::getPipAttrs(PipId pip) const
 {
     std::vector<std::pair<IdString, std::string>> ret;
+
+    ret.push_back(std::make_pair(id("INDEX"), stringf("%d", pip.index)));
+
     return ret;
 }
 
@@ -723,13 +729,29 @@ std::vector<GraphicElement> Arch::getDecalGraphics(DecalId decal) const
         GraphicElement::style_t style = decal.active ? GraphicElement::STYLE_ACTIVE : GraphicElement::STYLE_INACTIVE;
 
         for (int i = 0; i < n; i++)
-            gfxTileWire(ret, p[i].x, p[i].y, GfxTileWireId(p[i].index), style);
+            gfxTileWire(ret, p[i].x, p[i].y, chip_info->width, chip_info->height, GfxTileWireId(p[i].index), style);
+
+#if 0
+        if (ret.empty()) {
+            WireId wire;
+            wire.index = decal.index;
+            log_warning("No gfx decal for wire %s (%d).\n", getWireName(wire).c_str(getCtx()), decal.index);
+        }
+#endif
     }
 
     if (decal.type == DecalId::TYPE_PIP) {
         const PipInfoPOD &p = chip_info->pip_data[decal.index];
         GraphicElement::style_t style = decal.active ? GraphicElement::STYLE_ACTIVE : GraphicElement::STYLE_HIDDEN;
         gfxTilePip(ret, p.x, p.y, GfxTileWireId(p.src_seg), GfxTileWireId(p.dst_seg), style);
+
+#if 0
+        if (ret.empty()) {
+            PipId pip;
+            pip.index = decal.index;
+            log_warning("No gfx decal for pip %s (%d).\n", getPipName(pip).c_str(getCtx()), decal.index);
+        }
+#endif
     }
 
     if (decal.type == DecalId::TYPE_BEL) {
@@ -776,6 +798,36 @@ std::vector<GraphicElement> Arch::getDecalGraphics(DecalId decal) const
                 ret.push_back(el);
             }
         }
+
+        if (bel_type == id_SB_GB) {
+            GraphicElement el;
+            el.type = GraphicElement::TYPE_BOX;
+            el.style = decal.active ? GraphicElement::STYLE_ACTIVE : GraphicElement::STYLE_INACTIVE;
+            el.x1 = chip_info->bel_data[bel.index].x + local_swbox_x1 + 0.05;
+            el.x2 = chip_info->bel_data[bel.index].x + logic_cell_x2 - 0.05;
+            el.y1 = chip_info->bel_data[bel.index].y + main_swbox_y2 - 0.05;
+            el.y2 = chip_info->bel_data[bel.index].y + main_swbox_y2 - 0.10;
+            ret.push_back(el);
+        }
+
+        if (bel_type == id_ICESTORM_PLL || bel_type == id_SB_WARMBOOT) {
+            GraphicElement el;
+            el.type = GraphicElement::TYPE_BOX;
+            el.style = decal.active ? GraphicElement::STYLE_ACTIVE : GraphicElement::STYLE_INACTIVE;
+            el.x1 = chip_info->bel_data[bel.index].x + local_swbox_x1 + 0.05;
+            el.x2 = chip_info->bel_data[bel.index].x + logic_cell_x2 - 0.05;
+            el.y1 = chip_info->bel_data[bel.index].y + main_swbox_y2;
+            el.y2 = chip_info->bel_data[bel.index].y + main_swbox_y2 + 0.05;
+            ret.push_back(el);
+        }
+
+#if 0
+        if (ret.empty()) {
+            BelId bel;
+            bel.index = decal.index;
+            log_warning("No gfx decal for bel %s (%d).\n", getBelName(bel).c_str(getCtx()), decal.index);
+        }
+#endif
     }
 
     return ret;
diff --git a/ice40/arch.h b/ice40/arch.h
index 871b25fb..37f663d9 100644
--- a/ice40/arch.h
+++ b/ice40/arch.h
@@ -108,8 +108,6 @@ NPNR_PACKED_STRUCT(struct WireInfoPOD {
     };
 
     RelPtr<char> name;
-    int32_t netidx;
-
     int32_t num_uphill, num_downhill;
     RelPtr<int32_t> pips_uphill, pips_downhill;
 
diff --git a/ice40/chipdb.py b/ice40/chipdb.py
index a28cba4a..5b2f3e57 100644
--- a/ice40/chipdb.py
+++ b/ice40/chipdb.py
@@ -727,10 +727,6 @@ def add_pip(src, dst, flags=0):
 
     pip_xy[(src, dst)] = (x, y, 0, len(switches) - 1, flags)
 
-# Add virtual padin wires
-for i in range(8):
-    add_wire(0, 0, "padin_%d" % i)
-
 def add_bel_input(bel, wire, port):
     if wire not in wire_belports:
         wire_belports[wire] = set()
@@ -1265,8 +1261,6 @@ for t in range(num_tile_types):
 bba.l("wire_data_%s" % dev_name, "WireInfoPOD")
 for wire, info in enumerate(wireinfo):
     bba.s(info["name"], "name")
-    bba.u32(wire, "netidx")
-
     bba.u32(info["num_uphill"], "num_uphill")
     bba.u32(info["num_downhill"], "num_downhill")
     bba.r(info["list_uphill"], "pips_uphill")
diff --git a/ice40/gfx.cc b/ice40/gfx.cc
index 79350ad0..74338b8d 100644
--- a/ice40/gfx.cc
+++ b/ice40/gfx.cc
@@ -21,7 +21,7 @@
 
 NEXTPNR_NAMESPACE_BEGIN
 
-void gfxTileWire(std::vector<GraphicElement> &g, int x, int y, GfxTileWireId id, GraphicElement::style_t style)
+void gfxTileWire(std::vector<GraphicElement> &g, int x, int y, int w, int h, GfxTileWireId id, GraphicElement::style_t style)
 {
     GraphicElement el;
     el.type = GraphicElement::TYPE_LINE;
@@ -411,6 +411,96 @@ void gfxTileWire(std::vector<GraphicElement> &g, int x, int y, GfxTileWireId id,
         g.push_back(el);
     }
 
+    // Horizontal IO Span-4 Wires
+
+    if (id >= TILE_WIRE_SPAN4_HORZ_R_0 && id <= TILE_WIRE_SPAN4_HORZ_L_15) {
+        int idx = id - TILE_WIRE_SPAN4_HORZ_R_0;
+
+        float y1 = y + 1.0 - (0.03 + 0.0025 * (60 - idx));
+        float y2 = y + 1.0 - (0.03 + 0.0025 * (60 - idx - 4));
+
+        el.x1 = x;
+        el.x2 = x + 0.9;
+        el.y1 = y1;
+        el.y2 = y1;
+        g.push_back(el);
+
+        if (idx <= 15) {
+            el.x1 = x + 0.9;
+            el.x2 = x + 1.0;
+            el.y1 = y1;
+            el.y2 = y2;
+            g.push_back(el);
+        }
+
+        el.x1 = x + main_swbox_x1 + 0.0025 * (idx + 35);
+        el.x2 = el.x1;
+        el.y1 = y1;
+        el.y2 = y + main_swbox_y2;
+        g.push_back(el);
+    }
+
+    // Vertical IO Span-4 Wires
+
+    if (id >= TILE_WIRE_SPAN4_VERT_B_0 && id <= TILE_WIRE_SPAN4_VERT_T_15) {
+        int idx = id - TILE_WIRE_SPAN4_VERT_B_0;
+
+        float x1 = x + 0.03 + 0.0025 * (60 - idx);
+        float x2 = x + 0.03 + 0.0025 * (60 - idx - 4);
+
+        el.y1 = y + 1.00;
+        el.y2 = y + 0.10;
+        el.x1 = x1;
+        el.x2 = x1;
+        g.push_back(el);
+
+        if (idx <= 15) {
+            el.y1 = y + 0.10;
+            el.y2 = y;
+            el.x1 = x1;
+            el.x2 = x2;
+            g.push_back(el);
+        }
+
+        if (idx <= 15 && (x == 0 || x == w-1) && y == 1) {
+            float y1 = y - (0.03 + 0.0025 * (60 - idx - 4));
+
+            el.x1 = x2;
+            el.y1 = y;
+            el.x2 = x2;
+            el.y2 = y1;
+            g.push_back(el);
+
+            el.x1 = x2;
+            el.y1 = y1;
+            el.x2 = x + (x == 0);
+            el.y2 = y1;
+            g.push_back(el);
+        }
+
+        if (idx >= 4 && (x == 0 || x == w-1) && y == h-2) {
+            float y1 = y + 2.0 - (0.03 + 0.0025 * (60 - idx));
+
+            el.x1 = x1;
+            el.y1 = y + 1.0;
+            el.x2 = x1;
+            el.y2 = y1;
+            g.push_back(el);
+
+            el.x1 = x1;
+            el.y1 = y1;
+            el.x2 = x + (x == 0);
+            el.y2 = y1;
+            g.push_back(el);
+        }
+
+        el.y1 = y + 1.0 - (0.03 + 0.0025 * (270 - idx));
+        el.y2 = el.y1;
+        el.x1 = x1;
+        el.x2 = x + main_swbox_x1;
+        g.push_back(el);
+    }
+
     // Global2Local
 
     if (id >= TILE_WIRE_GLB2LOCAL_0 && id <= TILE_WIRE_GLB2LOCAL_3) {
@@ -464,7 +554,7 @@ void gfxTileWire(std::vector<GraphicElement> &g, int x, int y, GfxTileWireId id,
         int input = idx % 4;
         el.x1 = x + local_swbox_x2;
         el.x2 = x + lut_swbox_x1;
-        el.y1 = y + (logic_cell_y1 + logic_cell_y2) / 2 - 0.0075 + (0.005 * input) + z * logic_cell_pitch;
+        el.y1 = y + (logic_cell_y1 + logic_cell_y2) / 2 + 0.0075 - (0.005 * input) + z * logic_cell_pitch;
         el.y2 = el.y1;
         g.push_back(el);
     }
@@ -475,7 +565,7 @@ void gfxTileWire(std::vector<GraphicElement> &g, int x, int y, GfxTileWireId id,
         int input = idx % 4;
         el.x1 = x + lut_swbox_x2;
         el.x2 = x + logic_cell_x1;
-        el.y1 = y + (logic_cell_y1 + logic_cell_y2) / 2 - 0.0075 + (0.005 * input) + z * logic_cell_pitch;
+        el.y1 = y + (logic_cell_y1 + logic_cell_y2) / 2 + 0.0075 - (0.005 * input) + z * logic_cell_pitch;
         el.y2 = el.y1;
         g.push_back(el);
     }
@@ -711,6 +801,22 @@ static bool getWireXY_main(GfxTileWireId id, float &x, float &y)
         return true;
     }
 
+    // IO Span-4 Wires
+
+    if (id >= TILE_WIRE_SPAN4_HORZ_R_0 && id <= TILE_WIRE_SPAN4_HORZ_L_15) {
+        int idx = id - TILE_WIRE_SPAN4_HORZ_R_0;
+        y = main_swbox_y2;
+        x = main_swbox_x1 + 0.0025 * (idx + 35);
+        return true;
+    }
+
+    if (id >= TILE_WIRE_SPAN4_VERT_B_0 && id <= TILE_WIRE_SPAN4_VERT_T_15) {
+        int idx = id - TILE_WIRE_SPAN4_VERT_B_0;
+        y = 1.0 - (0.03 + 0.0025 * (270 - idx));
+        x = main_swbox_x1;
+        return true;
+    }
+
     // Global2Local
 
     if (id >= TILE_WIRE_GLB2LOCAL_0 && id <= TILE_WIRE_GLB2LOCAL_3) {
@@ -815,22 +921,22 @@ void pipGfx(std::vector<GraphicElement> &g, int x, int y, float x1, float y1, fl
     el.style = style;
 
     if (fabsf(x1 - swx1) < 0.001 && fabsf(x2 - swx1) < 0.001) {
-        tx = x1 + 0.25 * fabsf(y1 - y2);
+        tx = swx1 + 0.25 * fabsf(y1 - y2);
         goto edge_pip;
     }
 
     if (fabsf(x1 - swx2) < 0.001 && fabsf(x2 - swx2) < 0.001) {
-        tx = x1 - 0.25 * fabsf(y1 - y2);
+        tx = swx2 - 0.25 * fabsf(y1 - y2);
         goto edge_pip;
     }
 
     if (fabsf(y1 - swy1) < 0.001 && fabsf(y2 - swy1) < 0.001) {
-        ty = y1 + 0.25 * fabsf(x1 - x2);
+        ty = swy1 + 0.25 * fabsf(x1 - x2);
         goto edge_pip;
     }
 
-    if (fabsf(y1 - swy1) < 0.001 && fabsf(y2 - swy1) < 0.001) {
-        ty = y1 + 0.25 * fabsf(x1 - x2);
+    if (fabsf(y1 - swy2) < 0.001 && fabsf(y2 - swy2) < 0.001) {
+        ty = swy2 - 0.25 * fabsf(x1 - x2);
         goto edge_pip;
     }
 
@@ -880,7 +986,7 @@ void gfxTilePip(std::vector<GraphicElement> &g, int x, int y, GfxTileWireId src,
         el.style = style;
         el.x1 = x + logic_cell_x1;
         el.x2 = x + logic_cell_x2;
-        el.y1 = y + (logic_cell_y1 + logic_cell_y2) / 2 - 0.0075 + (0.005 * in_idx) + lut_idx * logic_cell_pitch;
+        el.y1 = y + (logic_cell_y1 + logic_cell_y2) / 2 + 0.0075 - (0.005 * in_idx) + lut_idx * logic_cell_pitch;
         el.y2 = y + (logic_cell_y1 + logic_cell_y2) / 2 + lut_idx * logic_cell_pitch;
         g.push_back(el);
         return;
@@ -897,8 +1003,46 @@ void gfxTilePip(std::vector<GraphicElement> &g, int x, int y, GfxTileWireId src,
         el.style = style;
         el.x1 = x + lut_swbox_x1;
         el.x2 = x + lut_swbox_x2;
-        el.y1 = y + (logic_cell_y1 + logic_cell_y2) / 2 - 0.0075 + (0.005 * in_idx) + lut_idx * logic_cell_pitch;
-        el.y2 = y + (logic_cell_y1 + logic_cell_y2) / 2 - 0.0075 + (0.005 * out_idx) + lut_idx * logic_cell_pitch;
+        el.y1 = y + (logic_cell_y1 + logic_cell_y2) / 2 + 0.0075 - (0.005 * in_idx) + lut_idx * logic_cell_pitch;
+        el.y2 = y + (logic_cell_y1 + logic_cell_y2) / 2 + 0.0075 - (0.005 * out_idx) + lut_idx * logic_cell_pitch;
+        g.push_back(el);
+        return;
+    }
+
+    if ((src == TILE_WIRE_CARRY_IN_MUX || (src >= TILE_WIRE_LUTFF_0_COUT && src <= TILE_WIRE_LUTFF_6_COUT)) &&
+        (dst >= TILE_WIRE_LUTFF_0_IN_0 && dst <= TILE_WIRE_LUTFF_7_IN_3 && (dst - TILE_WIRE_LUTFF_0_IN_0) % 4 == 3)) {
+        int lut_idx = (dst - TILE_WIRE_LUTFF_0_IN_0) / 4;
+
+        GraphicElement el;
+        el.type = GraphicElement::TYPE_ARROW;
+        el.style = style;
+        el.x1 = x + (local_swbox_x2 + lut_swbox_x1) / 2;
+        el.x2 = el.x1;
+        el.y1 = y + (logic_cell_y1 + logic_cell_y2) / 2 + 0.0075 - (0.005 * 3) + lut_idx * logic_cell_pitch;
+        el.y2 = y + (logic_cell_y1 + logic_cell_y2 - logic_cell_pitch) / 2 + lut_idx * logic_cell_pitch;
+        g.push_back(el);
+
+        el.x1 = x + logic_cell_x1 + 0.005 * 3;
+        el.y1 = el.y2;
+        g.push_back(el);
+        return;
+    }
+
+    if ((src >= TILE_WIRE_LUTFF_0_LOUT && src <= TILE_WIRE_LUTFF_6_LOUT) &&
+        (dst >= TILE_WIRE_LUTFF_0_IN_0 && dst <= TILE_WIRE_LUTFF_7_IN_3 && (dst - TILE_WIRE_LUTFF_0_IN_0) % 4 == 2)) {
+        int lut_idx = (dst - TILE_WIRE_LUTFF_0_IN_0) / 4;
+
+        GraphicElement el;
+        el.type = GraphicElement::TYPE_ARROW;
+        el.style = style;
+        el.x1 = x + (local_swbox_x2 + lut_swbox_x1) / 2 + 0.005;
+        el.x2 = el.x1;
+        el.y1 = y + (logic_cell_y1 + logic_cell_y2) / 2 + 0.0075 - (0.005 * 2) + lut_idx * logic_cell_pitch;
+        el.y2 = y + (logic_cell_y1 + logic_cell_y2 - logic_cell_pitch) / 2 + lut_idx * logic_cell_pitch + 0.003;
+        g.push_back(el);
+
+        el.x1 = x + logic_cell_x1 + 0.005 * 5;
+        el.y1 = el.y2;
         g.push_back(el);
         return;
     }
diff --git a/ice40/gfx.h b/ice40/gfx.h
index 5401a410..4fb6e147 100644
--- a/ice40/gfx.h
+++ b/ice40/gfx.h
@@ -664,12 +664,57 @@ enum GfxTileWireId
     TILE_WIRE_SPAN12_HORZ_22,
     TILE_WIRE_SPAN12_HORZ_23,
 
+    TILE_WIRE_SPAN4_VERT_B_0,
+    TILE_WIRE_SPAN4_VERT_B_1,
+    TILE_WIRE_SPAN4_VERT_B_2,
+    TILE_WIRE_SPAN4_VERT_B_3,
+    TILE_WIRE_SPAN4_VERT_B_4,
+    TILE_WIRE_SPAN4_VERT_B_5,
+    TILE_WIRE_SPAN4_VERT_B_6,
+    TILE_WIRE_SPAN4_VERT_B_7,
+    TILE_WIRE_SPAN4_VERT_B_8,
+    TILE_WIRE_SPAN4_VERT_B_9,
+    TILE_WIRE_SPAN4_VERT_B_10,
+    TILE_WIRE_SPAN4_VERT_B_11,
+    TILE_WIRE_SPAN4_VERT_B_12,
+    TILE_WIRE_SPAN4_VERT_B_13,
+    TILE_WIRE_SPAN4_VERT_B_14,
+    TILE_WIRE_SPAN4_VERT_B_15,
+
+    TILE_WIRE_SPAN4_VERT_T_12,
+    TILE_WIRE_SPAN4_VERT_T_13,
+    TILE_WIRE_SPAN4_VERT_T_14,
+    TILE_WIRE_SPAN4_VERT_T_15,
+
+    TILE_WIRE_SPAN4_HORZ_R_0,
+    TILE_WIRE_SPAN4_HORZ_R_1,
+    TILE_WIRE_SPAN4_HORZ_R_2,
+    TILE_WIRE_SPAN4_HORZ_R_3,
+    TILE_WIRE_SPAN4_HORZ_R_4,
+    TILE_WIRE_SPAN4_HORZ_R_5,
+    TILE_WIRE_SPAN4_HORZ_R_6,
+    TILE_WIRE_SPAN4_HORZ_R_7,
+    TILE_WIRE_SPAN4_HORZ_R_8,
+    TILE_WIRE_SPAN4_HORZ_R_9,
+    TILE_WIRE_SPAN4_HORZ_R_10,
+    TILE_WIRE_SPAN4_HORZ_R_11,
+    TILE_WIRE_SPAN4_HORZ_R_12,
+    TILE_WIRE_SPAN4_HORZ_R_13,
+    TILE_WIRE_SPAN4_HORZ_R_14,
+    TILE_WIRE_SPAN4_HORZ_R_15,
+
+    TILE_WIRE_SPAN4_HORZ_L_12,
+    TILE_WIRE_SPAN4_HORZ_L_13,
+    TILE_WIRE_SPAN4_HORZ_L_14,
+    TILE_WIRE_SPAN4_HORZ_L_15,
+
     TILE_WIRE_PLLIN,
     TILE_WIRE_PLLOUT_A,
     TILE_WIRE_PLLOUT_B
 };
 
-void gfxTileWire(std::vector<GraphicElement> &g, int x, int y, GfxTileWireId id, GraphicElement::style_t style);
+void gfxTileWire(std::vector<GraphicElement> &g, int x, int y, int w, int h, GfxTileWireId id,
+                 GraphicElement::style_t style);
 void gfxTilePip(std::vector<GraphicElement> &g, int x, int y, GfxTileWireId src, GfxTileWireId dst,
                 GraphicElement::style_t style);