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-rw-r--r--common/nextpnr.cc2
-rw-r--r--common/place_common.cc6
-rw-r--r--ecp5/arch.cc8
-rw-r--r--ecp5/arch.h2
-rw-r--r--generic/arch.cc12
-rw-r--r--generic/arch.h2
-rw-r--r--ice40/arch.cc41
-rw-r--r--ice40/arch.h2
8 files changed, 31 insertions, 44 deletions
diff --git a/common/nextpnr.cc b/common/nextpnr.cc
index 5b0a45ed..4a97bd93 100644
--- a/common/nextpnr.cc
+++ b/common/nextpnr.cc
@@ -111,7 +111,7 @@ delay_t Context::getNetinfoRouteDelay(NetInfo *net_info, int user_idx) const
if (cursor == src_wire)
return delay + getWireDelay(src_wire).maxDelay();
- return predictDelay(src_wire, dst_wire);
+ return predictDelay(net_info, net_info->users[user_idx]);
}
static uint32_t xorshift32(uint32_t x)
diff --git a/common/place_common.cc b/common/place_common.cc
index 9fba90f9..2ec8d571 100644
--- a/common/place_common.cc
+++ b/common/place_common.cc
@@ -37,7 +37,6 @@ wirelen_t get_net_metric(const Context *ctx, const NetInfo *net, MetricType type
return 0;
driver_gb = ctx->getBelGlobalBuf(driver_cell->bel);
driver_loc = ctx->getBelLocation(driver_cell->bel);
- WireId drv_wire = ctx->getBelPinWire(driver_cell->bel, ctx->portPinFromId(net->driver.port));
if (driver_gb)
return 0;
delay_t worst_slack = std::numeric_limits<delay_t>::max();
@@ -49,9 +48,8 @@ wirelen_t get_net_metric(const Context *ctx, const NetInfo *net, MetricType type
if (load_cell->bel == BelId())
continue;
if (ctx->timing_driven && type == MetricType::COST) {
- WireId user_wire = ctx->getBelPinWire(load_cell->bel, ctx->portPinFromId(load.port));
- delay_t raw_wl = ctx->estimateDelay(drv_wire, user_wire);
- auto slack = load.budget - raw_wl;
+ delay_t net_delay = ctx->predictDelay(net, load);
+ auto slack = load.budget - net_delay;
if (slack < 0)
tns += slack;
worst_slack = std::min(slack, worst_slack);
diff --git a/ecp5/arch.cc b/ecp5/arch.cc
index fa36e1f8..6fa26e1a 100644
--- a/ecp5/arch.cc
+++ b/ecp5/arch.cc
@@ -413,9 +413,13 @@ delay_t Arch::estimateDelay(WireId src, WireId dst) const
return 200 * (abs(src.location.x - dst.location.x) + abs(src.location.y - dst.location.y));
}
-delay_t Arch::predictDelay(WireId src, WireId dst) const
+delay_t Arch::predictDelay(const NetInfo *net_info, const PortRef &sink) const;
{
- return 200 * (abs(src.location.x - dst.location.x) + abs(src.location.y - dst.location.y));
+ const auto& driver = net_info->driver;
+ auto driver_loc = getBelLocation(driver.cell->bel);
+ auto sink_loc = getBelLocation(sink.cell->bel);
+
+ return 200 * (abs(driver_loc.x - sink_loc.x) + abs(driver_loc.y - sink_loc.y));
}
delay_t Arch::getBudgetOverride(NetInfo *net_info, int user_idx, delay_t budget) const { return budget; }
diff --git a/ecp5/arch.h b/ecp5/arch.h
index 5e181d49..62a035aa 100644
--- a/ecp5/arch.h
+++ b/ecp5/arch.h
@@ -776,7 +776,7 @@ struct Arch : BaseCtx
// -------------------------------------------------
delay_t estimateDelay(WireId src, WireId dst) const;
- delay_t predictDelay(WireId src, WireId dst) const;
+ delay_t predictDelay(const NetInfo *net_info, const PortRef &sink) const;
delay_t getDelayEpsilon() const { return 20; }
delay_t getRipupDelayPenalty() const { return 200; }
float getDelayNS(delay_t v) const { return v * 0.001; }
diff --git a/generic/arch.cc b/generic/arch.cc
index f6c264bb..43015685 100644
--- a/generic/arch.cc
+++ b/generic/arch.cc
@@ -403,12 +403,14 @@ delay_t Arch::estimateDelay(WireId src, WireId dst) const
return (dx + dy) * grid_distance_to_delay;
}
-delay_t Arch::predictDelay(WireId src, WireId dst) const
+delay_t Arch::predictDelay(const NetInfo *net_info, const PortRef &sink) const;
{
- const WireInfo &s = wires.at(src);
- const WireInfo &d = wires.at(dst);
- int dx = abs(s.x - d.x);
- int dy = abs(s.y - d.y);
+ const auto& driver = net_info->driver;
+ auto driver_loc = getBelLocation(driver.cell->bel);
+ auto sink_loc = getBelLocation(sink.cell->bel);
+
+ int dx = abs(driver_loc.x - driver_loc.x);
+ int dy = abs(sink_loc.y - sink_locy);
return (dx + dy) * grid_distance_to_delay;
}
diff --git a/generic/arch.h b/generic/arch.h
index 4e4dd663..0c831004 100644
--- a/generic/arch.h
+++ b/generic/arch.h
@@ -194,7 +194,7 @@ struct Arch : BaseCtx
const std::vector<GroupId> &getGroupGroups(GroupId group) const;
delay_t estimateDelay(WireId src, WireId dst) const;
- delay_t predictDelay(WireId src, WireId dst) const;
+ delay_t predictDelay(const NetInfo *net_info, const PortRef &sink) const;
delay_t getDelayEpsilon() const { return 0.01; }
delay_t getRipupDelayPenalty() const { return 1.0; }
float getDelayNS(delay_t v) const { return v; }
diff --git a/ice40/arch.cc b/ice40/arch.cc
index 4b28564a..76ce6a39 100644
--- a/ice40/arch.cc
+++ b/ice40/arch.cc
@@ -587,40 +587,23 @@ delay_t Arch::estimateDelay(WireId src, WireId dst) const
return xscale * abs(xd) + yscale * abs(yd) + offset;
}
-delay_t Arch::predictDelay(WireId src, WireId dst) const
+delay_t Arch::predictDelay(const NetInfo *net_info, const PortRef &sink) const
{
- NPNR_ASSERT(src != WireId());
- int x1 = chip_info->wire_data[src.index].x;
- int y1 = chip_info->wire_data[src.index].y;
+ const auto& driver = net_info->driver;
+ auto driver_loc = getBelLocation(driver.cell->bel);
+ auto sink_loc = getBelLocation(sink.cell->bel);
- NPNR_ASSERT(dst != WireId());
- int x2 = chip_info->wire_data[dst.index].x;
- int y2 = chip_info->wire_data[dst.index].y;
+ if (driver.port == id_cout) {
+ if (driver_loc.y == sink_loc.y)
+ return 0;
+ return 250;
+ }
- int xd = x2 - x1, yd = y2 - y1;
+ int xd = sink_loc.x - driver_loc.x, yd = sink_loc.y - driver_loc.y;
int xscale = 120, yscale = 120, offset = 0;
- // if (chip_info->wire_data[src.index].type == WIRE_TYPE_SP4_VERT) {
- // yd = yd < -4 ? yd + 4 : (yd < 0 ? 0 : yd);
- // offset = 500;
- // }
-
- // Estimate for output mux
- for (const auto &bp : getWireBelPins(src)) {
- if (bp.pin == PIN_O && getBelType(bp.bel) == TYPE_ICESTORM_LC) {
- offset += 330;
- break;
- }
- }
-
- // Estimate for input mux
- for (const auto &bp : getWireBelPins(dst)) {
- if ((bp.pin == PIN_I0 || bp.pin == PIN_I1 || bp.pin == PIN_I2 || bp.pin == PIN_I3) &&
- getBelType(bp.bel) == TYPE_ICESTORM_LC) {
- offset += 260;
- break;
- }
- }
+ if (driver.port == id_o) offset += 330;
+ if (sink.port == id_i0 || sink.port == id_i1 || sink.port == id_i2 || sink.port == id_i3) offset += 260;
return xscale * abs(xd) + yscale * abs(yd) + offset;
}
diff --git a/ice40/arch.h b/ice40/arch.h
index c2768efe..a4d148e5 100644
--- a/ice40/arch.h
+++ b/ice40/arch.h
@@ -697,7 +697,7 @@ struct Arch : BaseCtx
// -------------------------------------------------
delay_t estimateDelay(WireId src, WireId dst) const;
- delay_t predictDelay(WireId src, WireId dst) const;
+ delay_t predictDelay(const NetInfo *net_info, const PortRef &sink) const;
delay_t getDelayEpsilon() const { return 20; }
delay_t getRipupDelayPenalty() const { return 200; }
float getDelayNS(delay_t v) const { return v * 0.001; }
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-15 15:25:44 +0000