diff options
| -rw-r--r-- | mistral/bitstream.cc | 10 | ||||
| -rw-r--r-- | mistral/globals.cc | 1 |
2 files changed, 10 insertions, 1 deletions
diff --git a/mistral/bitstream.cc b/mistral/bitstream.cc index 7885f959..6921bbb5 100644 --- a/mistral/bitstream.cc +++ b/mistral/bitstream.cc @@ -189,7 +189,7 @@ struct MistralBitgen { (void)ci; // currently unused auto pos = CycloneV::xy2pos(x, y); - cv->bmux_n_set(CycloneV::CMUXHG, pos, CycloneV::INPUT_SELECT, bi, 0x1b); // hardcode to general routing + cv->bmux_r_set(CycloneV::CMUXHG, pos, CycloneV::INPUT_SELECT, bi, 0x1b); // hardcode to general routing cv->bmux_m_set(CycloneV::CMUXHG, pos, CycloneV::TESTSYN_ENOUT_SELECT, bi, CycloneV::PRE_SYNENB); } @@ -245,8 +245,10 @@ struct MistralBitgen if (is_carry && alm == 5) cv->bmux_b_set(CycloneV::LAB, pos, CycloneV::BTO_DIS, alm, true); // Flipflop configuration + const std::array<CycloneV::bmux_type_t, 2> ef_sel{CycloneV::TEF_SEL, CycloneV::BEF_SEL}; const std::array<CycloneV::bmux_type_t, 4> pkreg{CycloneV::TPKREG0, CycloneV::TPKREG1, CycloneV::BPKREG0, CycloneV::BPKREG1}; + const std::array<CycloneV::bmux_type_t, 2> clk_sel{CycloneV::TCLK_SEL, CycloneV::BCLK_SEL}, clr_sel{CycloneV::TCLR_SEL, CycloneV::BCLR_SEL}, sclr_dis{CycloneV::TSCLR_DIS, CycloneV::BSCLR_DIS}, sload_en{CycloneV::TSLOAD_EN, CycloneV::BSLOAD_EN}; @@ -258,6 +260,12 @@ struct MistralBitgen en_ninv{CycloneV::EN0_NINV, CycloneV::EN1_NINV, CycloneV::EN2_NINV}; const std::array<CycloneV::bmux_type_t, 2> aclr_inv{CycloneV::ACLR0_INV, CycloneV::ACLR1_INV}; + for (int i = 0; i < 2; i++) { + // EF selection mux + if (ctx->wires_connected(ctx->getBelPinWire(alm_data.lut_bels[i], i ? id_F1 : id_F0), alm_data.sel_ef[i])) + cv->bmux_m_set(CycloneV::LAB, pos, ef_sel[i], alm, CycloneV::bmux_type_t::F); + } + for (int i = 0; i < 4; i++) { CellInfo *ff = ffs[i]; if (!ff) diff --git a/mistral/globals.cc b/mistral/globals.cc index 2d1b2ef8..eee8d0a9 100644 --- a/mistral/globals.cc +++ b/mistral/globals.cc @@ -32,6 +32,7 @@ void Arch::create_clkbuf(int x, int y) add_bel_pin(bel, id_A, PORT_IN, get_port(CycloneV::CMUXHG, x, y, -1, CycloneV::CLKIN, z)); add_bel_pin(bel, id_Q, PORT_OUT, get_port(CycloneV::CMUXHG, x, y, z, CycloneV::CLKOUT)); // TODO: enable pin + bel_data(bel).block_index = z; } } |