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-rw-r--r--common/bits.cc14
-rw-r--r--common/bits.h13
-rw-r--r--common/nextpnr.h4
-rw-r--r--docs/archapi.md6
-rw-r--r--fpga_interchange/arch.h2
-rw-r--r--generic/arch.cc2
-rw-r--r--generic/arch.h2
-rw-r--r--gowin/arch.cc2
-rw-r--r--gowin/arch.h2
9 files changed, 26 insertions, 21 deletions
diff --git a/common/bits.cc b/common/bits.cc
index 1fe65544..36c7539a 100644
--- a/common/bits.cc
+++ b/common/bits.cc
@@ -24,7 +24,8 @@
namespace nextpnr {
-int Bits::generic_popcount(unsigned int v) {
+int Bits::generic_popcount(unsigned int v)
+{
unsigned int c; // c accumulates the total bits set in v
for (c = 0; v; c++) {
v &= v - 1; // clear the least significant bit set
@@ -33,13 +34,14 @@ int Bits::generic_popcount(unsigned int v) {
return c;
}
-int Bits::generic_ctz(unsigned int x) {
- if(x == 0) {
+int Bits::generic_ctz(unsigned int x)
+{
+ if (x == 0) {
throw std::runtime_error("Cannot call ctz with arg = 0");
}
- for(size_t i = 0; i < std::numeric_limits<unsigned int>::digits; ++i) {
- if((x & (1 << i)) != 0) {
+ for (size_t i = 0; i < std::numeric_limits<unsigned int>::digits; ++i) {
+ if ((x & (1 << i)) != 0) {
return i;
}
}
@@ -48,4 +50,4 @@ int Bits::generic_ctz(unsigned int x) {
throw std::runtime_error("Unreachable!");
}
-};
+}; // namespace nextpnr
diff --git a/common/bits.h b/common/bits.h
index 1abf6735..d1598a8e 100644
--- a/common/bits.h
+++ b/common/bits.h
@@ -34,18 +34,20 @@
#if defined(_MSC_VER) && (defined(_M_X64) || defined(_M_IX86))
#include <intrin.h>
-#pragma intrinsic(_BitScanForward,_BitScanReverse,__popcnt)
+#pragma intrinsic(_BitScanForward, _BitScanReverse, __popcnt)
#endif
// Uses plain nextpnr namespace to avoid header inclusion nightmare that is
// "nextpnr.h".
namespace nextpnr {
-struct Bits {
+struct Bits
+{
static int generic_popcount(unsigned int x);
static int generic_ctz(unsigned int x);
- static int popcount(unsigned int x) {
+ static int popcount(unsigned int x)
+ {
#if defined(__GNUC__) || defined(__clang__)
return __builtin_popcount(x);
#elif defined(_MSC_VER) && (defined(_M_X64) || defined(_M_IX86))
@@ -55,7 +57,8 @@ struct Bits {
#endif
}
- static int ctz(unsigned int x) {
+ static int ctz(unsigned int x)
+ {
#if defined(__GNUC__) || defined(__clang__)
return __builtin_ctz(x);
#elif defined(_MSC_VER) && (defined(_M_X64) || defined(_M_IX86))
@@ -68,6 +71,6 @@ struct Bits {
}
};
-};
+}; // namespace nextpnr
#endif /* BITS_H */
diff --git a/common/nextpnr.h b/common/nextpnr.h
index ed227fb6..59198d6d 100644
--- a/common/nextpnr.h
+++ b/common/nextpnr.h
@@ -1146,7 +1146,7 @@ template <typename R> struct ArchAPI : BaseCtx
virtual WireId getBelPinWire(BelId bel, IdString pin) const = 0;
virtual PortType getBelPinType(BelId bel, IdString pin) const = 0;
virtual typename R::BelPinsRangeT getBelPins(BelId bel) const = 0;
- virtual typename R::CellBelPinRangeT getBelPinsForCellPin(CellInfo *cell_info, IdString pin) const = 0;
+ virtual typename R::CellBelPinRangeT getBelPinsForCellPin(const CellInfo *cell_info, IdString pin) const = 0;
// Wire methods
virtual typename R::AllWiresRangeT getWires() const = 0;
virtual WireId getWireByName(IdStringList name) const = 0;
@@ -1298,7 +1298,7 @@ template <typename R> struct BaseArch : ArchAPI<R>
return empty_if_possible<typename R::BelAttrsRangeT>();
}
- virtual typename R::CellBelPinRangeT getBelPinsForCellPin(CellInfo *cell_info, IdString pin) const override
+ virtual typename R::CellBelPinRangeT getBelPinsForCellPin(const CellInfo *cell_info, IdString pin) const override
{
return return_if_match<std::array<IdString, 1>, typename R::CellBelPinRangeT>({pin});
}
diff --git a/docs/archapi.md b/docs/archapi.md
index 9ecb1bf1..3131ae64 100644
--- a/docs/archapi.md
+++ b/docs/archapi.md
@@ -236,7 +236,7 @@ Return the type (input/output/inout) of the given bel pin.
Return a list of all pins on that bel.
-### CellBelPinRangeT getBelPinsForCellPin(CellInfo *cell_info, IdString pin) const
+### CellBelPinRangeT getBelPinsForCellPin(const CellInfo *cell_info, IdString pin) const
Return the list of bel pin names that a given cell pin should be routed to. In most cases there will be a single bel pin for each cell pin; and output pins must _always_ have only one bel pin associated with them.
@@ -662,9 +662,9 @@ Return the BelBucketId for the specified bucket name.
Returns the bucket for a particular bel.
-*BaseArch default: `getBelBucketForCellType(getCellType(bel))`*
+*BaseArch default: `getBelBucketForCellType(getBelType(bel))`*
-### BelBucketId getBelBucketForCell(IdString cell\_type) const
+### BelBucketId getBelBucketForCellType(IdString cell\_type) const
Returns the bel bucket for a particular cell type.
diff --git a/fpga_interchange/arch.h b/fpga_interchange/arch.h
index 82a2788b..1118a96b 100644
--- a/fpga_interchange/arch.h
+++ b/fpga_interchange/arch.h
@@ -1033,7 +1033,7 @@ struct Arch : ArchAPI<ArchRanges>
return str_range;
}
- const std::vector<IdString> &getBelPinsForCellPin(CellInfo *cell_info, IdString pin) const override
+ const std::vector<IdString> &getBelPinsForCellPin(const CellInfo *cell_info, IdString pin) const override
{
return cell_info->cell_bel_pins.at(pin);
}
diff --git a/generic/arch.cc b/generic/arch.cc
index 03d8c801..1f9531c7 100644
--- a/generic/arch.cc
+++ b/generic/arch.cc
@@ -347,7 +347,7 @@ std::vector<IdString> Arch::getBelPins(BelId bel) const
return ret;
}
-const std::vector<IdString> &Arch::getBelPinsForCellPin(CellInfo *cell_info, IdString pin) const
+const std::vector<IdString> &Arch::getBelPinsForCellPin(const CellInfo *cell_info, IdString pin) const
{
return cell_info->bel_pins.at(pin);
}
diff --git a/generic/arch.h b/generic/arch.h
index 8a5b27e0..cc8de484 100644
--- a/generic/arch.h
+++ b/generic/arch.h
@@ -247,7 +247,7 @@ struct Arch : ArchAPI<ArchRanges>
WireId getBelPinWire(BelId bel, IdString pin) const override;
PortType getBelPinType(BelId bel, IdString pin) const override;
std::vector<IdString> getBelPins(BelId bel) const override;
- const std::vector<IdString> &getBelPinsForCellPin(CellInfo *cell_info, IdString pin) const override;
+ const std::vector<IdString> &getBelPinsForCellPin(const CellInfo *cell_info, IdString pin) const override;
WireId getWireByName(IdStringList name) const override;
IdStringList getWireName(WireId wire) const override;
diff --git a/gowin/arch.cc b/gowin/arch.cc
index d1fbd0ed..7e947341 100644
--- a/gowin/arch.cc
+++ b/gowin/arch.cc
@@ -824,7 +824,7 @@ std::vector<IdString> Arch::getBelPins(BelId bel) const
return ret;
}
-std::array<IdString, 1> Arch::getBelPinsForCellPin(CellInfo *cell_info, IdString pin) const { return {pin}; }
+std::array<IdString, 1> Arch::getBelPinsForCellPin(const CellInfo *cell_info, IdString pin) const { return {pin}; }
// ---------------------------------------------------------------
diff --git a/gowin/arch.h b/gowin/arch.h
index 0b0d7b9c..052c1545 100644
--- a/gowin/arch.h
+++ b/gowin/arch.h
@@ -372,7 +372,7 @@ struct Arch : BaseArch<ArchRanges>
WireId getBelPinWire(BelId bel, IdString pin) const override;
PortType getBelPinType(BelId bel, IdString pin) const override;
std::vector<IdString> getBelPins(BelId bel) const override;
- std::array<IdString, 1> getBelPinsForCellPin(CellInfo *cell_info, IdString pin) const override;
+ std::array<IdString, 1> getBelPinsForCellPin(const CellInfo *cell_info, IdString pin) const override;
WireId getWireByName(IdStringList name) const override;
IdStringList getWireName(WireId wire) const override;
generated by cgit v1.2.3 (git 2.25.1) at 2025-04-15 23:41:11 +0000