diff options
Diffstat (limited to 'common/timing.cc')
| -rw-r--r-- | common/timing.cc | 21 |
1 files changed, 12 insertions, 9 deletions
diff --git a/common/timing.cc b/common/timing.cc index 161769dc..ce293f34 100644 --- a/common/timing.cc +++ b/common/timing.cc @@ -275,12 +275,13 @@ void TimingAnalyser::setup_port_domains() if (launch_data.key.clock != capture_data.key.clock) continue; IdString clk = launch_data.key.clock; - if (!ctx->nets.count(clk)) - continue; - NetInfo *clk_net = ctx->nets.at(clk).get(); - if (!clk_net->clkconstr) - continue; - delay_t period = clk_net->clkconstr->period.minDelay(); + delay_t period = ctx->getDelayFromNS(1.0e9 / ctx->setting<float>("target_freq")); + if (ctx->nets.count(clk)) { + NetInfo *clk_net = ctx->nets.at(clk).get(); + if (clk_net->clkconstr) { + period = clk_net->clkconstr->period.minDelay(); + } + } if (launch_data.key.edge != capture_data.key.edge) period /= 2; dp.period = DelayPair(period); @@ -426,15 +427,17 @@ void TimingAnalyser::walk_backward() // Input port: propagate delay back through net, subtracting route delay NetInfo *net = port_info(p).net; if (net != nullptr && net->driver.cell != nullptr) - set_required_time(CellPortKey(net->driver), req.first, req.second.value - pd.route_delay, - req.second.path_length, p); + set_required_time(CellPortKey(net->driver), req.first, + req.second.value - DelayPair(pd.route_delay.maxDelay()), req.second.path_length, + p); } else if (pd.type == PORT_OUT) { // Output port : propagate delay back through cell, subtracting combinational delay for (auto &fanin : pd.cell_arcs) { if (fanin.type != CellArc::COMBINATIONAL) continue; set_required_time(CellPortKey(p.cell, fanin.other_port), req.first, - req.second.value - fanin.value.delayPair(), req.second.path_length + 1, p); + req.second.value - DelayPair(fanin.value.maxDelay()), req.second.path_length + 1, + p); } } } |