diff options
Diffstat (limited to 'ecp5/cells.cc')
| -rw-r--r-- | ecp5/cells.cc | 487 |
1 files changed, 240 insertions, 247 deletions
diff --git a/ecp5/cells.cc b/ecp5/cells.cc index b0ae2065..a5d484ff 100644 --- a/ecp5/cells.cc +++ b/ecp5/cells.cc @@ -25,22 +25,12 @@ NEXTPNR_NAMESPACE_BEGIN -void add_port(const Context *ctx, CellInfo *cell, std::string name, PortType dir) -{ - IdString id = ctx->id(name); - cell->ports[id] = PortInfo{id, nullptr, dir}; -} - std::unique_ptr<CellInfo> create_ecp5_cell(Context *ctx, IdString type, std::string name) { static int auto_idx = 0; - std::unique_ptr<CellInfo> new_cell = std::unique_ptr<CellInfo>(new CellInfo()); - if (name.empty()) { - new_cell->name = ctx->id("$nextpnr_" + type.str(ctx) + "_" + std::to_string(auto_idx++)); - } else { - new_cell->name = ctx->id(name); - } - new_cell->type = type; + IdString name_id = + name.empty() ? ctx->id("$nextpnr_" + type.str(ctx) + "_" + std::to_string(auto_idx++)) : ctx->id(name); + std::unique_ptr<CellInfo> new_cell = std::make_unique<CellInfo>(ctx, name_id, type); auto copy_bel_ports = [&]() { // First find a Bel of the target type @@ -53,133 +43,133 @@ std::unique_ptr<CellInfo> create_ecp5_cell(Context *ctx, IdString type, std::str } NPNR_ASSERT(tgt != BelId()); for (auto port : ctx->getBelPins(tgt)) { - add_port(ctx, new_cell.get(), port.str(ctx), ctx->getBelPinType(tgt, port)); + new_cell->ports[port] = PortInfo{port, nullptr, ctx->getBelPinType(tgt, port)}; } }; - if (type == ctx->id("TRELLIS_SLICE")) { - new_cell->params[ctx->id("MODE")] = std::string("LOGIC"); - new_cell->params[ctx->id("GSR")] = std::string("DISABLED"); - new_cell->params[ctx->id("SRMODE")] = std::string("LSR_OVER_CE"); - new_cell->params[ctx->id("CEMUX")] = std::string("1"); - new_cell->params[ctx->id("CLKMUX")] = std::string("CLK"); - new_cell->params[ctx->id("LSRMUX")] = std::string("LSR"); - new_cell->params[ctx->id("LUT0_INITVAL")] = Property(0, 16); - new_cell->params[ctx->id("LUT1_INITVAL")] = Property(0, 16); - new_cell->params[ctx->id("REG0_SD")] = std::string("0"); - new_cell->params[ctx->id("REG1_SD")] = std::string("0"); - new_cell->params[ctx->id("REG0_REGSET")] = std::string("RESET"); - new_cell->params[ctx->id("REG1_REGSET")] = std::string("RESET"); - new_cell->params[ctx->id("CCU2_INJECT1_0")] = std::string("NO"); - new_cell->params[ctx->id("CCU2_INJECT1_1")] = std::string("NO"); - new_cell->params[ctx->id("WREMUX")] = std::string("WRE"); - - add_port(ctx, new_cell.get(), "A0", PORT_IN); - add_port(ctx, new_cell.get(), "B0", PORT_IN); - add_port(ctx, new_cell.get(), "C0", PORT_IN); - add_port(ctx, new_cell.get(), "D0", PORT_IN); - - add_port(ctx, new_cell.get(), "A1", PORT_IN); - add_port(ctx, new_cell.get(), "B1", PORT_IN); - add_port(ctx, new_cell.get(), "C1", PORT_IN); - add_port(ctx, new_cell.get(), "D1", PORT_IN); - - add_port(ctx, new_cell.get(), "M0", PORT_IN); - add_port(ctx, new_cell.get(), "M1", PORT_IN); - - add_port(ctx, new_cell.get(), "FCI", PORT_IN); - add_port(ctx, new_cell.get(), "FXA", PORT_IN); - add_port(ctx, new_cell.get(), "FXB", PORT_IN); - - add_port(ctx, new_cell.get(), "CLK", PORT_IN); - add_port(ctx, new_cell.get(), "LSR", PORT_IN); - add_port(ctx, new_cell.get(), "CE", PORT_IN); - - add_port(ctx, new_cell.get(), "DI0", PORT_IN); - add_port(ctx, new_cell.get(), "DI1", PORT_IN); - - add_port(ctx, new_cell.get(), "WD0", PORT_IN); - add_port(ctx, new_cell.get(), "WD1", PORT_IN); - add_port(ctx, new_cell.get(), "WAD0", PORT_IN); - add_port(ctx, new_cell.get(), "WAD1", PORT_IN); - add_port(ctx, new_cell.get(), "WAD2", PORT_IN); - add_port(ctx, new_cell.get(), "WAD3", PORT_IN); - add_port(ctx, new_cell.get(), "WRE", PORT_IN); - add_port(ctx, new_cell.get(), "WCK", PORT_IN); - - add_port(ctx, new_cell.get(), "F0", PORT_OUT); - add_port(ctx, new_cell.get(), "Q0", PORT_OUT); - add_port(ctx, new_cell.get(), "F1", PORT_OUT); - add_port(ctx, new_cell.get(), "Q1", PORT_OUT); - - add_port(ctx, new_cell.get(), "FCO", PORT_OUT); - add_port(ctx, new_cell.get(), "OFX0", PORT_OUT); - add_port(ctx, new_cell.get(), "OFX1", PORT_OUT); - - add_port(ctx, new_cell.get(), "WDO0", PORT_OUT); - add_port(ctx, new_cell.get(), "WDO1", PORT_OUT); - add_port(ctx, new_cell.get(), "WDO2", PORT_OUT); - add_port(ctx, new_cell.get(), "WDO3", PORT_OUT); - add_port(ctx, new_cell.get(), "WADO0", PORT_OUT); - add_port(ctx, new_cell.get(), "WADO1", PORT_OUT); - add_port(ctx, new_cell.get(), "WADO2", PORT_OUT); - add_port(ctx, new_cell.get(), "WADO3", PORT_OUT); - } else if (type == ctx->id("TRELLIS_IO")) { - new_cell->params[ctx->id("DIR")] = std::string("INPUT"); - new_cell->attrs[ctx->id("IO_TYPE")] = std::string("LVCMOS33"); - new_cell->params[ctx->id("DATAMUX_ODDR")] = std::string("PADDO"); - new_cell->params[ctx->id("DATAMUX_MDDR")] = std::string("PADDO"); - - add_port(ctx, new_cell.get(), "B", PORT_INOUT); - add_port(ctx, new_cell.get(), "I", PORT_IN); - add_port(ctx, new_cell.get(), "T", PORT_IN); - add_port(ctx, new_cell.get(), "O", PORT_OUT); - - add_port(ctx, new_cell.get(), "IOLDO", PORT_IN); - add_port(ctx, new_cell.get(), "IOLTO", PORT_IN); - - } else if (type == ctx->id("LUT4")) { - new_cell->params[ctx->id("INIT")] = Property(0, 16); - - add_port(ctx, new_cell.get(), "A", PORT_IN); - add_port(ctx, new_cell.get(), "B", PORT_IN); - add_port(ctx, new_cell.get(), "C", PORT_IN); - add_port(ctx, new_cell.get(), "D", PORT_IN); - add_port(ctx, new_cell.get(), "Z", PORT_OUT); - } else if (type == ctx->id("CCU2C")) { - new_cell->params[ctx->id("INIT0")] = Property(0, 16); - new_cell->params[ctx->id("INIT1")] = Property(0, 16); - new_cell->params[ctx->id("INJECT1_0")] = std::string("YES"); - new_cell->params[ctx->id("INJECT1_1")] = std::string("YES"); - - add_port(ctx, new_cell.get(), "CIN", PORT_IN); - - add_port(ctx, new_cell.get(), "A0", PORT_IN); - add_port(ctx, new_cell.get(), "B0", PORT_IN); - add_port(ctx, new_cell.get(), "C0", PORT_IN); - add_port(ctx, new_cell.get(), "D0", PORT_IN); - - add_port(ctx, new_cell.get(), "A1", PORT_IN); - add_port(ctx, new_cell.get(), "B1", PORT_IN); - add_port(ctx, new_cell.get(), "C1", PORT_IN); - add_port(ctx, new_cell.get(), "D1", PORT_IN); - - add_port(ctx, new_cell.get(), "S0", PORT_OUT); - add_port(ctx, new_cell.get(), "S1", PORT_OUT); - add_port(ctx, new_cell.get(), "COUT", PORT_OUT); - - } else if (type == ctx->id("DCCA")) { - add_port(ctx, new_cell.get(), "CLKI", PORT_IN); - add_port(ctx, new_cell.get(), "CLKO", PORT_OUT); - add_port(ctx, new_cell.get(), "CE", PORT_IN); + if (type == id_TRELLIS_SLICE) { + new_cell->params[id_MODE] = std::string("LOGIC"); + new_cell->params[id_GSR] = std::string("DISABLED"); + new_cell->params[id_SRMODE] = std::string("LSR_OVER_CE"); + new_cell->params[id_CEMUX] = std::string("1"); + new_cell->params[id_CLKMUX] = std::string("CLK"); + new_cell->params[id_LSRMUX] = std::string("LSR"); + new_cell->params[id_LUT0_INITVAL] = Property(0, 16); + new_cell->params[id_LUT1_INITVAL] = Property(0, 16); + new_cell->params[id_REG0_SD] = std::string("0"); + new_cell->params[id_REG1_SD] = std::string("0"); + new_cell->params[id_REG0_REGSET] = std::string("RESET"); + new_cell->params[id_REG1_REGSET] = std::string("RESET"); + new_cell->params[id_CCU2_INJECT1_0] = std::string("NO"); + new_cell->params[id_CCU2_INJECT1_1] = std::string("NO"); + new_cell->params[id_WREMUX] = std::string("WRE"); + + new_cell->addInput(id_A0); + new_cell->addInput(id_B0); + new_cell->addInput(id_C0); + new_cell->addInput(id_D0); + + new_cell->addInput(id_A1); + new_cell->addInput(id_B1); + new_cell->addInput(id_C1); + new_cell->addInput(id_D1); + + new_cell->addInput(id_M0); + new_cell->addInput(id_M1); + + new_cell->addInput(id_FCI); + new_cell->addInput(id_FXA); + new_cell->addInput(id_FXB); + + new_cell->addInput(id_CLK); + new_cell->addInput(id_LSR); + new_cell->addInput(id_CE); + + new_cell->addInput(id_DI0); + new_cell->addInput(id_DI1); + + new_cell->addInput(id_WD0); + new_cell->addInput(id_WD1); + new_cell->addInput(id_WAD0); + new_cell->addInput(id_WAD1); + new_cell->addInput(id_WAD2); + new_cell->addInput(id_WAD3); + new_cell->addInput(id_WRE); + new_cell->addInput(id_WCK); + + new_cell->addOutput(id_F0); + new_cell->addOutput(id_Q0); + new_cell->addOutput(id_F1); + new_cell->addOutput(id_Q1); + + new_cell->addOutput(id_FCO); + new_cell->addOutput(id_OFX0); + new_cell->addOutput(id_OFX1); + + new_cell->addOutput(id_WDO0); + new_cell->addOutput(id_WDO1); + new_cell->addOutput(id_WDO2); + new_cell->addOutput(id_WDO3); + new_cell->addOutput(id_WADO0); + new_cell->addOutput(id_WADO1); + new_cell->addOutput(id_WADO2); + new_cell->addOutput(id_WADO3); + } else if (type == id_TRELLIS_IO) { + new_cell->params[id_DIR] = std::string("INPUT"); + new_cell->attrs[id_IO_TYPE] = std::string("LVCMOS33"); + new_cell->params[id_DATAMUX_ODDR] = std::string("PADDO"); + new_cell->params[id_DATAMUX_MDDR] = std::string("PADDO"); + + new_cell->addInout(id_B); + new_cell->addInput(id_I); + new_cell->addInput(id_T); + new_cell->addOutput(id_O); + + new_cell->addInput(id_IOLDO); + new_cell->addInput(id_IOLTO); + + } else if (type == id_LUT4) { + new_cell->params[id_INIT] = Property(0, 16); + + new_cell->addInput(id_A); + new_cell->addInput(id_B); + new_cell->addInput(id_C); + new_cell->addInput(id_D); + new_cell->addOutput(id_Z); + } else if (type == id_CCU2C) { + new_cell->params[id_INIT0] = Property(0, 16); + new_cell->params[id_INIT1] = Property(0, 16); + new_cell->params[id_INJECT1_0] = std::string("YES"); + new_cell->params[id_INJECT1_1] = std::string("YES"); + + new_cell->addInput(id_CIN); + + new_cell->addInput(id_A0); + new_cell->addInput(id_B0); + new_cell->addInput(id_C0); + new_cell->addInput(id_D0); + + new_cell->addInput(id_A1); + new_cell->addInput(id_B1); + new_cell->addInput(id_C1); + new_cell->addInput(id_D1); + + new_cell->addOutput(id_S0); + new_cell->addOutput(id_S1); + new_cell->addOutput(id_COUT); + + } else if (type == id_DCCA) { + new_cell->addInput(id_CLKI); + new_cell->addOutput(id_CLKO); + new_cell->addInput(id_CE); } else if (type == id_IOLOGIC || type == id_SIOLOGIC) { - new_cell->params[ctx->id("MODE")] = std::string("NONE"); - new_cell->params[ctx->id("GSR")] = std::string("DISABLED"); - new_cell->params[ctx->id("CLKIMUX")] = std::string("CLK"); - new_cell->params[ctx->id("CLKOMUX")] = std::string("CLK"); - new_cell->params[ctx->id("LSRIMUX")] = std::string("0"); - new_cell->params[ctx->id("LSROMUX")] = std::string("0"); - new_cell->params[ctx->id("LSRMUX")] = std::string("LSR"); + new_cell->params[id_MODE] = std::string("NONE"); + new_cell->params[id_GSR] = std::string("DISABLED"); + new_cell->params[id_CLKIMUX] = std::string("CLK"); + new_cell->params[id_CLKOMUX] = std::string("CLK"); + new_cell->params[id_LSRIMUX] = std::string("0"); + new_cell->params[id_LSROMUX] = std::string("0"); + new_cell->params[id_LSRMUX] = std::string("LSR"); new_cell->params[ctx->id("DELAY.OUTDEL")] = std::string("DISABLED"); new_cell->params[ctx->id("DELAY.DEL_VALUE")] = Property(0, 7); @@ -193,7 +183,7 @@ std::unique_ptr<CellInfo> create_ecp5_cell(Context *ctx, IdString type, std::str new_cell->params[ctx->id("MODDRX.MODE")] = std::string("NONE"); new_cell->params[ctx->id("MTDDRX.MODE")] = std::string("NONE"); - new_cell->params[ctx->id("IOLTOMUX")] = std::string("NONE"); + new_cell->params[id_IOLTOMUX] = std::string("NONE"); new_cell->params[ctx->id("MTDDRX.DQSW_INVERT")] = std::string("DISABLED"); new_cell->params[ctx->id("MTDDRX.REGSET")] = std::string("RESET"); @@ -202,8 +192,8 @@ std::unique_ptr<CellInfo> create_ecp5_cell(Context *ctx, IdString type, std::str // Just copy ports from the Bel copy_bel_ports(); } else if (type == id_TRELLIS_ECLKBUF) { - add_port(ctx, new_cell.get(), "ECLKI", PORT_IN); - add_port(ctx, new_cell.get(), "ECLKO", PORT_OUT); + new_cell->addInput(id_ECLKI); + new_cell->addOutput(id_ECLKO); } else { log_error("unable to create ECP5 cell of type %s", type.c_str(ctx)); } @@ -227,7 +217,7 @@ static void replace_port_safe(bool has_ff, CellInfo *ff, IdString ff_port, CellI [ff, ff_port](PortRef port) { return port.cell == ff && port.port == ff_port; }), ffnet->users.end()); } else { - replace_port(ff, ff_port, lc, lc_port); + ff->movePortTo(ff_port, lc, lc_port); } } @@ -235,38 +225,38 @@ void ff_to_slice(Context *ctx, CellInfo *ff, CellInfo *lc, int index, bool drive { if (lc->hierpath == IdString()) lc->hierpath = ff->hierpath; - bool has_ff = lc->ports.at(ctx->id("Q0")).net != nullptr || lc->ports.at(ctx->id("Q1")).net != nullptr; + bool has_ff = lc->ports.at(id_Q0).net != nullptr || lc->ports.at(id_Q1).net != nullptr; std::string reg = "REG" + std::to_string(index); - set_param_safe(has_ff, lc, ctx->id("SRMODE"), str_or_default(ff->params, ctx->id("SRMODE"), "LSR_OVER_CE")); - set_param_safe(has_ff, lc, ctx->id("GSR"), str_or_default(ff->params, ctx->id("GSR"), "DISABLED")); - set_param_safe(has_ff, lc, ctx->id("CEMUX"), str_or_default(ff->params, ctx->id("CEMUX"), "1")); - set_param_safe(has_ff, lc, ctx->id("LSRMUX"), str_or_default(ff->params, ctx->id("LSRMUX"), "LSR")); - set_param_safe(has_ff, lc, ctx->id("CLKMUX"), str_or_default(ff->params, ctx->id("CLKMUX"), "CLK")); + set_param_safe(has_ff, lc, id_SRMODE, str_or_default(ff->params, id_SRMODE, "LSR_OVER_CE")); + set_param_safe(has_ff, lc, id_GSR, str_or_default(ff->params, id_GSR, "DISABLED")); + set_param_safe(has_ff, lc, id_CEMUX, str_or_default(ff->params, id_CEMUX, "1")); + set_param_safe(has_ff, lc, id_LSRMUX, str_or_default(ff->params, id_LSRMUX, "LSR")); + set_param_safe(has_ff, lc, id_CLKMUX, str_or_default(ff->params, id_CLKMUX, "CLK")); lc->params[ctx->id(reg + "_SD")] = std::string(driven_by_lut ? "1" : "0"); - lc->params[ctx->id(reg + "_REGSET")] = str_or_default(ff->params, ctx->id("REGSET"), "RESET"); - lc->params[ctx->id(reg + "_LSRMODE")] = str_or_default(ff->params, ctx->id("LSRMODE"), "LSR"); - replace_port_safe(has_ff, ff, ctx->id("CLK"), lc, ctx->id("CLK")); - if (ff->ports.find(ctx->id("LSR")) != ff->ports.end()) - replace_port_safe(has_ff, ff, ctx->id("LSR"), lc, ctx->id("LSR")); - if (ff->ports.find(ctx->id("CE")) != ff->ports.end()) - replace_port_safe(has_ff, ff, ctx->id("CE"), lc, ctx->id("CE")); - - replace_port(ff, ctx->id("Q"), lc, ctx->id("Q" + std::to_string(index))); - if (get_net_or_empty(ff, ctx->id("M")) != nullptr) { + lc->params[ctx->id(reg + "_REGSET")] = str_or_default(ff->params, id_REGSET, "RESET"); + lc->params[ctx->id(reg + "_LSRMODE")] = str_or_default(ff->params, id_LSRMODE, "LSR"); + replace_port_safe(has_ff, ff, id_CLK, lc, id_CLK); + if (ff->ports.find(id_LSR) != ff->ports.end()) + replace_port_safe(has_ff, ff, id_LSR, lc, id_LSR); + if (ff->ports.find(id_CE) != ff->ports.end()) + replace_port_safe(has_ff, ff, id_CE, lc, id_CE); + + ff->movePortTo(id_Q, lc, ctx->id("Q" + std::to_string(index))); + if (ff->getPort(id_M) != nullptr) { // PRLD FFs that use both M and DI NPNR_ASSERT(!driven_by_lut); // As M is used; must route DI through a new LUT lc->params[ctx->id(reg + "_SD")] = std::string("1"); lc->params[ctx->id("LUT" + std::to_string(index) + "_INITVAL")] = Property(0xFF00, 16); - replace_port(ff, ctx->id("DI"), lc, ctx->id("D" + std::to_string(index))); - replace_port(ff, ctx->id("M"), lc, ctx->id("M" + std::to_string(index))); - connect_ports(ctx, lc, ctx->id("F" + std::to_string(index)), lc, ctx->id("DI" + std::to_string(index))); + ff->movePortTo(id_DI, lc, ctx->id("D" + std::to_string(index))); + ff->movePortTo(id_M, lc, ctx->id("M" + std::to_string(index))); + lc->connectPorts(ctx->id("F" + std::to_string(index)), lc, ctx->id("DI" + std::to_string(index))); } else { if (driven_by_lut) { - replace_port(ff, ctx->id("DI"), lc, ctx->id("DI" + std::to_string(index))); + ff->movePortTo(id_DI, lc, ctx->id("DI" + std::to_string(index))); } else { - replace_port(ff, ctx->id("DI"), lc, ctx->id("M" + std::to_string(index))); + ff->movePortTo(id_DI, lc, ctx->id("M" + std::to_string(index))); } } } @@ -276,62 +266,62 @@ void lut_to_slice(Context *ctx, CellInfo *lut, CellInfo *lc, int index) if (lc->hierpath == IdString()) lc->hierpath = lut->hierpath; lc->params[ctx->id("LUT" + std::to_string(index) + "_INITVAL")] = - get_or_default(lut->params, ctx->id("INIT"), Property(0, 16)); - replace_port(lut, ctx->id("A"), lc, ctx->id("A" + std::to_string(index))); - replace_port(lut, ctx->id("B"), lc, ctx->id("B" + std::to_string(index))); - replace_port(lut, ctx->id("C"), lc, ctx->id("C" + std::to_string(index))); - replace_port(lut, ctx->id("D"), lc, ctx->id("D" + std::to_string(index))); - replace_port(lut, ctx->id("Z"), lc, ctx->id("F" + std::to_string(index))); + get_or_default(lut->params, id_INIT, Property(0, 16)); + lut->movePortTo(id_A, lc, ctx->id("A" + std::to_string(index))); + lut->movePortTo(id_B, lc, ctx->id("B" + std::to_string(index))); + lut->movePortTo(id_C, lc, ctx->id("C" + std::to_string(index))); + lut->movePortTo(id_D, lc, ctx->id("D" + std::to_string(index))); + lut->movePortTo(id_Z, lc, ctx->id("F" + std::to_string(index))); } void ccu2c_to_slice(Context *ctx, CellInfo *ccu, CellInfo *lc) { if (lc->hierpath == IdString()) lc->hierpath = ccu->hierpath; - lc->params[ctx->id("MODE")] = std::string("CCU2"); - lc->params[ctx->id("LUT0_INITVAL")] = get_or_default(ccu->params, ctx->id("INIT0"), Property(0, 16)); - lc->params[ctx->id("LUT1_INITVAL")] = get_or_default(ccu->params, ctx->id("INIT1"), Property(0, 16)); + lc->params[id_MODE] = std::string("CCU2"); + lc->params[id_LUT0_INITVAL] = get_or_default(ccu->params, id_INIT0, Property(0, 16)); + lc->params[id_LUT1_INITVAL] = get_or_default(ccu->params, id_INIT1, Property(0, 16)); - lc->params[ctx->id("CCU2_INJECT1_0")] = str_or_default(ccu->params, ctx->id("INJECT1_0"), "YES"); - lc->params[ctx->id("CCU2_INJECT1_1")] = str_or_default(ccu->params, ctx->id("INJECT1_1"), "YES"); + lc->params[id_CCU2_INJECT1_0] = str_or_default(ccu->params, id_INJECT1_0, "YES"); + lc->params[id_CCU2_INJECT1_1] = str_or_default(ccu->params, id_INJECT1_1, "YES"); - replace_port(ccu, ctx->id("CIN"), lc, ctx->id("FCI")); + ccu->movePortTo(id_CIN, lc, id_FCI); - replace_port(ccu, ctx->id("A0"), lc, ctx->id("A0")); - replace_port(ccu, ctx->id("B0"), lc, ctx->id("B0")); - replace_port(ccu, ctx->id("C0"), lc, ctx->id("C0")); - replace_port(ccu, ctx->id("D0"), lc, ctx->id("D0")); + ccu->movePortTo(id_A0, lc, id_A0); + ccu->movePortTo(id_B0, lc, id_B0); + ccu->movePortTo(id_C0, lc, id_C0); + ccu->movePortTo(id_D0, lc, id_D0); - replace_port(ccu, ctx->id("A1"), lc, ctx->id("A1")); - replace_port(ccu, ctx->id("B1"), lc, ctx->id("B1")); - replace_port(ccu, ctx->id("C1"), lc, ctx->id("C1")); - replace_port(ccu, ctx->id("D1"), lc, ctx->id("D1")); + ccu->movePortTo(id_A1, lc, id_A1); + ccu->movePortTo(id_B1, lc, id_B1); + ccu->movePortTo(id_C1, lc, id_C1); + ccu->movePortTo(id_D1, lc, id_D1); - replace_port(ccu, ctx->id("S0"), lc, ctx->id("F0")); - replace_port(ccu, ctx->id("S1"), lc, ctx->id("F1")); + ccu->movePortTo(id_S0, lc, id_F0); + ccu->movePortTo(id_S1, lc, id_F1); - replace_port(ccu, ctx->id("COUT"), lc, ctx->id("FCO")); + ccu->movePortTo(id_COUT, lc, id_FCO); } void dram_to_ramw(Context *ctx, CellInfo *ram, CellInfo *lc) { if (lc->hierpath == IdString()) lc->hierpath = ram->hierpath; - lc->params[ctx->id("MODE")] = std::string("RAMW"); - replace_port(ram, ctx->id("WAD[0]"), lc, ctx->id("D0")); - replace_port(ram, ctx->id("WAD[1]"), lc, ctx->id("B0")); - replace_port(ram, ctx->id("WAD[2]"), lc, ctx->id("C0")); - replace_port(ram, ctx->id("WAD[3]"), lc, ctx->id("A0")); - - replace_port(ram, ctx->id("DI[0]"), lc, ctx->id("C1")); - replace_port(ram, ctx->id("DI[1]"), lc, ctx->id("A1")); - replace_port(ram, ctx->id("DI[2]"), lc, ctx->id("D1")); - replace_port(ram, ctx->id("DI[3]"), lc, ctx->id("B1")); + lc->params[id_MODE] = std::string("RAMW"); + ram->movePortTo(ctx->id("WAD[0]"), lc, id_D0); + ram->movePortTo(ctx->id("WAD[1]"), lc, id_B0); + ram->movePortTo(ctx->id("WAD[2]"), lc, id_C0); + ram->movePortTo(ctx->id("WAD[3]"), lc, id_A0); + + ram->movePortTo(ctx->id("DI[0]"), lc, id_C1); + ram->movePortTo(ctx->id("DI[1]"), lc, id_A1); + ram->movePortTo(ctx->id("DI[2]"), lc, id_D1); + ram->movePortTo(ctx->id("DI[3]"), lc, id_B1); } static unsigned get_dram_init(const Context *ctx, const CellInfo *ram, int bit) { - auto init_prop = get_or_default(ram->params, ctx->id("INITVAL"), Property(0, 64)); + auto init_prop = get_or_default(ram->params, id_INITVAL, Property(0, 64)); NPNR_ASSERT(!init_prop.is_string); const std::string &idata = init_prop.str; NPNR_ASSERT(idata.length() == 64); @@ -350,9 +340,9 @@ void dram_to_ram_slice(Context *ctx, CellInfo *ram, CellInfo *lc, CellInfo *ramw { if (lc->hierpath == IdString()) lc->hierpath = ram->hierpath; - lc->params[ctx->id("MODE")] = std::string("DPRAM"); - lc->params[ctx->id("WREMUX")] = str_or_default(ram->params, ctx->id("WREMUX"), "WRE"); - lc->params[ctx->id("WCKMUX")] = str_or_default(ram->params, ctx->id("WCKMUX"), "WCK"); + lc->params[id_MODE] = std::string("DPRAM"); + lc->params[id_WREMUX] = str_or_default(ram->params, id_WREMUX, "WRE"); + lc->params[id_WCKMUX] = str_or_default(ram->params, id_WCKMUX, "WCK"); unsigned permuted_init0 = 0, permuted_init1 = 0; unsigned init0 = get_dram_init(ctx, ram, index * 2), init1 = get_dram_init(ctx, ram, index * 2 + 1); @@ -373,49 +363,49 @@ void dram_to_ram_slice(Context *ctx, CellInfo *ram, CellInfo *lc, CellInfo *ramw permuted_init1 |= (1 << i); } - lc->params[ctx->id("LUT0_INITVAL")] = Property(permuted_init0, 16); - lc->params[ctx->id("LUT1_INITVAL")] = Property(permuted_init1, 16); + lc->params[id_LUT0_INITVAL] = Property(permuted_init0, 16); + lc->params[id_LUT1_INITVAL] = Property(permuted_init1, 16); if (ram->ports.count(ctx->id("RAD[0]"))) { - connect_port(ctx, ram->ports.at(ctx->id("RAD[0]")).net, lc, ctx->id("D0")); - connect_port(ctx, ram->ports.at(ctx->id("RAD[0]")).net, lc, ctx->id("D1")); + lc->connectPort(id_D0, ram->ports.at(ctx->id("RAD[0]")).net); + lc->connectPort(id_D1, ram->ports.at(ctx->id("RAD[0]")).net); } if (ram->ports.count(ctx->id("RAD[1]"))) { - connect_port(ctx, ram->ports.at(ctx->id("RAD[1]")).net, lc, ctx->id("B0")); - connect_port(ctx, ram->ports.at(ctx->id("RAD[1]")).net, lc, ctx->id("B1")); + lc->connectPort(id_B0, ram->ports.at(ctx->id("RAD[1]")).net); + lc->connectPort(id_B1, ram->ports.at(ctx->id("RAD[1]")).net); } if (ram->ports.count(ctx->id("RAD[2]"))) { - connect_port(ctx, ram->ports.at(ctx->id("RAD[2]")).net, lc, ctx->id("C0")); - connect_port(ctx, ram->ports.at(ctx->id("RAD[2]")).net, lc, ctx->id("C1")); + lc->connectPort(id_C0, ram->ports.at(ctx->id("RAD[2]")).net); + lc->connectPort(id_C1, ram->ports.at(ctx->id("RAD[2]")).net); } if (ram->ports.count(ctx->id("RAD[3]"))) { - connect_port(ctx, ram->ports.at(ctx->id("RAD[3]")).net, lc, ctx->id("A0")); - connect_port(ctx, ram->ports.at(ctx->id("RAD[3]")).net, lc, ctx->id("A1")); + lc->connectPort(id_A0, ram->ports.at(ctx->id("RAD[3]")).net); + lc->connectPort(id_A1, ram->ports.at(ctx->id("RAD[3]")).net); } - if (ram->ports.count(ctx->id("WRE"))) - connect_port(ctx, ram->ports.at(ctx->id("WRE")).net, lc, ctx->id("WRE")); - if (ram->ports.count(ctx->id("WCK"))) - connect_port(ctx, ram->ports.at(ctx->id("WCK")).net, lc, ctx->id("WCK")); + if (ram->ports.count(id_WRE)) + lc->connectPort(id_WRE, ram->ports.at(id_WRE).net); + if (ram->ports.count(id_WCK)) + lc->connectPort(id_WCK, ram->ports.at(id_WCK).net); - connect_ports(ctx, ramw, id_WADO0, lc, id_WAD0); - connect_ports(ctx, ramw, id_WADO1, lc, id_WAD1); - connect_ports(ctx, ramw, id_WADO2, lc, id_WAD2); - connect_ports(ctx, ramw, id_WADO3, lc, id_WAD3); + ramw->connectPorts(id_WADO0, lc, id_WAD0); + ramw->connectPorts(id_WADO1, lc, id_WAD1); + ramw->connectPorts(id_WADO2, lc, id_WAD2); + ramw->connectPorts(id_WADO3, lc, id_WAD3); if (index == 0) { - connect_ports(ctx, ramw, id_WDO0, lc, id_WD0); - connect_ports(ctx, ramw, id_WDO1, lc, id_WD1); + ramw->connectPorts(id_WDO0, lc, id_WD0); + ramw->connectPorts(id_WDO1, lc, id_WD1); - replace_port(ram, ctx->id("DO[0]"), lc, id_F0); - replace_port(ram, ctx->id("DO[1]"), lc, id_F1); + ram->movePortTo(ctx->id("DO[0]"), lc, id_F0); + ram->movePortTo(ctx->id("DO[1]"), lc, id_F1); } else if (index == 1) { - connect_ports(ctx, ramw, id_WDO2, lc, id_WD0); - connect_ports(ctx, ramw, id_WDO3, lc, id_WD1); + ramw->connectPorts(id_WDO2, lc, id_WD0); + ramw->connectPorts(id_WDO3, lc, id_WD1); - replace_port(ram, ctx->id("DO[2]"), lc, id_F0); - replace_port(ram, ctx->id("DO[3]"), lc, id_F1); + ram->movePortTo(ctx->id("DO[2]"), lc, id_F0); + ram->movePortTo(ctx->id("DO[3]"), lc, id_F1); } else { NPNR_ASSERT_FALSE("bad DPRAM index"); } @@ -425,32 +415,34 @@ void nxio_to_tr(Context *ctx, CellInfo *nxio, CellInfo *trio, std::vector<std::u pool<IdString> &todelete_cells) { if (nxio->type == ctx->id("$nextpnr_ibuf")) { - trio->params[ctx->id("DIR")] = std::string("INPUT"); - replace_port(nxio, ctx->id("O"), trio, ctx->id("O")); + trio->params[id_DIR] = std::string("INPUT"); + nxio->movePortTo(id_O, trio, id_O); } else if (nxio->type == ctx->id("$nextpnr_obuf")) { - trio->params[ctx->id("DIR")] = std::string("OUTPUT"); - replace_port(nxio, ctx->id("I"), trio, ctx->id("I")); + trio->params[id_DIR] = std::string("OUTPUT"); + nxio->movePortTo(id_I, trio, id_I); } else if (nxio->type == ctx->id("$nextpnr_iobuf")) { // N.B. tristate will be dealt with below - NetInfo *i = get_net_or_empty(nxio, ctx->id("I")); + NetInfo *i = nxio->getPort(id_I); if (i == nullptr || i->driver.cell == nullptr) - trio->params[ctx->id("DIR")] = std::string("INPUT"); + trio->params[id_DIR] = std::string("INPUT"); else { log_info("%s: %s.%s\n", ctx->nameOf(i), ctx->nameOf(i->driver.cell), ctx->nameOf(i->driver.port)); - trio->params[ctx->id("DIR")] = std::string("BIDIR"); + trio->params[id_DIR] = std::string("BIDIR"); } - replace_port(nxio, ctx->id("I"), trio, ctx->id("I")); - replace_port(nxio, ctx->id("O"), trio, ctx->id("O")); + nxio->movePortTo(id_I, trio, id_I); + nxio->movePortTo(id_O, trio, id_O); } else { NPNR_ASSERT(false); } - NetInfo *donet = trio->ports.at(ctx->id("I")).net, *dinet = trio->ports.at(ctx->id("O")).net; + NetInfo *donet = trio->ports.at(id_I).net, *dinet = trio->ports.at(id_O).net; // Rename I/O nets to avoid conflicts if (donet != nullptr && donet->name == nxio->name) - rename_net(ctx, donet, ctx->id(donet->name.str(ctx) + "$TRELLIS_IO_OUT")); + if (donet) + ctx->renameNet(donet->name, ctx->id(donet->name.str(ctx) + "$TRELLIS_IO_OUT")); if (dinet != nullptr && dinet->name == nxio->name) - rename_net(ctx, dinet, ctx->id(dinet->name.str(ctx) + "$TRELLIS_IO_IN")); + if (dinet) + ctx->renameNet(dinet->name, ctx->id(dinet->name.str(ctx) + "$TRELLIS_IO_IN")); if (ctx->nets.count(nxio->name)) { int i = 0; @@ -458,30 +450,31 @@ void nxio_to_tr(Context *ctx, CellInfo *nxio, CellInfo *trio, std::vector<std::u do { new_name = ctx->id(nxio->name.str(ctx) + "$rename$" + std::to_string(i++)); } while (ctx->nets.count(new_name)); - rename_net(ctx, ctx->nets.at(nxio->name).get(), new_name); + if (ctx->nets.at(nxio->name).get()) + ctx->renameNet(ctx->nets.at(nxio->name).get()->name, new_name); } // Create a new top port net for accurate IO timing analysis and simulation netlists if (ctx->ports.count(nxio->name)) { IdString tn_netname = nxio->name; NPNR_ASSERT(!ctx->nets.count(tn_netname)); - std::unique_ptr<NetInfo> toplevel_net{new NetInfo}; + ctx->net_aliases.erase(tn_netname); + NetInfo *toplevel_net = ctx->createNet(tn_netname); toplevel_net->name = tn_netname; - connect_port(ctx, toplevel_net.get(), trio, ctx->id("B")); - ctx->ports[nxio->name].net = toplevel_net.get(); - ctx->nets[tn_netname] = std::move(toplevel_net); + trio->connectPort(id_B, toplevel_net); + ctx->ports[nxio->name].net = toplevel_net; } CellInfo *tbuf = net_driven_by( ctx, donet, [](const Context *ctx, const CellInfo *cell) { return cell->type == ctx->id("$_TBUF_"); }, - ctx->id("Y")); + id_Y); if (tbuf) { - replace_port(tbuf, ctx->id("A"), trio, ctx->id("I")); + tbuf->movePortTo(id_A, trio, id_I); // Need to invert E to form T - std::unique_ptr<CellInfo> inv_lut = create_ecp5_cell(ctx, ctx->id("LUT4"), trio->name.str(ctx) + "$invert_T"); - replace_port(tbuf, ctx->id("E"), inv_lut.get(), ctx->id("A")); - inv_lut->params[ctx->id("INIT")] = Property(21845, 16); - connect_ports(ctx, inv_lut.get(), ctx->id("Z"), trio, ctx->id("T")); + std::unique_ptr<CellInfo> inv_lut = create_ecp5_cell(ctx, id_LUT4, trio->name.str(ctx) + "$invert_T"); + tbuf->movePortTo(id_E, inv_lut.get(), id_A); + inv_lut->params[id_INIT] = Property(21845, 16); + inv_lut->connectPorts(id_Z, trio, id_T); created_cells.push_back(std::move(inv_lut)); if (donet->users.size() > 1) { |