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-rw-r--r--ecp5/cells.cc46
1 files changed, 46 insertions, 0 deletions
diff --git a/ecp5/cells.cc b/ecp5/cells.cc
index 31839ee4..9621b35c 100644
--- a/ecp5/cells.cc
+++ b/ecp5/cells.cc
@@ -41,6 +41,22 @@ std::unique_ptr<CellInfo> create_ecp5_cell(Context *ctx, IdString type, std::str
new_cell->name = ctx->id(name);
}
new_cell->type = type;
+
+ auto copy_bel_ports = [&]() {
+ // First find a Bel of the target type
+ BelId tgt;
+ for (auto bel : ctx->getBels()) {
+ if (ctx->getBelType(bel) == type) {
+ tgt = bel;
+ break;
+ }
+ }
+ NPNR_ASSERT(tgt != BelId());
+ for (auto port : ctx->getBelPins(tgt)) {
+ add_port(ctx, new_cell.get(), port.str(ctx), ctx->getBelPinType(tgt, port));
+ }
+ };
+
if (type == ctx->id("TRELLIS_SLICE")) {
new_cell->params[ctx->id("MODE")] = "LOGIC";
new_cell->params[ctx->id("GSR")] = "DISABLED";
@@ -150,6 +166,36 @@ std::unique_ptr<CellInfo> create_ecp5_cell(Context *ctx, IdString type, std::str
add_port(ctx, new_cell.get(), "CLKI", PORT_IN);
add_port(ctx, new_cell.get(), "CLKO", PORT_OUT);
add_port(ctx, new_cell.get(), "CE", PORT_IN);
+ } else if (type == id_IOLOGIC || type == id_SIOLOGIC) {
+ new_cell->params[ctx->id("MODE")] = "NONE";
+ new_cell->params[ctx->id("GSR")] = "DISABLED";
+ new_cell->params[ctx->id("CLKIMUX")] = "CLK";
+ new_cell->params[ctx->id("CLKOMUX")] = "CLK";
+ new_cell->params[ctx->id("LSRIMUX")] = "0";
+ new_cell->params[ctx->id("LSROMUX")] = "0";
+ new_cell->params[ctx->id("LSRMUX")] = "LSR";
+
+ new_cell->params[ctx->id("OUTDEL")] = "DISABLED";
+ new_cell->params[ctx->id("DEL_VALUE")] = "0";
+ new_cell->params[ctx->id("WAIT_FOR_EDGE")] = "DISABLED";
+
+ new_cell->params[ctx->id("DATAMUX_ODDR")] = "PADDO";
+ if (type == id_IOLOGIC) {
+ new_cell->params[ctx->id("IDDRXN_MODE")] = "NONE";
+ new_cell->params[ctx->id("ODDRXN_MODE")] = "NONE";
+
+ new_cell->params[ctx->id("MIDDRX_MODE")] = "NONE";
+ new_cell->params[ctx->id("MODDRX_MODE")] = "NONE";
+ new_cell->params[ctx->id("MTDDRX_MODE")] = "NONE";
+
+ new_cell->params[ctx->id("IOLTOMUX")] = "NONE";
+ new_cell->params[ctx->id("MTDDRX_DQSW_INVERT")] = "DISABLED";
+ new_cell->params[ctx->id("MTDDRX_REGSET")] = "RESET";
+
+ new_cell->params[ctx->id("MIDDRX_MODDRX_WRCLKMUX")] = "NONE";
+ }
+ // Just copy ports from the Bel
+ copy_bel_ports();
} else {
log_error("unable to create ECP5 cell of type %s", type.c_str(ctx));
}