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-rw-r--r--ecp5/pack.cc1009
1 files changed, 1007 insertions, 2 deletions
diff --git a/ecp5/pack.cc b/ecp5/pack.cc
index ca329530..7f00de1f 100644
--- a/ecp5/pack.cc
+++ b/ecp5/pack.cc
@@ -20,12 +20,14 @@
#include <algorithm>
#include <boost/optional.hpp>
#include <iterator>
+#include <queue>
#include <unordered_set>
#include "cells.h"
#include "chain_utils.h"
#include "design_utils.h"
#include "globals.h"
#include "log.h"
+#include "timing.h"
#include "util.h"
NEXTPNR_NAMESPACE_BEGIN
@@ -163,6 +165,7 @@ class Ecp5Packer
CellInfo *ci = cell.second;
if (is_lut(ctx, ci) && procdLuts.find(cell.first) == procdLuts.end()) {
NetInfo *znet = ci->ports.at(ctx->id("Z")).net;
+ std::vector<NetInfo *> inpnets;
if (znet != nullptr) {
for (auto user : znet->users) {
if (is_lut(ctx, user.cell) && user.cell != ci &&
@@ -227,12 +230,67 @@ class Ecp5Packer
}
}
}
+
+ // Pack LUTs feeding the same CCU2, RAM or DFF into a SLICE
+ if (znet != nullptr && znet->users.size() < 10) {
+ for (auto user : znet->users) {
+ if (is_lc(ctx, user.cell) || user.cell->type == ctx->id("DP16KD") || is_ff(ctx, user.cell)) {
+ for (auto port : user.cell->ports) {
+ if (port.second.type != PORT_IN || port.second.net == nullptr ||
+ port.second.net == znet)
+ continue;
+ if (port.second.net->users.size() > 10)
+ continue;
+ CellInfo *drv = port.second.net->driver.cell;
+ if (drv == nullptr)
+ continue;
+ if (is_lut(ctx, drv) && !procdLuts.count(drv->name) &&
+ can_pack_lutff(ci->name, drv->name)) {
+ procdLuts.insert(ci->name);
+ procdLuts.insert(drv->name);
+ lutPairs[ci->name] = drv->name;
+ goto paired_inlut;
+ }
+ }
+ }
+ }
+ }
+
+ // Pack LUTs sharing an input with a simple fanout-based heuristic
+ for (const char *inp : {"A", "B", "C", "D"}) {
+ NetInfo *innet = ci->ports.at(ctx->id(inp)).net;
+ if (innet != nullptr && innet->users.size() < 5 && innet->users.size() > 1)
+ inpnets.push_back(innet);
+ }
+ std::sort(inpnets.begin(), inpnets.end(),
+ [&](const NetInfo *a, const NetInfo *b) { return a->users.size() < b->users.size(); });
+ for (auto inet : inpnets) {
+ for (auto &user : inet->users) {
+ if (user.cell == nullptr || user.cell == ci || !is_lut(ctx, user.cell))
+ continue;
+ if (procdLuts.count(user.cell->name))
+ continue;
+ if (can_pack_lutff(ci->name, user.cell->name)) {
+ procdLuts.insert(ci->name);
+ procdLuts.insert(user.cell->name);
+ lutPairs[ci->name] = user.cell->name;
+ goto paired_inlut;
+ }
+ }
+ }
+
if (false) {
paired_inlut:
continue;
}
}
}
+ if (ctx->debug) {
+ log_info("Singleton LUTs (packer QoR debug): \n");
+ for (auto cell : sorted(ctx->cells))
+ if (is_lut(ctx, cell.second) && !procdLuts.count(cell.first))
+ log_info(" %s\n", cell.first.c_str(ctx));
+ }
}
// Return true if an port is a top level port that provides its own IOBUF
@@ -299,7 +357,16 @@ class Ecp5Packer
// iobuf
log_info("%s feeds TRELLIS_IO %s, removing %s %s.\n", ci->name.c_str(ctx), trio->name.c_str(ctx),
ci->type.c_str(ctx), ci->name.c_str(ctx));
+
NetInfo *net = trio->ports.at(ctx->id("B")).net;
+ if (((ci->type == ctx->id("$nextpnr_ibuf") || ci->type == ctx->id("$nextpnr_iobuf")) &&
+ net->users.size() > 1) ||
+ (ci->type == ctx->id("$nextpnr_obuf") &&
+ (net->users.size() > 2 || net->driver.cell != nullptr)) ||
+ (ci->type == ctx->id("$nextpnr_iobuf") && ci->ports.at(ctx->id("I")).net != nullptr &&
+ ci->ports.at(ctx->id("I")).net->driver.cell != nullptr))
+ log_error("Pin B of %s '%s' connected to more than a single top level IO.\n",
+ trio->type.c_str(ctx), trio->name.c_str(ctx));
if (net != nullptr) {
ctx->nets.erase(net->name);
trio->ports.at(ctx->id("B")).net = nullptr;
@@ -930,11 +997,11 @@ class Ecp5Packer
if (is_lut(ctx, ci)) {
std::unique_ptr<CellInfo> slice =
create_ecp5_cell(ctx, ctx->id("TRELLIS_SLICE"), ci->name.str(ctx) + "_SLICE");
- lut_to_slice(ctx, ci, slice.get(), 0);
+ lut_to_slice(ctx, ci, slice.get(), 1);
auto ff = lutffPairs.find(ci->name);
if (ff != lutffPairs.end()) {
- ff_to_slice(ctx, ctx->cells.at(ff->second).get(), slice.get(), 0, true);
+ ff_to_slice(ctx, ctx->cells.at(ff->second).get(), slice.get(), 1, true);
packed_cells.insert(ff->second);
fflutPairs.erase(ff->second);
lutffPairs.erase(ci->name);
@@ -1323,6 +1390,19 @@ class Ecp5Packer
}
}
+ // Miscellaneous packer tasks
+ void pack_misc()
+ {
+ for (auto cell : sorted(ctx->cells)) {
+ CellInfo *ci = cell.second;
+ if (ci->type == id_USRMCLK) {
+ rename_port(ctx, ci, ctx->id("USRMCLKI"), id_PADDO);
+ rename_port(ctx, ci, ctx->id("USRMCLKTS"), id_PADDT);
+ rename_port(ctx, ci, ctx->id("USRMCLKO"), id_PADDI);
+ }
+ }
+ }
+
// Preplace PLL
void preplace_plls()
{
@@ -1377,13 +1457,934 @@ class Ecp5Packer
}
}
+ // Check if two nets have identical constant drivers
+ bool equal_constant(NetInfo *a, NetInfo *b)
+ {
+ if (a->driver.cell == nullptr || b->driver.cell == nullptr)
+ return (a->driver.cell == nullptr && b->driver.cell == nullptr);
+ if (a->driver.cell->type != ctx->id("GND") && a->driver.cell->type != ctx->id("VCC"))
+ return false;
+ return a->driver.cell->type == b->driver.cell->type;
+ }
+
+ struct EdgeClockInfo
+ {
+ CellInfo *buffer = nullptr;
+ NetInfo *unbuf = nullptr;
+ NetInfo *buf = nullptr;
+ };
+
+ std::map<std::pair<int, int>, EdgeClockInfo> eclks;
+
+ void make_eclk(PortInfo &usr_port, CellInfo *usr_cell, BelId usr_bel, int bank)
+ {
+ NetInfo *ecknet = usr_port.net;
+ if (ecknet == nullptr)
+ log_error("Input '%s' of cell '%s' cannot be disconnected\n", usr_port.name.c_str(ctx),
+ usr_cell->name.c_str(ctx));
+ int found_eclk = -1, free_eclk = -1;
+ for (int i = 0; i < 2; i++) {
+ if (eclks.count(std::make_pair(bank, i))) {
+ if (eclks.at(std::make_pair(bank, i)).unbuf == ecknet) {
+ found_eclk = i;
+ break;
+ }
+ } else if (free_eclk == -1) {
+ free_eclk = i;
+ }
+ }
+ if (found_eclk == -1) {
+ if (free_eclk == -1) {
+ log_error("Unable to promote edge clock '%s' for bank %d. 2/2 edge clocks already used by '%s' and "
+ "'%s'.\n",
+ ecknet->name.c_str(ctx), bank, eclks.at(std::make_pair(bank, 0)).unbuf->name.c_str(ctx),
+ eclks.at(std::make_pair(bank, 1)).unbuf->name.c_str(ctx));
+ } else {
+ log_info("Promoted '%s' to bank %d ECLK%d.\n", ecknet->name.c_str(ctx), bank, free_eclk);
+ auto &eclk = eclks[std::make_pair(bank, free_eclk)];
+ eclk.unbuf = ecknet;
+ IdString eckname = ctx->id(ecknet->name.str(ctx) + "$eclk" + std::to_string(bank) + "_" +
+ std::to_string(free_eclk));
+
+ std::unique_ptr<NetInfo> promoted_ecknet(new NetInfo);
+ promoted_ecknet->name = eckname;
+ promoted_ecknet->is_global = true; // Prevents router etc touching this special net
+ eclk.buf = promoted_ecknet.get();
+ NPNR_ASSERT(!ctx->nets.count(eckname));
+ ctx->nets[eckname] = std::move(promoted_ecknet);
+
+ // Insert TRELLIS_ECLKBUF to isolate edge clock from general routing
+ std::unique_ptr<CellInfo> eclkbuf =
+ create_ecp5_cell(ctx, id_TRELLIS_ECLKBUF, eckname.str(ctx) + "$buffer");
+ BelId target_bel;
+ // Find the correct Bel for the ECLKBUF
+ IdString eclkname = ctx->id("G_BANK" + std::to_string(bank) + "ECLK" + std::to_string(free_eclk));
+ for (auto bel : ctx->getBels()) {
+ if (ctx->getBelType(bel) != id_TRELLIS_ECLKBUF)
+ continue;
+ if (ctx->getWireBasename(ctx->getBelPinWire(bel, id_ECLKO)) != eclkname)
+ continue;
+ target_bel = bel;
+ break;
+ }
+ NPNR_ASSERT(target_bel != BelId());
+
+ eclkbuf->attrs[ctx->id("BEL")] = ctx->getBelName(target_bel).str(ctx);
+
+ connect_port(ctx, ecknet, eclkbuf.get(), id_ECLKI);
+ connect_port(ctx, eclk.buf, eclkbuf.get(), id_ECLKO);
+ found_eclk = free_eclk;
+ eclk.buffer = eclkbuf.get();
+ new_cells.push_back(std::move(eclkbuf));
+ }
+ }
+
+ auto &eclk = eclks[std::make_pair(bank, found_eclk)];
+ disconnect_port(ctx, usr_cell, usr_port.name);
+ usr_port.net = nullptr;
+ connect_port(ctx, eclk.buf, usr_cell, usr_port.name);
+
+ // Simple ECLK router
+ WireId userWire = ctx->getBelPinWire(usr_bel, usr_port.name);
+ IdString bnke_name = ctx->id("BNK_ECLK" + std::to_string(found_eclk));
+ IdString global_name = ctx->id("G_BANK" + std::to_string(bank) + "ECLK" + std::to_string(found_eclk));
+
+ std::queue<WireId> upstream;
+ std::unordered_map<WireId, PipId> backtrace;
+ upstream.push(userWire);
+ WireId next;
+ while (true) {
+ if (upstream.empty() || upstream.size() > 30000)
+ log_error("failed to route bank %d ECLK%d to %s.%s\n", bank, found_eclk,
+ ctx->getBelName(usr_bel).c_str(ctx), usr_port.name.c_str(ctx));
+ next = upstream.front();
+ upstream.pop();
+ if (ctx->debug)
+ log_info(" visited %s\n", ctx->getWireName(next).c_str(ctx));
+ IdString basename = ctx->getWireBasename(next);
+ if (basename == bnke_name || basename == global_name) {
+ break;
+ }
+ if (ctx->checkWireAvail(next)) {
+ for (auto pip : ctx->getPipsUphill(next)) {
+ WireId src = ctx->getPipSrcWire(pip);
+ backtrace[src] = pip;
+ upstream.push(src);
+ }
+ }
+ }
+ // Set all the pips we found along the way
+ WireId cursor = next;
+ while (true) {
+ auto fnd = backtrace.find(cursor);
+ if (fnd == backtrace.end())
+ break;
+ ctx->bindPip(fnd->second, eclk.buf, STRENGTH_LOCKED);
+ cursor = ctx->getPipDstWire(fnd->second);
+ }
+ }
+
+ void tie_zero(CellInfo *ci, IdString port)
+ {
+
+ if (!ci->ports.count(port)) {
+ ci->ports[port].name = port;
+ ci->ports[port].type = PORT_IN;
+ }
+
+ std::unique_ptr<CellInfo> zero_cell{new CellInfo};
+ std::unique_ptr<NetInfo> zero_net{new NetInfo};
+ IdString name = ctx->id(ci->name.str(ctx) + "$zero$" + port.str(ctx));
+ zero_cell->type = ctx->id("GND");
+ zero_cell->name = name;
+ zero_net->name = name;
+ zero_cell->ports[ctx->id("GND")].type = PORT_OUT;
+ connect_port(ctx, zero_net.get(), zero_cell.get(), ctx->id("GND"));
+ connect_port(ctx, zero_net.get(), ci, port);
+ ctx->nets[name] = std::move(zero_net);
+ new_cells.push_back(std::move(zero_cell));
+ }
+
+ std::unordered_map<IdString, std::pair<bool, int>> dqsbuf_dqsg;
+ // Pack DQSBUFs
+ void pack_dqsbuf()
+ {
+ for (auto cell : sorted(ctx->cells)) {
+ CellInfo *ci = cell.second;
+ if (ci->type == id_DQSBUFM) {
+ CellInfo *pio = net_driven_by(ctx, ci->ports.at(ctx->id("DQSI")).net, is_trellis_io, id_O);
+ if (pio == nullptr || ci->ports.at(ctx->id("DQSI")).net->users.size() > 1)
+ log_error("DQSBUFM '%s' DQSI input must be connected only to a top level input\n",
+ ci->name.c_str(ctx));
+ if (!pio->attrs.count(ctx->id("BEL")))
+ log_error("DQSBUFM can only be used with a pin-constrained PIO connected to its DQSI input"
+ "(while processing '%s').\n",
+ ci->name.c_str(ctx));
+ BelId pio_bel = ctx->getBelByName(ctx->id(pio->attrs.at(ctx->id("BEL"))));
+ NPNR_ASSERT(pio_bel != BelId());
+ Loc pio_loc = ctx->getBelLocation(pio_bel);
+ if (pio_loc.z != 0)
+ log_error("PIO '%s' does not appear to be a DQS site (expecting an 'A' pin).\n",
+ ctx->getBelName(pio_bel).c_str(ctx));
+ pio_loc.z = 8;
+ BelId dqsbuf = ctx->getBelByLocation(pio_loc);
+ if (dqsbuf == BelId() || ctx->getBelType(dqsbuf) != id_DQSBUFM)
+ log_error("PIO '%s' does not appear to be a DQS site (didn't find a DQSBUFM).\n",
+ ctx->getBelName(pio_bel).c_str(ctx));
+ ci->attrs[ctx->id("BEL")] = ctx->getBelName(dqsbuf).str(ctx);
+ bool got_dqsg = ctx->getPIODQSGroup(pio_bel, dqsbuf_dqsg[ci->name].first, dqsbuf_dqsg[ci->name].second);
+ NPNR_ASSERT(got_dqsg);
+ log_info("Constrained DQSBUFM '%s' to %cDQS%d\n", ci->name.c_str(ctx),
+ dqsbuf_dqsg[ci->name].first ? 'R' : 'L', dqsbuf_dqsg[ci->name].second);
+
+ // Set all special ports, if used as 'globals' that the router won't touch
+ for (auto port : {id_DQSR90, id_RDPNTR0, id_RDPNTR1, id_RDPNTR2, id_WRPNTR0, id_WRPNTR1, id_WRPNTR2,
+ id_DQSW270, id_DQSW}) {
+ if (!ci->ports.count(port))
+ continue;
+ NetInfo *pn = ci->ports.at(port).net;
+ if (pn == nullptr)
+ continue;
+ for (auto &usr : pn->users) {
+ if (usr.port != port ||
+ (usr.cell->type != ctx->id("ODDRX2DQA") && usr.cell->type != ctx->id("ODDRX2DQSB") &&
+ usr.cell->type != ctx->id("TSHX2DQSA") && usr.cell->type != ctx->id("IDDRX2DQA") &&
+ usr.cell->type != ctx->id("TSHX2DQA") && usr.cell->type != id_IOLOGIC))
+ log_error("Port '%s' of DQSBUFM '%s' cannot drive port '%s' of cell '%s'.\n",
+ port.c_str(ctx), ci->name.c_str(ctx), usr.port.c_str(ctx),
+ usr.cell->name.c_str(ctx));
+ }
+ pn->is_global = true;
+ }
+
+ for (auto zport :
+ {id_RDMOVE, id_RDDIRECTION, id_WRMOVE, id_WRDIRECTION, id_READ0, id_READ1, id_READCLKSEL0,
+ id_READCLKSEL1, id_READCLKSEL2, id_DYNDELAY0, id_DYNDELAY1, id_DYNDELAY2, id_DYNDELAY3,
+ id_DYNDELAY4, id_DYNDELAY5, id_DYNDELAY6, id_DYNDELAY7}) {
+ if (net_or_nullptr(ci, zport) == nullptr)
+ tie_zero(ci, zport);
+ }
+ }
+ }
+ }
+
+ int lookup_delay(const std::string &del_mode)
+ {
+ if (del_mode == "USER_DEFINED")
+ return 0;
+ else if (del_mode == "DQS_ALIGNED_X2")
+ return 6;
+ else if (del_mode == "DQS_CMD_CLK")
+ return 9;
+ else if (del_mode == "ECLK_ALIGNED")
+ return 21;
+ else if (del_mode == "ECLK_CENTERED")
+ return 11;
+ else if (del_mode == "ECLKBRIDGE_ALIGNED")
+ return 39;
+ else if (del_mode == "ECLKBRIDGE_CENTERED")
+ return 29;
+ else if (del_mode == "SCLK_ALIGNED")
+ return 50;
+ else if (del_mode == "SCLK_CENTERED")
+ return 39;
+ else if (del_mode == "SCLK_ZEROHOLD")
+ return 59;
+ else
+ log_error("Unsupported DEL_MODE '%s'\n", del_mode.c_str());
+ }
+
+ // Pack IOLOGIC
+ void pack_iologic()
+ {
+ std::unordered_map<IdString, CellInfo *> pio_iologic;
+
+ auto set_iologic_sclk = [&](CellInfo *iol, CellInfo *prim, IdString port, bool input) {
+ NetInfo *sclk = nullptr;
+ if (prim->ports.count(port))
+ sclk = prim->ports[port].net;
+ if (sclk == nullptr) {
+ iol->params[input ? ctx->id("CLKIMUX") : ctx->id("CLKOMUX")] = "0";
+ } else {
+ iol->params[input ? ctx->id("CLKIMUX") : ctx->id("CLKOMUX")] = "CLK";
+ if (iol->ports[id_CLK].net != nullptr) {
+ if (iol->ports[id_CLK].net != sclk && !equal_constant(iol->ports[id_CLK].net, sclk))
+ log_error("IOLOGIC '%s' has conflicting clocks '%s' and '%s'\n", iol->name.c_str(ctx),
+ iol->ports[id_CLK].net->name.c_str(ctx), sclk->name.c_str(ctx));
+ } else {
+ connect_port(ctx, sclk, iol, id_CLK);
+ }
+ }
+ if (prim->ports.count(port))
+ disconnect_port(ctx, prim, port);
+ };
+
+ auto set_iologic_eclk = [&](CellInfo *iol, CellInfo *prim, IdString port) {
+ NetInfo *eclk = nullptr;
+ if (prim->ports.count(port))
+ eclk = prim->ports[port].net;
+ if (eclk == nullptr)
+ log_error("%s '%s' cannot have disconnected ECLK", prim->type.c_str(ctx), prim->name.c_str(ctx));
+
+ if (iol->ports[id_ECLK].net != nullptr) {
+ if (iol->ports[id_ECLK].net != eclk)
+ log_error("IOLOGIC '%s' has conflicting ECLKs '%s' and '%s'\n", iol->name.c_str(ctx),
+ iol->ports[id_ECLK].net->name.c_str(ctx), eclk->name.c_str(ctx));
+ } else {
+ connect_port(ctx, eclk, iol, id_ECLK);
+ }
+ if (prim->ports.count(port))
+ disconnect_port(ctx, prim, port);
+ };
+
+ auto set_iologic_lsr = [&](CellInfo *iol, CellInfo *prim, IdString port, bool input) {
+ NetInfo *lsr = nullptr;
+ if (prim->ports.count(port))
+ lsr = prim->ports[port].net;
+ if (lsr == nullptr) {
+ iol->params[input ? ctx->id("LSRIMUX") : ctx->id("LSROMUX")] = "0";
+ } else {
+ iol->params[input ? ctx->id("LSRIMUX") : ctx->id("LSROMUX")] = "LSRMUX";
+ if (iol->ports[id_LSR].net != nullptr && !equal_constant(iol->ports[id_LSR].net, lsr)) {
+ if (iol->ports[id_LSR].net != lsr)
+ log_error("IOLOGIC '%s' has conflicting LSR signals '%s' and '%s'\n", iol->name.c_str(ctx),
+ iol->ports[id_LSR].net->name.c_str(ctx), lsr->name.c_str(ctx));
+ } else if (iol->ports[id_LSR].net == nullptr) {
+ connect_port(ctx, lsr, iol, id_LSR);
+ }
+ }
+ if (prim->ports.count(port))
+ disconnect_port(ctx, prim, port);
+ };
+
+ auto set_iologic_mode = [&](CellInfo *iol, std::string mode) {
+ auto &curr_mode = iol->params[ctx->id("MODE")];
+ if (curr_mode != "NONE" && curr_mode != "IREG_OREG" && curr_mode != mode)
+ log_error("IOLOGIC '%s' has conflicting modes '%s' and '%s'\n", iol->name.c_str(ctx), curr_mode.c_str(),
+ mode.c_str());
+ if (iol->type == id_SIOLOGIC && mode != "IREG_OREG" && mode != "IDDRX1_ODDRX1" && mode != "NONE")
+ log_error("IOLOGIC '%s' is set to mode '%s', but this is only supported for left and right IO\n",
+ iol->name.c_str(ctx), mode.c_str());
+ curr_mode = mode;
+ };
+
+ auto get_pio_bel = [&](CellInfo *pio, CellInfo *curr) {
+ if (!pio->attrs.count(ctx->id("BEL")))
+ log_error("IOLOGIC functionality (DDR, DELAY, DQS, etc) can only be used with pin-constrained PIO "
+ "(while processing '%s').\n",
+ curr->name.c_str(ctx));
+ BelId bel = ctx->getBelByName(ctx->id(pio->attrs.at(ctx->id("BEL"))));
+ NPNR_ASSERT(bel != BelId());
+ return bel;
+ };
+
+ auto create_pio_iologic = [&](CellInfo *pio, CellInfo *curr) {
+ BelId bel = get_pio_bel(pio, curr);
+ log_info("IOLOGIC component %s connected to PIO Bel %s\n", curr->name.c_str(ctx),
+ ctx->getBelName(bel).c_str(ctx));
+ Loc loc = ctx->getBelLocation(bel);
+ bool s = false;
+ if (loc.y == 0 || loc.y == (ctx->chip_info->height - 1))
+ s = true;
+ std::unique_ptr<CellInfo> iol =
+ create_ecp5_cell(ctx, s ? id_SIOLOGIC : id_IOLOGIC, pio->name.str(ctx) + "$IOL");
+
+ loc.z += s ? 2 : 4;
+ iol->attrs[ctx->id("BEL")] = ctx->getBelName(ctx->getBelByLocation(loc)).str(ctx);
+
+ CellInfo *iol_ptr = iol.get();
+ pio_iologic[pio->name] = iol_ptr;
+ new_cells.push_back(std::move(iol));
+ return iol_ptr;
+ };
+
+ auto process_dqs_port = [&](CellInfo *prim, CellInfo *pio, CellInfo *iol, IdString port) {
+ NetInfo *sig = nullptr;
+ if (prim->ports.count(port))
+ sig = prim->ports[port].net;
+ if (sig == nullptr || sig->driver.cell == nullptr)
+ log_error("Port %s of cell '%s' cannot be disconnected, it must be driven by a DQSBUFM\n",
+ port.c_str(ctx), prim->name.c_str(ctx));
+ if (iol->ports.at(port).net != nullptr) {
+ if (iol->ports.at(port).net != sig) {
+ log_error("IOLOGIC '%s' has conflicting %s signals '%s' and '%s'\n", iol->name.c_str(ctx),
+ port.c_str(ctx), iol->ports[port].net->name.c_str(ctx), sig->name.c_str(ctx));
+ }
+ disconnect_port(ctx, prim, port);
+ } else {
+ bool dqsr;
+ int dqsgroup;
+ bool has_dqs = ctx->getPIODQSGroup(get_pio_bel(pio, prim), dqsr, dqsgroup);
+ if (!has_dqs)
+ log_error("Primitive '%s' cannot be connected to top level port '%s' as the associated pin is not "
+ "in any DQS group",
+ prim->name.c_str(ctx), pio->name.c_str(ctx));
+ if (sig->driver.cell->type != id_DQSBUFM || sig->driver.port != port)
+ log_error("Port %s of cell '%s' must be driven by port %s of a DQSBUFM", port.c_str(ctx),
+ prim->name.c_str(ctx), port.c_str(ctx));
+ auto &driver_group = dqsbuf_dqsg.at(sig->driver.cell->name);
+ if (driver_group.first != dqsr || driver_group.second != dqsgroup)
+ log_error("DQS group mismatch, port %s of '%s' in group %cDQ%d is driven by DQSBUFM '%s' in group "
+ "%cDQ%d\n",
+ port.c_str(ctx), prim->name.c_str(ctx), dqsr ? 'R' : 'L', dqsgroup,
+ sig->driver.cell->name.c_str(ctx), driver_group.first ? 'R' : 'L', driver_group.second);
+ replace_port(prim, port, iol, port);
+ }
+ };
+
+ for (auto cell : sorted(ctx->cells)) {
+ CellInfo *ci = cell.second;
+ if (ci->type == ctx->id("DELAYF") || ci->type == ctx->id("DELAYG")) {
+ CellInfo *i_pio = net_driven_by(ctx, ci->ports.at(ctx->id("A")).net, is_trellis_io, id_O);
+ CellInfo *o_pio = net_only_drives(ctx, ci->ports.at(ctx->id("Z")).net, is_trellis_io, id_I, true);
+ CellInfo *iol = nullptr;
+ if (i_pio != nullptr && ci->ports.at(ctx->id("A")).net->users.size() == 1) {
+ iol = create_pio_iologic(i_pio, ci);
+ set_iologic_mode(iol, "IREG_OREG");
+ bool drives_iologic = false;
+ for (auto user : ci->ports.at(ctx->id("Z")).net->users)
+ if (is_iologic_input_cell(ctx, user.cell) && user.port == ctx->id("D"))
+ drives_iologic = true;
+ if (drives_iologic) {
+ // Reconnect to PIO which the packer expects later on
+ NetInfo *input_net = ci->ports.at(ctx->id("A")).net, *dly_net = ci->ports.at(ctx->id("Z")).net;
+ disconnect_port(ctx, i_pio, id_O);
+ i_pio->ports.at(id_O).net = nullptr;
+ disconnect_port(ctx, ci, id_A);
+ ci->ports.at(id_A).net = nullptr;
+ disconnect_port(ctx, ci, id_Z);
+ ci->ports.at(id_Z).net = nullptr;
+ connect_port(ctx, dly_net, i_pio, id_O);
+ connect_port(ctx, input_net, iol, id_INDD);
+ connect_port(ctx, input_net, iol, id_DI);
+ } else {
+ replace_port(ci, id_A, iol, id_PADDI);
+ replace_port(ci, id_Z, iol, id_INDD);
+ }
+ packed_cells.insert(cell.first);
+ } else if (o_pio != nullptr) {
+ iol = create_pio_iologic(o_pio, ci);
+ iol->params[ctx->id("DELAY.OUTDEL")] = "ENABLED";
+ bool driven_by_iol = false;
+ NetInfo *input_net = ci->ports.at(ctx->id("A")).net, *dly_net = ci->ports.at(ctx->id("Z")).net;
+ if (input_net->driver.cell != nullptr && is_iologic_output_cell(ctx, input_net->driver.cell) &&
+ input_net->driver.port == ctx->id("Q"))
+ driven_by_iol = true;
+ if (driven_by_iol) {
+ disconnect_port(ctx, o_pio, id_I);
+ o_pio->ports.at(id_I).net = nullptr;
+ disconnect_port(ctx, ci, id_A);
+ ci->ports.at(id_A).net = nullptr;
+ disconnect_port(ctx, ci, id_Z);
+ ci->ports.at(id_Z).net = nullptr;
+ connect_port(ctx, input_net, o_pio, id_I);
+ ctx->nets.erase(dly_net->name);
+ } else {
+ replace_port(ci, ctx->id("A"), iol, id_TXDATA0);
+ replace_port(ci, ctx->id("Z"), iol, id_IOLDO);
+ if (!o_pio->ports.count(id_IOLDO)) {
+ o_pio->ports[id_IOLDO].name = id_IOLDO;
+ o_pio->ports[id_IOLDO].type = PORT_IN;
+ }
+ replace_port(o_pio, id_I, o_pio, id_IOLDO);
+ }
+ packed_cells.insert(cell.first);
+ } else {
+ log_error("%s '%s' must be connected directly to top level input or output\n", ci->type.c_str(ctx),
+ ci->name.c_str(ctx));
+ }
+ iol->params[ctx->id("DELAY.DEL_VALUE")] =
+ std::to_string(lookup_delay(str_or_default(ci->params, ctx->id("DEL_MODE"), "USER_DEFINED")));
+ if (ci->params.count(ctx->id("DEL_VALUE")) &&
+ ci->params.at(ctx->id("DEL_VALUE")).substr(0, 5) != "DELAY")
+ iol->params[ctx->id("DELAY.DEL_VALUE")] = ci->params.at(ctx->id("DEL_VALUE"));
+ if (ci->ports.count(id_LOADN))
+ replace_port(ci, id_LOADN, iol, id_LOADN);
+ else
+ tie_zero(ci, id_LOADN);
+ if (ci->ports.count(id_MOVE))
+ replace_port(ci, id_MOVE, iol, id_MOVE);
+ else
+ tie_zero(ci, id_MOVE);
+ if (ci->ports.count(id_DIRECTION))
+ replace_port(ci, id_DIRECTION, iol, id_DIRECTION);
+ else
+ tie_zero(ci, id_DIRECTION);
+ if (ci->ports.count(id_CFLAG))
+ replace_port(ci, id_CFLAG, iol, id_CFLAG);
+ }
+ }
+
+ for (auto cell : sorted(ctx->cells)) {
+ CellInfo *ci = cell.second;
+ if (ci->type == ctx->id("IDDRX1F")) {
+ CellInfo *pio = net_driven_by(ctx, ci->ports.at(ctx->id("D")).net, is_trellis_io, id_O);
+ if (pio == nullptr || ci->ports.at(ctx->id("D")).net->users.size() > 1)
+ log_error("IDDRX1F '%s' D input must be connected only to a top level input\n",
+ ci->name.c_str(ctx));
+ CellInfo *iol;
+ if (pio_iologic.count(pio->name))
+ iol = pio_iologic.at(pio->name);
+ else
+ iol = create_pio_iologic(pio, ci);
+ set_iologic_mode(iol, "IDDRX1_ODDRX1");
+ replace_port(ci, ctx->id("D"), iol, id_PADDI);
+ set_iologic_sclk(iol, ci, ctx->id("SCLK"), true);
+ set_iologic_lsr(iol, ci, ctx->id("RST"), true);
+ replace_port(ci, ctx->id("Q0"), iol, id_RXDATA0);
+ replace_port(ci, ctx->id("Q1"), iol, id_RXDATA1);
+ iol->params[ctx->id("GSR")] = str_or_default(ci->params, ctx->id("GSR"), "DISABLED");
+ packed_cells.insert(cell.first);
+ } else if (ci->type == ctx->id("ODDRX1F")) {
+ CellInfo *pio = net_only_drives(ctx, ci->ports.at(ctx->id("Q")).net, is_trellis_io, id_I, true);
+ if (pio == nullptr)
+ log_error("ODDRX1F '%s' Q output must be connected only to a top level output\n",
+ ci->name.c_str(ctx));
+ CellInfo *iol;
+ if (pio_iologic.count(pio->name))
+ iol = pio_iologic.at(pio->name);
+ else
+ iol = create_pio_iologic(pio, ci);
+ set_iologic_mode(iol, "IDDRX1_ODDRX1");
+ replace_port(ci, ctx->id("Q"), iol, id_IOLDO);
+ if (!pio->ports.count(id_IOLDO)) {
+ pio->ports[id_IOLDO].name = id_IOLDO;
+ pio->ports[id_IOLDO].type = PORT_IN;
+ }
+ replace_port(pio, id_I, pio, id_IOLDO);
+ pio->params[ctx->id("DATAMUX_ODDR")] = "IOLDO";
+ set_iologic_sclk(iol, ci, ctx->id("SCLK"), false);
+ set_iologic_lsr(iol, ci, ctx->id("RST"), false);
+ replace_port(ci, ctx->id("D0"), iol, id_TXDATA0);
+ replace_port(ci, ctx->id("D1"), iol, id_TXDATA1);
+ iol->params[ctx->id("GSR")] = str_or_default(ci->params, ctx->id("GSR"), "DISABLED");
+ packed_cells.insert(cell.first);
+ } else if (ci->type == ctx->id("ODDRX2F")) {
+ CellInfo *pio = net_only_drives(ctx, ci->ports.at(ctx->id("Q")).net, is_trellis_io, id_I, true);
+ if (pio == nullptr)
+ log_error("ODDRX2F '%s' Q output must be connected only to a top level output\n",
+ ci->name.c_str(ctx));
+ CellInfo *iol;
+ if (pio_iologic.count(pio->name))
+ iol = pio_iologic.at(pio->name);
+ else
+ iol = create_pio_iologic(pio, ci);
+ set_iologic_mode(iol, "ODDRXN");
+ replace_port(ci, ctx->id("Q"), iol, id_IOLDO);
+ if (!pio->ports.count(id_IOLDO)) {
+ pio->ports[id_IOLDO].name = id_IOLDO;
+ pio->ports[id_IOLDO].type = PORT_IN;
+ }
+ replace_port(pio, id_I, pio, id_IOLDO);
+ set_iologic_sclk(iol, ci, ctx->id("SCLK"), false);
+ set_iologic_sclk(iol, ci, ctx->id("SCLK"), true);
+ set_iologic_eclk(iol, ci, id_ECLK);
+ set_iologic_lsr(iol, ci, ctx->id("RST"), false);
+ set_iologic_lsr(iol, ci, ctx->id("RST"), true);
+ replace_port(ci, ctx->id("D0"), iol, id_TXDATA0);
+ replace_port(ci, ctx->id("D1"), iol, id_TXDATA1);
+ replace_port(ci, ctx->id("D2"), iol, id_TXDATA2);
+ replace_port(ci, ctx->id("D3"), iol, id_TXDATA3);
+ iol->params[ctx->id("GSR")] = str_or_default(ci->params, ctx->id("GSR"), "DISABLED");
+ iol->params[ctx->id("ODDRXN.MODE")] = "ODDRX2";
+ pio->params[ctx->id("DATAMUX_ODDR")] = "IOLDO";
+ packed_cells.insert(cell.first);
+ } else if (ci->type == ctx->id("IDDRX2F")) {
+ CellInfo *pio = net_driven_by(ctx, ci->ports.at(ctx->id("D")).net, is_trellis_io, id_O);
+ if (pio == nullptr || ci->ports.at(ctx->id("D")).net->users.size() > 1)
+ log_error("IDDRX2F '%s' D input must be connected only to a top level input\n",
+ ci->name.c_str(ctx));
+ CellInfo *iol;
+ if (pio_iologic.count(pio->name))
+ iol = pio_iologic.at(pio->name);
+ else
+ iol = create_pio_iologic(pio, ci);
+ set_iologic_mode(iol, "IDDRXN");
+ replace_port(ci, ctx->id("D"), iol, id_PADDI);
+ set_iologic_sclk(iol, ci, ctx->id("SCLK"), true);
+ set_iologic_eclk(iol, ci, id_ECLK);
+ set_iologic_lsr(iol, ci, ctx->id("RST"), true);
+ replace_port(ci, ctx->id("Q0"), iol, id_RXDATA0);
+ replace_port(ci, ctx->id("Q1"), iol, id_RXDATA1);
+ replace_port(ci, ctx->id("Q2"), iol, id_RXDATA2);
+ replace_port(ci, ctx->id("Q3"), iol, id_RXDATA3);
+ iol->params[ctx->id("GSR")] = str_or_default(ci->params, ctx->id("GSR"), "DISABLED");
+ iol->params[ctx->id("IDDRXN.MODE")] = "IDDRX2";
+ packed_cells.insert(cell.first);
+ } else if (ci->type == ctx->id("OSHX2A")) {
+ CellInfo *pio = net_only_drives(ctx, ci->ports.at(ctx->id("Q")).net, is_trellis_io, id_I, true);
+ if (pio == nullptr)
+ log_error("OSHX2A '%s' Q output must be connected only to a top level output\n",
+ ci->name.c_str(ctx));
+ CellInfo *iol;
+ if (pio_iologic.count(pio->name))
+ iol = pio_iologic.at(pio->name);
+ else
+ iol = create_pio_iologic(pio, ci);
+ set_iologic_mode(iol, "MIDDRX_MODDRX");
+ replace_port(ci, ctx->id("Q"), iol, id_IOLDO);
+ if (!pio->ports.count(id_IOLDO)) {
+ pio->ports[id_IOLDO].name = id_IOLDO;
+ pio->ports[id_IOLDO].type = PORT_IN;
+ }
+ replace_port(pio, id_I, pio, id_IOLDO);
+ set_iologic_sclk(iol, ci, ctx->id("SCLK"), false);
+ set_iologic_eclk(iol, ci, id_ECLK);
+ set_iologic_lsr(iol, ci, ctx->id("RST"), false);
+ set_iologic_lsr(iol, ci, ctx->id("RST"), true);
+ replace_port(ci, ctx->id("D0"), iol, id_TXDATA0);
+ replace_port(ci, ctx->id("D1"), iol, id_TXDATA2);
+ iol->params[ctx->id("GSR")] = str_or_default(ci->params, ctx->id("GSR"), "DISABLED");
+ iol->params[ctx->id("MODDRX.MODE")] = "MOSHX2";
+ pio->params[ctx->id("DATAMUX_MDDR")] = "IOLDO";
+ packed_cells.insert(cell.first);
+ } else if (ci->type == ctx->id("ODDRX2DQA") || ci->type == ctx->id("ODDRX2DQSB")) {
+ CellInfo *pio = net_only_drives(ctx, ci->ports.at(ctx->id("Q")).net, is_trellis_io, id_I, true);
+ if (pio == nullptr)
+ log_error("%s '%s' Q output must be connected only to a top level output\n", ci->type.c_str(ctx),
+ ci->name.c_str(ctx));
+ CellInfo *iol;
+ if (pio_iologic.count(pio->name))
+ iol = pio_iologic.at(pio->name);
+ else
+ iol = create_pio_iologic(pio, ci);
+ set_iologic_mode(iol, "MIDDRX_MODDRX");
+ replace_port(ci, ctx->id("Q"), iol, id_IOLDO);
+ if (!pio->ports.count(id_IOLDO)) {
+ pio->ports[id_IOLDO].name = id_IOLDO;
+ pio->ports[id_IOLDO].type = PORT_IN;
+ }
+ replace_port(pio, id_I, pio, id_IOLDO);
+ set_iologic_sclk(iol, ci, ctx->id("SCLK"), false);
+ set_iologic_eclk(iol, ci, id_ECLK);
+ set_iologic_lsr(iol, ci, ctx->id("RST"), false);
+ set_iologic_lsr(iol, ci, ctx->id("RST"), true);
+ replace_port(ci, ctx->id("D0"), iol, id_TXDATA0);
+ replace_port(ci, ctx->id("D1"), iol, id_TXDATA1);
+ replace_port(ci, ctx->id("D2"), iol, id_TXDATA2);
+ replace_port(ci, ctx->id("D3"), iol, id_TXDATA3);
+ iol->params[ctx->id("GSR")] = str_or_default(ci->params, ctx->id("GSR"), "DISABLED");
+ iol->params[ctx->id("MODDRX.MODE")] = "MODDRX2";
+ iol->params[ctx->id("MIDDRX_MODDRX.WRCLKMUX")] = ci->type == ctx->id("ODDRX2DQSB") ? "DQSW" : "DQSW270";
+ process_dqs_port(ci, pio, iol, ci->type == ctx->id("ODDRX2DQSB") ? id_DQSW : id_DQSW270);
+ pio->params[ctx->id("DATAMUX_MDDR")] = "IOLDO";
+ packed_cells.insert(cell.first);
+ } else if (ci->type == ctx->id("IDDRX2DQA")) {
+ CellInfo *pio = net_driven_by(ctx, ci->ports.at(ctx->id("D")).net, is_trellis_io, id_O);
+ if (pio == nullptr || ci->ports.at(ctx->id("D")).net->users.size() > 1)
+ log_error("IDDRX2DQA '%s' D input must be connected only to a top level input\n",
+ ci->name.c_str(ctx));
+ CellInfo *iol;
+ if (pio_iologic.count(pio->name))
+ iol = pio_iologic.at(pio->name);
+ else
+ iol = create_pio_iologic(pio, ci);
+ set_iologic_mode(iol, "MIDDRX_MODDRX");
+ replace_port(ci, ctx->id("D"), iol, id_PADDI);
+ set_iologic_sclk(iol, ci, ctx->id("SCLK"), true);
+ set_iologic_eclk(iol, ci, id_ECLK);
+ set_iologic_lsr(iol, ci, ctx->id("RST"), true);
+ replace_port(ci, ctx->id("Q0"), iol, id_RXDATA0);
+ replace_port(ci, ctx->id("Q1"), iol, id_RXDATA1);
+ replace_port(ci, ctx->id("Q2"), iol, id_RXDATA2);
+ replace_port(ci, ctx->id("Q3"), iol, id_RXDATA3);
+ replace_port(ci, ctx->id("QWL"), iol, id_INFF);
+ iol->params[ctx->id("GSR")] = str_or_default(ci->params, ctx->id("GSR"), "DISABLED");
+ iol->params[ctx->id("MIDDRX.MODE")] = "MIDDRX2";
+ process_dqs_port(ci, pio, iol, id_DQSR90);
+ process_dqs_port(ci, pio, iol, id_RDPNTR2);
+ process_dqs_port(ci, pio, iol, id_RDPNTR1);
+ process_dqs_port(ci, pio, iol, id_RDPNTR0);
+ process_dqs_port(ci, pio, iol, id_WRPNTR2);
+ process_dqs_port(ci, pio, iol, id_WRPNTR1);
+ process_dqs_port(ci, pio, iol, id_WRPNTR0);
+ packed_cells.insert(cell.first);
+ } else if (ci->type == ctx->id("TSHX2DQA") || ci->type == ctx->id("TSHX2DQSA")) {
+ CellInfo *pio = net_only_drives(ctx, ci->ports.at(ctx->id("Q")).net, is_trellis_io, id_T, true);
+ if (pio == nullptr)
+ log_error("%s '%s' Q output must be connected only to a top level tristate\n", ci->type.c_str(ctx),
+ ci->name.c_str(ctx));
+ CellInfo *iol;
+ if (pio_iologic.count(pio->name))
+ iol = pio_iologic.at(pio->name);
+ else
+ iol = create_pio_iologic(pio, ci);
+ set_iologic_mode(iol, "MIDDRX_MODDRX");
+ replace_port(ci, ctx->id("Q"), iol, id_IOLTO);
+ if (!pio->ports.count(id_IOLTO)) {
+ pio->ports[id_IOLTO].name = id_IOLTO;
+ pio->ports[id_IOLTO].type = PORT_IN;
+ }
+ replace_port(pio, id_T, pio, id_IOLTO);
+ set_iologic_sclk(iol, ci, ctx->id("SCLK"), false);
+ set_iologic_eclk(iol, ci, id_ECLK);
+ set_iologic_lsr(iol, ci, ctx->id("RST"), false);
+ replace_port(ci, ctx->id("T0"), iol, id_TSDATA0);
+ replace_port(ci, ctx->id("T1"), iol, id_TSDATA1);
+ process_dqs_port(ci, pio, iol, ci->type == ctx->id("TSHX2DQSA") ? id_DQSW : id_DQSW270);
+ iol->params[ctx->id("GSR")] = str_or_default(ci->params, ctx->id("GSR"), "DISABLED");
+ iol->params[ctx->id("MTDDRX.MODE")] = "MTSHX2";
+ iol->params[ctx->id("MTDDRX.REGSET")] = "SET";
+ iol->params[ctx->id("MTDDRX.DQSW_INVERT")] = ci->type == ctx->id("TSHX2DQSA") ? "ENABLED" : "DISABLED";
+ iol->params[ctx->id("MIDDRX_MODDRX.WRCLKMUX")] = ci->type == ctx->id("TSHX2DQSA") ? "DQSW" : "DQSW270";
+ iol->params[ctx->id("IOLTOMUX")] = "TDDR";
+ packed_cells.insert(cell.first);
+ }
+ }
+ flush_cells();
+ // Promote/route edge clocks
+ for (auto cell : sorted(ctx->cells)) {
+ CellInfo *ci = cell.second;
+ if (ci->type == id_IOLOGIC || ci->type == id_DQSBUFM) {
+ if (!ci->ports.count(id_ECLK) || ci->ports.at(id_ECLK).net == nullptr)
+ continue;
+ BelId bel = ctx->getBelByName(ctx->id(str_or_default(ci->attrs, ctx->id("BEL"))));
+ NPNR_ASSERT(bel != BelId());
+ Loc pioLoc = ctx->getBelLocation(bel);
+ if (ci->type == id_DQSBUFM)
+ pioLoc.z -= 8;
+ else
+ pioLoc.z -= 4;
+ BelId pioBel = ctx->getBelByLocation(pioLoc);
+ NPNR_ASSERT(pioBel != BelId());
+ int bank = ctx->getPioBelBank(pioBel);
+ make_eclk(ci->ports.at(id_ECLK), ci, bel, bank);
+ }
+ }
+ flush_cells();
+ // Constrain ECLK-related cells
+ for (auto cell : sorted(ctx->cells)) {
+ CellInfo *ci = cell.second;
+ if (ci->type == id_CLKDIVF) {
+ const NetInfo *clki = net_or_nullptr(ci, id_CLKI);
+ for (auto &eclk : eclks) {
+ if (eclk.second.unbuf == clki) {
+ for (auto bel : ctx->getBels()) {
+ if (ctx->getBelType(bel) != id_CLKDIVF)
+ continue;
+ Loc loc = ctx->getBelLocation(bel);
+ // CLKDIVF for bank 6/7 on the left; for bank 2/3 on the right
+ if (loc.x < 10 && eclk.first.first != 6 && eclk.first.first != 7)
+ continue;
+ // z-index of CLKDIVF must match index of ECLK
+ if (loc.z != eclk.first.second)
+ continue;
+ ci->attrs[ctx->id("BEL")] = ctx->getBelName(bel).str(ctx);
+ make_eclk(ci->ports.at(id_CLKI), ci, bel, eclk.first.first);
+ goto clkdiv_done;
+ }
+ }
+ }
+ clkdiv_done:
+ continue;
+ } else if (ci->type == id_ECLKSYNCB) {
+ const NetInfo *eclko = net_or_nullptr(ci, id_ECLKO);
+ if (eclko == nullptr)
+ log_error("ECLKSYNCB '%s' has disconnected port ECLKO\n", ci->name.c_str(ctx));
+ for (auto user : eclko->users) {
+ if (user.cell->type == id_TRELLIS_ECLKBUF) {
+ Loc eckbuf_loc =
+ ctx->getBelLocation(ctx->getBelByName(ctx->id(user.cell->attrs.at(ctx->id("BEL")))));
+ for (auto bel : ctx->getBels()) {
+ if (ctx->getBelType(bel) != id_ECLKSYNCB)
+ continue;
+ Loc loc = ctx->getBelLocation(bel);
+ if (loc.x == eckbuf_loc.x && loc.y == eckbuf_loc.y && loc.z == eckbuf_loc.z - 2) {
+ ci->attrs[ctx->id("BEL")] = ctx->getBelName(bel).str(ctx);
+ goto eclksync_done;
+ }
+ }
+ }
+ }
+ eclksync_done:
+ continue;
+ } else if (ci->type == ctx->id("DDRDLLA")) {
+ ci->type = id_DDRDLL; // transform from Verilog to Bel name
+ const NetInfo *clk = net_or_nullptr(ci, id_CLK);
+ if (clk == nullptr)
+ log_error("DDRDLLA '%s' has disconnected port CLK\n", ci->name.c_str(ctx));
+ for (auto &eclk : eclks) {
+ if (eclk.second.unbuf == clk) {
+ for (auto bel : ctx->getBels()) {
+ if (ctx->getBelType(bel) != id_DDRDLL)
+ continue;
+ Loc loc = ctx->getBelLocation(bel);
+ int ddrdll_bank = -1;
+ if (loc.x < 15 && loc.y < 15)
+ ddrdll_bank = 7;
+ else if (loc.x < 15 && loc.y > 15)
+ ddrdll_bank = 6;
+ else if (loc.x > 15 && loc.y < 15)
+ ddrdll_bank = 2;
+ else if (loc.x > 15 && loc.y > 15)
+ ddrdll_bank = 3;
+ if (eclk.first.first != ddrdll_bank)
+ continue;
+ ci->attrs[ctx->id("BEL")] = ctx->getBelName(bel).str(ctx);
+ make_eclk(ci->ports.at(id_CLK), ci, bel, eclk.first.first);
+ goto ddrdll_done;
+ }
+ }
+ }
+ ddrdll_done:
+ continue;
+ }
+ }
+
+ flush_cells();
+ };
+
+ void generate_constraints()
+ {
+ log_info("Generating derived timing constraints...\n");
+ auto MHz = [&](delay_t a) { return 1000.0 / ctx->getDelayNS(a); };
+
+ auto equals_epsilon = [](delay_t a, delay_t b) { return (std::abs(a - b) / std::max(double(b), 1.0)) < 1e-3; };
+
+ std::unordered_set<IdString> user_constrained, changed_nets;
+ for (auto &net : ctx->nets) {
+ if (net.second->clkconstr != nullptr)
+ user_constrained.insert(net.first);
+ changed_nets.insert(net.first);
+ }
+ auto get_period = [&](CellInfo *ci, IdString port, delay_t &period) {
+ if (!ci->ports.count(port))
+ return false;
+ NetInfo *from = ci->ports.at(port).net;
+ if (from == nullptr || from->clkconstr == nullptr)
+ return false;
+ period = from->clkconstr->period.min_delay;
+ return true;
+ };
+
+ auto set_period = [&](CellInfo *ci, IdString port, delay_t period) {
+ if (!ci->ports.count(port))
+ return;
+ NetInfo *to = ci->ports.at(port).net;
+ if (to == nullptr)
+ return;
+ if (to->clkconstr != nullptr) {
+ if (!equals_epsilon(to->clkconstr->period.min_delay, period) && user_constrained.count(to->name))
+ log_warning(
+ " Overriding derived constraint of %.1f MHz on net %s with user-specified constraint of "
+ "%.1f MHz.\n",
+ MHz(to->clkconstr->period.min_delay), to->name.c_str(ctx), MHz(period));
+ return;
+ }
+ to->clkconstr = std::unique_ptr<ClockConstraint>(new ClockConstraint());
+ to->clkconstr->low.min_delay = period / 2;
+ to->clkconstr->low.max_delay = period / 2;
+ to->clkconstr->high.min_delay = period / 2;
+ to->clkconstr->high.max_delay = period / 2;
+ to->clkconstr->period.min_delay = period;
+ to->clkconstr->period.max_delay = period;
+ log_info(" Derived frequency constraint of %.1f MHz for net %s\n", MHz(to->clkconstr->period.min_delay),
+ to->name.c_str(ctx));
+ changed_nets.insert(to->name);
+ };
+
+ auto copy_constraint = [&](CellInfo *ci, IdString fromPort, IdString toPort, double ratio = 1.0) {
+ if (!ci->ports.count(fromPort) || !ci->ports.count(toPort))
+ return;
+ NetInfo *from = ci->ports.at(fromPort).net, *to = ci->ports.at(toPort).net;
+ if (from == nullptr || from->clkconstr == nullptr || to == nullptr)
+ return;
+ if (to->clkconstr != nullptr) {
+ if (!equals_epsilon(to->clkconstr->period.min_delay,
+ delay_t(from->clkconstr->period.min_delay / ratio)) &&
+ user_constrained.count(to->name))
+ log_warning(
+ " Overriding derived constraint of %.1f MHz on net %s with user-specified constraint of "
+ "%.1f MHz.\n",
+ MHz(to->clkconstr->period.min_delay), to->name.c_str(ctx),
+ MHz(delay_t(from->clkconstr->period.min_delay / ratio)));
+ return;
+ }
+ to->clkconstr = std::unique_ptr<ClockConstraint>(new ClockConstraint());
+ to->clkconstr->low = ctx->getDelayFromNS(ctx->getDelayNS(from->clkconstr->low.min_delay) / ratio);
+ to->clkconstr->high = ctx->getDelayFromNS(ctx->getDelayNS(from->clkconstr->high.min_delay) / ratio);
+ to->clkconstr->period = ctx->getDelayFromNS(ctx->getDelayNS(from->clkconstr->period.min_delay) / ratio);
+ log_info(" Derived frequency constraint of %.1f MHz for net %s\n", MHz(to->clkconstr->period.min_delay),
+ to->name.c_str(ctx));
+ changed_nets.insert(to->name);
+ };
+
+ // Run in a loop while constraints are changing to deal with dependencies
+ // Iteration limit avoids hanging in crazy loopback situation (self-fed PLLs or dividers, etc)
+ int iter = 0;
+ const int itermax = 5000;
+ while (!changed_nets.empty() && iter < itermax) {
+ ++iter;
+ std::unordered_set<IdString> changed_cells;
+ for (auto net : changed_nets)
+ for (auto &user : ctx->nets.at(net)->users)
+ if (user.port == id_CLKI || user.port == id_ECLKI)
+ changed_cells.insert(user.cell->name);
+ changed_nets.clear();
+ for (auto cell : sorted(changed_cells)) {
+ CellInfo *ci = ctx->cells.at(cell).get();
+ if (ci->type == id_CLKDIVF) {
+ std::string div = str_or_default(ci->params, ctx->id("DIV"), "2.0");
+ double ratio;
+ if (div == "2.0")
+ ratio = 1 / 2.0;
+ else if (div == "3.5")
+ ratio = 1 / 3.5;
+ else
+ log_error("Unsupported divider ratio '%s' on CLKDIVF '%s'\n", div.c_str(), ci->name.c_str(ctx));
+ copy_constraint(ci, id_CLKI, id_CDIVX, ratio);
+ } else if (ci->type == id_ECLKSYNCB || ci->type == id_TRELLIS_ECLKBUF) {
+ copy_constraint(ci, id_ECLKI, id_ECLKO, 1);
+ } else if (ci->type == id_EHXPLLL) {
+ delay_t period_in;
+ if (!get_period(ci, id_CLKI, period_in))
+ continue;
+ log_info(" Input frequency of PLL '%s' is constrained to %.1f MHz\n", ci->name.c_str(ctx),
+ MHz(period_in));
+ double period_in_div = period_in * int_or_default(ci->params, ctx->id("CLKI_DIV"), 1);
+ std::string path = str_or_default(ci->params, ctx->id("FEEDBK_PATH"), "CLKOP");
+ int feedback_div = int_or_default(ci->params, ctx->id("CLKFB_DIV"), 1);
+ if (path == "CLKOP" || path == "INT_OP")
+ feedback_div *= int_or_default(ci->params, ctx->id("CLKOP_DIV"), 1);
+ else if (path == "CLKOS" || path == "INT_OS")
+ feedback_div *= int_or_default(ci->params, ctx->id("CLKOS_DIV"), 1);
+ else if (path == "CLKOS2" || path == "INT_OS2")
+ feedback_div *= int_or_default(ci->params, ctx->id("CLKOS2_DIV"), 1);
+ else if (path == "CLKOS3" || path == "INT_OS3")
+ feedback_div *= int_or_default(ci->params, ctx->id("CLKOS3_DIV"), 1);
+ else {
+ log_info(" Unable to determine output frequencies for PLL '%s' with FEEDBK_PATH=%s\n",
+ ci->name.c_str(ctx), path.c_str());
+ continue;
+ }
+ double vco_period = period_in_div / feedback_div;
+ double vco_freq = MHz(vco_period);
+ if (vco_freq < 400 || vco_freq > 800)
+ log_info(" Derived VCO frequency %.1f MHz of PLL '%s' is out of legal range [400MHz, "
+ "800MHz]\n",
+ vco_freq, ci->name.c_str(ctx));
+ set_period(ci, id_CLKOP, vco_period * int_or_default(ci->params, ctx->id("CLKOP_DIV"), 1));
+ set_period(ci, id_CLKOS, vco_period * int_or_default(ci->params, ctx->id("CLKOS_DIV"), 1));
+ set_period(ci, id_CLKOS2, vco_period * int_or_default(ci->params, ctx->id("CLKOS2_DIV"), 1));
+ set_period(ci, id_CLKOS3, vco_period * int_or_default(ci->params, ctx->id("CLKOS3_DIV"), 1));
+ } else if (ci->type == id_OSCG) {
+ int div = int_or_default(ci->params, ctx->id("DIV"), 128);
+ set_period(ci, id_OSC, delay_t((1.0e6 / (2.0 * 155)) * div));
+ }
+ }
+ }
+ }
+
public:
void pack()
{
pack_io();
+ pack_dqsbuf();
+ pack_iologic();
pack_ebr();
pack_dsps();
pack_dcus();
+ pack_misc();
preplace_plls();
pack_constants();
pack_dram();
@@ -1394,6 +2395,7 @@ class Ecp5Packer
pack_lut_pairs();
pack_remaining_luts();
pack_remaining_ffs();
+ generate_constraints();
promote_ecp5_globals(ctx);
ctx->check();
}
@@ -1458,6 +2460,9 @@ void Arch::assignArchInfo()
ci->sliceInfo.clkmux = id(str_or_default(ci->params, id_CLKMUX, "CLK"));
ci->sliceInfo.lsrmux = id(str_or_default(ci->params, id_LSRMUX, "LSR"));
ci->sliceInfo.srmode = id(str_or_default(ci->params, id_SRMODE, "LSR_OVER_CE"));
+ ci->sliceInfo.is_carry = str_or_default(ci->params, id("MODE"), "LOGIC") == "CCU2";
+ ci->sliceInfo.sd0 = int_or_default(ci->params, id("REG0_SD"), 0);
+ ci->sliceInfo.sd1 = int_or_default(ci->params, id("REG1_SD"), 0);
ci->sliceInfo.has_l6mux = false;
if (ci->ports.count(id_FXA) && ci->ports[id_FXA].net != nullptr &&
ci->ports[id_FXA].net->driver.port == id_OFX0)
generated by cgit v1.2.3 (git 2.25.1) at 2025-04-24 02:42:02 +0000