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-rw-r--r--fpga_interchange/arch.cc30
1 files changed, 30 insertions, 0 deletions
diff --git a/fpga_interchange/arch.cc b/fpga_interchange/arch.cc
index c49a172b..938c4f2c 100644
--- a/fpga_interchange/arch.cc
+++ b/fpga_interchange/arch.cc
@@ -479,6 +479,32 @@ IdString Arch::getWireType(WireId wire) const
return IdString(chip_info->wire_types[wire_type].name);
}
+bool Arch::is_site_wire(WireId wire) const
+{
+ if (wire.tile == -1)
+ return false;
+ const auto &tile_type = loc_info(chip_info, wire);
+ return tile_type.wire_data[wire.index].site != -1;
+}
+
+WireCategory Arch::get_wire_category(WireId wire) const
+{
+ int tile = wire.tile, index = wire.index;
+ if (tile == -1) {
+ // Nodal wire
+ const TileWireRefPOD &wr = chip_info->nodes[wire.index].tile_wires[0];
+ tile = wr.tile;
+ index = wr.index;
+ }
+ auto &w2t = chip_info->tiles[tile].tile_wire_to_type;
+ if (index >= w2t.ssize())
+ return WIRE_CAT_GENERAL;
+ int wire_type = w2t[index];
+ if (wire_type == -1)
+ return WIRE_CAT_GENERAL;
+ return WireCategory(chip_info->wire_types[wire_type].category);
+}
+
std::vector<std::pair<IdString, std::string>> Arch::getWireAttrs(WireId wire) const { return {}; }
// -----------------------------------------------------------------------
@@ -773,6 +799,8 @@ bool Arch::place()
getCtx()->check();
#endif
+ place_globals();
+
std::string placer = str_or_default(settings, id("placer"), defaultPlacer);
if (placer == "heap") {
PlacerHeapCfg cfg(getCtx());
@@ -895,6 +923,8 @@ bool Arch::route()
// terminate at a BEL pin.
disallow_site_routing = true;
+ route_globals();
+
bool result;
if (router == "router1") {
result = router1(getCtx(), Router1Cfg(getCtx()));