aboutsummaryrefslogtreecommitdiffstats
path: root/fpga_interchange/arch.cc
diff options
context:
space:
mode:
Diffstat (limited to 'fpga_interchange/arch.cc')
-rw-r--r--fpga_interchange/arch.cc21
1 files changed, 19 insertions, 2 deletions
diff --git a/fpga_interchange/arch.cc b/fpga_interchange/arch.cc
index 1abf6f30..814e4f85 100644
--- a/fpga_interchange/arch.cc
+++ b/fpga_interchange/arch.cc
@@ -25,6 +25,7 @@
#include <cmath>
#include <cstring>
#include <queue>
+#include "fpga_interchange.h"
#include "log.h"
#include "nextpnr.h"
#include "placer1.h"
@@ -82,6 +83,10 @@ Arch::Arch(ArchArgs args) : args(args)
for (int32_t i = 0; i < cell_map.cell_names.ssize(); ++i) {
log_assert(cell_map.cell_names[i] == i + first_cell_id);
}
+
+ io_port_types.emplace(this->id("$nextpnr_ibuf"));
+ io_port_types.emplace(this->id("$nextpnr_obuf"));
+ io_port_types.emplace(this->id("$nextpnr_iobuf"));
}
// -----------------------------------------------------------------------
@@ -561,8 +566,14 @@ TimingClockingInfo Arch::getPortClockingInfo(const CellInfo *cell, IdString port
// -----------------------------------------------------------------------
-void Arch::read_logical_netlist(const std::string &filename) {}
-void Arch::write_physical_netlist(const std::string &filename) const {}
+void Arch::read_logical_netlist(const std::string &filename)
+{
+ FpgaInterchange::read_logical_netlist(getCtx(), filename);
+}
+void Arch::write_physical_netlist(const std::string &filename) const
+{
+ FpgaInterchange::write_physical_netlist(getCtx(), filename);
+}
void Arch::parse_xdc(const std::string &filename)
{
@@ -574,6 +585,12 @@ void Arch::parse_xdc(const std::string &filename)
}
}
+std::string Arch::get_part() const
+{
+ // FIXME: Need a map between device / package / speed grade and part.
+ return chip_info->name.get() + args.package + "-1";
+}
+
// -----------------------------------------------------------------------
#ifdef WITH_HEAP