1 files changed, 71 insertions, 3 deletions

diff --git a/fpga_interchange/dedicated_interconnect.cc b/fpga_interchange/dedicated_interconnect.cc
index 1254b367..56b6b706 100644
--- a/fpga_interchange/dedicated_interconnect.cc
+++ b/fpga_interchange/dedicated_interconnect.cc
@@ -39,6 +39,12 @@ enum WireNodeState
     IN_SOURCE_SITE = 2
 };
 
+enum ExpansionDirection
+{
+    EXPAND_DOWNHILL = 0,
+    EXPAND_UPHILL = 1
+};
+
 struct WireNode
 {
     WireId wire;
@@ -52,6 +58,50 @@ struct WireNode
 // interconnect.
 constexpr int kMaxDepth = 6;
 
+static uint32_t get_num_pips(const Context *ctx, WireId wire, ExpansionDirection direction)
+{
+    uint32_t num_pips = 0;
+
+    if (direction == EXPAND_DOWNHILL) {
+        for (PipId pip : ctx->getPipsDownhill(wire)) {
+            auto &pip_data = pip_info(ctx->chip_info, pip);
+            if (pip_data.pseudo_cell_wires.size() > 0)
+                continue;
+
+            if (ctx->getPipDstWire(pip) == WireId())
+                continue;
+
+            if (ctx->is_pip_synthetic(pip))
+                continue;
+
+            if (ctx->is_site_port(pip))
+                continue;
+
+            num_pips++;
+        }
+    } else {
+        NPNR_ASSERT(direction == EXPAND_UPHILL);
+        for (PipId pip : ctx->getPipsUphill(wire)) {
+            auto &pip_data = pip_info(ctx->chip_info, pip);
+            if (pip_data.pseudo_cell_wires.size() > 0)
+                continue;
+
+            if (ctx->getPipSrcWire(pip) == WireId())
+                continue;
+
+            if (ctx->is_pip_synthetic(pip))
+                continue;
+
+            if (ctx->is_site_port(pip))
+                continue;
+
+            num_pips++;
+        }
+    }
+
+    return num_pips;
+}
+
 void DedicatedInterconnect::init(const Context *ctx)
 {
     this->ctx = ctx;
@@ -99,6 +149,16 @@ bool DedicatedInterconnect::check_routing(BelId src_bel, IdString src_bel_pin, B
         WireNode node_to_expand = nodes_to_expand.back();
         nodes_to_expand.pop_back();
 
+        auto num_pips = get_num_pips(ctx, node_to_expand.wire, EXPAND_DOWNHILL);
+
+        // Usually, dedicated interconnects do not have more than one PIPs in the out-of-site
+        if (node_to_expand.depth > 1 && node_to_expand.state == IN_ROUTING && num_pips > 1) {
+            if (ctx->verbose)
+                log_info("Wire %s is on a non-dedicated path (number of pips %d)\n",
+                         ctx->nameOfWire(node_to_expand.wire), num_pips);
+            continue;
+        }
+
         for (PipId pip : ctx->getPipsDownhill(node_to_expand.wire)) {
             if (ctx->is_pip_synthetic(pip)) {
                 continue;
@@ -147,7 +207,7 @@ bool DedicatedInterconnect::check_routing(BelId src_bel, IdString src_bel_pin, B
 #ifdef DEBUG_EXPANSION
                         log_info(" - Not dedicated site routing because loop!");
 #endif
-                        return false;
+                        continue;
                     }
                     next_node.state = IN_SINK_SITE;
                     break;
@@ -365,6 +425,10 @@ bool DedicatedInterconnect::isBelLocationValid(BelId bel, const CellInfo *cell)
             continue;
         }
 
+        if (ctx->io_port_types.count(net->driver.cell->type)) {
+            continue;
+        }
+
         // Only check sink BELs.
         if (net->driver.cell == cell && net->driver.port == port_name) {
             if (!is_driver_on_net_valid(bel, cell, port_name, net)) {
@@ -394,15 +458,19 @@ void DedicatedInterconnect::explain_bel_status(BelId bel, const CellInfo *cell)
         // This net doesn't have a driver, probably not valid?
         NPNR_ASSERT(net->driver.cell != nullptr);
 
+        if (ctx->io_port_types.count(net->driver.cell->type)) {
+            continue;
+        }
+
         // Only check sink BELs.
         if (net->driver.cell == cell && net->driver.port == port_name) {
             if (!is_driver_on_net_valid(bel, cell, port_name, net)) {
-                log_info("Driver %s/%s is not valid on net '%s'", cell->name.c_str(ctx), port_name.c_str(ctx),
+                log_info("Driver %s/%s is not valid on net '%s'\n", cell->name.c_str(ctx), port_name.c_str(ctx),
                          net->name.c_str(ctx));
             }
         } else {
             if (!is_sink_on_net_valid(bel, cell, port_name, net)) {
-                log_info("Sink %s/%s is not valid on net '%s'", cell->name.c_str(ctx), port_name.c_str(ctx),
+                log_info("Sink %s/%s is not valid on net '%s'\n", cell->name.c_str(ctx), port_name.c_str(ctx),
                          net->name.c_str(ctx));
             }
         }