diff options
Diffstat (limited to 'fpga_interchange/examples/tests/const_wire')
4 files changed, 48 insertions, 0 deletions
diff --git a/fpga_interchange/examples/tests/const_wire/CMakeLists.txt b/fpga_interchange/examples/tests/const_wire/CMakeLists.txt new file mode 100644 index 00000000..163f4a97 --- /dev/null +++ b/fpga_interchange/examples/tests/const_wire/CMakeLists.txt @@ -0,0 +1,17 @@ +add_interchange_test( + name const_wire_basys3 + part xc7a35tcpg236-1 + package cpg236 + tcl run.tcl + xdc wire.xdc + sources wire.v +) + +add_interchange_test( + name const_wire_arty + part xc7a35tcsg324-1 + package csg324 + tcl run.tcl + xdc wire.xdc + sources wire.v +) diff --git a/fpga_interchange/examples/tests/const_wire/run.tcl b/fpga_interchange/examples/tests/const_wire/run.tcl new file mode 100644 index 00000000..b8d0df72 --- /dev/null +++ b/fpga_interchange/examples/tests/const_wire/run.tcl @@ -0,0 +1,14 @@ +yosys -import + +read_verilog $::env(SOURCES) + +synth_xilinx -nolutram -nowidelut -nosrl -nocarry -nodsp + +# opt_expr -undriven makes sure all nets are driven, if only by the $undef +# net. +opt_expr -undriven +opt_clean + +setundef -zero -params + +write_json $::env(OUT_JSON) diff --git a/fpga_interchange/examples/tests/const_wire/wire.v b/fpga_interchange/examples/tests/const_wire/wire.v new file mode 100644 index 00000000..5b1ab692 --- /dev/null +++ b/fpga_interchange/examples/tests/const_wire/wire.v @@ -0,0 +1,8 @@ +module top(output o, output o2, output o3, output o4); + +assign o = 1'b0; +assign o2 = 1'b1; +assign o3 = 1'b0; +assign o4 = 1'b1; + +endmodule diff --git a/fpga_interchange/examples/tests/const_wire/wire.xdc b/fpga_interchange/examples/tests/const_wire/wire.xdc new file mode 100644 index 00000000..0d96fc45 --- /dev/null +++ b/fpga_interchange/examples/tests/const_wire/wire.xdc @@ -0,0 +1,9 @@ +set_property PACKAGE_PIN N15 [get_ports o] +set_property PACKAGE_PIN N16 [get_ports o2] +set_property PACKAGE_PIN P17 [get_ports o3] +set_property PACKAGE_PIN R17 [get_ports o4] + +set_property IOSTANDARD LVCMOS33 [get_ports o] +set_property IOSTANDARD LVCMOS33 [get_ports o2] +set_property IOSTANDARD LVCMOS33 [get_ports o3] +set_property IOSTANDARD LVCMOS33 [get_ports o4] |