4 files changed, 43 insertions, 0 deletions
diff --git a/fpga_interchange/examples/tests/lut/CMakeLists.txt b/fpga_interchange/examples/tests/lut/CMakeLists.txt
new file mode 100644
index 00000000..4ec74b3d
--- /dev/null
+++ b/fpga_interchange/examples/tests/lut/CMakeLists.txt
@@ -0,0 +1,17 @@
+add_interchange_test(
+    name lut_basys3
+    part xc7a35tcpg236-1
+    package cpg236
+    tcl run.tcl
+    xdc lut.xdc
+    sources lut.v
+)
+
+add_interchange_test(
+    name lut_arty
+    part xc7a35tcsg324-1
+    package csg324
+    tcl run.tcl
+    xdc lut.xdc
+    sources lut.v
+)
diff --git a/fpga_interchange/examples/tests/lut/lut.v b/fpga_interchange/examples/tests/lut/lut.v
new file mode 100644
index 00000000..ca18e665
--- /dev/null
+++ b/fpga_interchange/examples/tests/lut/lut.v
@@ -0,0 +1,5 @@
+module top(input i0, input i1, output o);
+
+assign o = i0 | i1;
+
+endmodule
diff --git a/fpga_interchange/examples/tests/lut/lut.xdc b/fpga_interchange/examples/tests/lut/lut.xdc
new file mode 100644
index 00000000..4f390f25
--- /dev/null
+++ b/fpga_interchange/examples/tests/lut/lut.xdc
@@ -0,0 +1,7 @@
+set_property PACKAGE_PIN N16 [get_ports i0]
+set_property PACKAGE_PIN N15 [get_ports i1]
+set_property PACKAGE_PIN M17 [get_ports o]
+
+set_property IOSTANDARD LVCMOS33 [get_ports i0]
+set_property IOSTANDARD LVCMOS33 [get_ports i1]
+set_property IOSTANDARD LVCMOS33 [get_ports o]
diff --git a/fpga_interchange/examples/tests/lut/run.tcl b/fpga_interchange/examples/tests/lut/run.tcl
new file mode 100644
index 00000000..b8d0df72
--- /dev/null
+++ b/fpga_interchange/examples/tests/lut/run.tcl
@@ -0,0 +1,14 @@
+yosys -import
+
+read_verilog $::env(SOURCES)
+
+synth_xilinx -nolutram -nowidelut -nosrl -nocarry -nodsp
+
+# opt_expr -undriven makes sure all nets are driven, if only by the $undef
+# net.
+opt_expr -undriven
+opt_clean
+
+setundef -zero -params
+
+write_json $::env(OUT_JSON)