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-rw-r--r--fpga_interchange/examples/tests/wire/CMakeLists.txt9
-rw-r--r--fpga_interchange/examples/tests/wire/lifcl40evn.xdc5
-rw-r--r--fpga_interchange/examples/tests/wire/run_nexus.tcl14
3 files changed, 28 insertions, 0 deletions
diff --git a/fpga_interchange/examples/tests/wire/CMakeLists.txt b/fpga_interchange/examples/tests/wire/CMakeLists.txt
index 6308a6e9..9caffcd1 100644
--- a/fpga_interchange/examples/tests/wire/CMakeLists.txt
+++ b/fpga_interchange/examples/tests/wire/CMakeLists.txt
@@ -6,3 +6,12 @@ add_interchange_group_test(
sources wire.v
output_fasm
)
+
+add_interchange_group_test(
+ name wire
+ family ${family}
+ board_list lifcl40evn
+ tcl run_nexus.tcl
+ sources wire.v
+ skip_dcp
+)
diff --git a/fpga_interchange/examples/tests/wire/lifcl40evn.xdc b/fpga_interchange/examples/tests/wire/lifcl40evn.xdc
new file mode 100644
index 00000000..c1a87488
--- /dev/null
+++ b/fpga_interchange/examples/tests/wire/lifcl40evn.xdc
@@ -0,0 +1,5 @@
+set_property PACKAGE_PIN G19 [get_ports i]
+set_property PACKAGE_PIN E17 [get_ports o]
+
+set_property IOSTANDARD LVCMOS33 [get_ports i]
+set_property IOSTANDARD LVCMOS33 [get_ports o]
diff --git a/fpga_interchange/examples/tests/wire/run_nexus.tcl b/fpga_interchange/examples/tests/wire/run_nexus.tcl
new file mode 100644
index 00000000..cddad3f8
--- /dev/null
+++ b/fpga_interchange/examples/tests/wire/run_nexus.tcl
@@ -0,0 +1,14 @@
+yosys -import
+
+read_verilog $::env(SOURCES)
+
+synth_nexus -nolutram -nowidelut -nobram -noccu2 -nodsp
+
+# opt_expr -undriven makes sure all nets are driven, if only by the $undef
+# net.
+opt_expr -undriven
+opt_clean
+
+setundef -zero -params
+
+write_json $::env(OUT_JSON)