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-rw-r--r--fpga_interchange/examples/tests/wire/CMakeLists.txt18
-rw-r--r--fpga_interchange/examples/tests/wire/arty100t.xdc (renamed from fpga_interchange/examples/tests/wire/wire_arty.xdc)4
-rw-r--r--fpga_interchange/examples/tests/wire/arty35t.xdc5
-rw-r--r--fpga_interchange/examples/tests/wire/basys3.xdc (renamed from fpga_interchange/examples/tests/wire/wire_basys3.xdc)0
-rw-r--r--fpga_interchange/examples/tests/wire/nexys_video.xdc5
-rw-r--r--fpga_interchange/examples/tests/wire/zybo.xdc5
6 files changed, 20 insertions, 17 deletions
diff --git a/fpga_interchange/examples/tests/wire/CMakeLists.txt b/fpga_interchange/examples/tests/wire/CMakeLists.txt
index 59faf402..7b6567ae 100644
--- a/fpga_interchange/examples/tests/wire/CMakeLists.txt
+++ b/fpga_interchange/examples/tests/wire/CMakeLists.txt
@@ -1,19 +1,7 @@
-add_interchange_test(
- name wire_basys3
+add_interchange_group_test(
+ name wire
family ${family}
- device xc7a35t
- package cpg236
+ board_list basys3 arty35t zybo arty100t nexys_video
tcl run.tcl
- xdc wire_basys3.xdc
- sources wire.v
-)
-
-add_interchange_test(
- name wire_arty
- family ${family}
- device xc7a35t
- package csg324
- tcl run.tcl
- xdc wire_arty.xdc
sources wire.v
)
diff --git a/fpga_interchange/examples/tests/wire/wire_arty.xdc b/fpga_interchange/examples/tests/wire/arty100t.xdc
index c923f0fc..54c661c9 100644
--- a/fpga_interchange/examples/tests/wire/wire_arty.xdc
+++ b/fpga_interchange/examples/tests/wire/arty100t.xdc
@@ -1,5 +1,5 @@
-set_property PACKAGE_PIN N16 [get_ports i]
-set_property PACKAGE_PIN N15 [get_ports o]
+set_property PACKAGE_PIN A8 [get_ports i]
+set_property PACKAGE_PIN H5 [get_ports o]
set_property IOSTANDARD LVCMOS33 [get_ports i]
set_property IOSTANDARD LVCMOS33 [get_ports o]
diff --git a/fpga_interchange/examples/tests/wire/arty35t.xdc b/fpga_interchange/examples/tests/wire/arty35t.xdc
new file mode 100644
index 00000000..54c661c9
--- /dev/null
+++ b/fpga_interchange/examples/tests/wire/arty35t.xdc
@@ -0,0 +1,5 @@
+set_property PACKAGE_PIN A8 [get_ports i]
+set_property PACKAGE_PIN H5 [get_ports o]
+
+set_property IOSTANDARD LVCMOS33 [get_ports i]
+set_property IOSTANDARD LVCMOS33 [get_ports o]
diff --git a/fpga_interchange/examples/tests/wire/wire_basys3.xdc b/fpga_interchange/examples/tests/wire/basys3.xdc
index 317d5acc..317d5acc 100644
--- a/fpga_interchange/examples/tests/wire/wire_basys3.xdc
+++ b/fpga_interchange/examples/tests/wire/basys3.xdc
diff --git a/fpga_interchange/examples/tests/wire/nexys_video.xdc b/fpga_interchange/examples/tests/wire/nexys_video.xdc
new file mode 100644
index 00000000..326f77cb
--- /dev/null
+++ b/fpga_interchange/examples/tests/wire/nexys_video.xdc
@@ -0,0 +1,5 @@
+set_property PACKAGE_PIN E22 [get_ports i]
+set_property PACKAGE_PIN T14 [get_ports o]
+
+set_property IOSTANDARD LVCMOS33 [get_ports i]
+set_property IOSTANDARD LVCMOS33 [get_ports o]
diff --git a/fpga_interchange/examples/tests/wire/zybo.xdc b/fpga_interchange/examples/tests/wire/zybo.xdc
new file mode 100644
index 00000000..072c19d2
--- /dev/null
+++ b/fpga_interchange/examples/tests/wire/zybo.xdc
@@ -0,0 +1,5 @@
+set_property PACKAGE_PIN G15 [get_ports i]
+set_property PACKAGE_PIN M14 [get_ports o]
+
+set_property IOSTANDARD LVCMOS33 [get_ports i]
+set_property IOSTANDARD LVCMOS33 [get_ports o]