4 files changed, 0 insertions, 32 deletions
diff --git a/fpga_interchange/examples/wire/Makefile b/fpga_interchange/examples/wire/Makefile
deleted file mode 100644
index 49194f53..00000000
--- a/fpga_interchange/examples/wire/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-DESIGN := wire
-DESIGN_TOP := top
-PACKAGE := csg324
-
-include ../template.mk
-
-build/wire.json: wire.v | build
-	yosys -c run.tcl
diff --git a/fpga_interchange/examples/wire/run.tcl b/fpga_interchange/examples/wire/run.tcl
deleted file mode 100644
index 9127be20..00000000
--- a/fpga_interchange/examples/wire/run.tcl
+++ /dev/null
@@ -1,14 +0,0 @@
-yosys -import
-
-read_verilog wire.v
-
-synth_xilinx -nolutram -nowidelut -nosrl -nocarry -nodsp
-
-# opt_expr -undriven makes sure all nets are driven, if only by the $undef
-# net.
-opt_expr -undriven
-opt_clean
-
-setundef -zero -params
-
-write_json build/wire.json
diff --git a/fpga_interchange/examples/wire/wire.v b/fpga_interchange/examples/wire/wire.v
deleted file mode 100644
index 429d05ff..00000000
--- a/fpga_interchange/examples/wire/wire.v
+++ /dev/null
@@ -1,5 +0,0 @@
-module top(input i, output o);
-
-assign o = i;
-
-endmodule
diff --git a/fpga_interchange/examples/wire/wire.xdc b/fpga_interchange/examples/wire/wire.xdc
deleted file mode 100644
index c923f0fc..00000000
--- a/fpga_interchange/examples/wire/wire.xdc
+++ /dev/null
@@ -1,5 +0,0 @@
-set_property PACKAGE_PIN N16 [get_ports i]
-set_property PACKAGE_PIN N15 [get_ports o]
-
-set_property IOSTANDARD LVCMOS33 [get_ports i]
-set_property IOSTANDARD LVCMOS33 [get_ports o]