3 files changed, 12 insertions, 5 deletions
diff --git a/fpga_interchange/examples/tests.cmake b/fpga_interchange/examples/tests.cmake
index 3c97fe26..48b1cee3 100644
--- a/fpga_interchange/examples/tests.cmake
+++ b/fpga_interchange/examples/tests.cmake
@@ -77,13 +77,14 @@ function(add_interchange_test)
 
     # Synthesis
     set(synth_json ${CMAKE_CURRENT_BINARY_DIR}/${name}.json)
+    set(synth_log ${CMAKE_CURRENT_BINARY_DIR}/${name}.json.log)
     add_custom_command(
         OUTPUT ${synth_json}
         COMMAND ${CMAKE_COMMAND} -E env
             SOURCES="${sources}"
             OUT_JSON=${synth_json}
             TECHMAP=${techmap}
-            yosys -c ${tcl}
+            yosys -c ${tcl} -l ${synth_log}
         DEPENDS ${sources} ${techmap} ${tcl}
     )
 
@@ -134,6 +135,7 @@ function(add_interchange_test)
     get_property(chipdb_bin_loc TARGET device-${device} PROPERTY CHIPDB_BIN_LOC)
 
     set(phys ${CMAKE_CURRENT_BINARY_DIR}/${name}.phys)
+    set(phys_log ${CMAKE_CURRENT_BINARY_DIR}/${name}.phys.log)
     add_custom_command(
         OUTPUT ${phys}
         COMMAND
@@ -143,6 +145,7 @@ function(add_interchange_test)
                 --netlist ${netlist}
                 --phys ${phys}
                 --package ${package}
+                --log ${phys_log}
         DEPENDS
             nextpnr-fpga_interchange
             ${netlist}
@@ -151,6 +154,7 @@ function(add_interchange_test)
             ${chipdb_bin_loc}
     )
 
+    set(phys_verbose_log ${CMAKE_CURRENT_BINARY_DIR}/${name}.phys.verbose.log)
     add_custom_target(
         test-${family}-${name}-phys-verbose
         COMMAND
@@ -161,6 +165,7 @@ function(add_interchange_test)
                 --phys ${phys}
                 --package ${package}
                 --verbose
+                --log ${phys_verbose_log}
         DEPENDS
             ${netlist}
             ${xdc}
diff --git a/fpga_interchange/examples/tests/counter/counter.v b/fpga_interchange/examples/tests/counter/counter.v
index 00f52a20..4b3f343b 100644
--- a/fpga_interchange/examples/tests/counter/counter.v
+++ b/fpga_interchange/examples/tests/counter/counter.v
@@ -1,13 +1,15 @@
 module top(input clk, input rst, output [7:4] io_led);
 
-reg [31:0] counter = 32'b0;
+localparam SIZE = 32;
 
-assign io_led = counter >> 22;
+reg [SIZE-1:0] counter = SIZE'b0;
+
+assign io_led = {counter[SIZE-1], counter[25:23]};
 
 always @(posedge clk)
 begin
     if(rst)
-        counter <= 32'b0;
+        counter <= SIZE'b0;
     else
         counter <= counter + 1;
 end
diff --git a/fpga_interchange/examples/tests/counter/run_xilinx.tcl b/fpga_interchange/examples/tests/counter/run_xilinx.tcl
index ffea3b2e..c02cf933 100644
--- a/fpga_interchange/examples/tests/counter/run_xilinx.tcl
+++ b/fpga_interchange/examples/tests/counter/run_xilinx.tcl
@@ -2,7 +2,7 @@ yosys -import
 
 read_verilog $::env(SOURCES)
 
-synth_xilinx -nolutram -nowidelut -nosrl -nocarry -nodsp
+synth_xilinx -nolutram -nowidelut -nosrl -nodsp
 techmap -map $::env(TECHMAP)
 
 # opt_expr -undriven makes sure all nets are driven, if only by the $undef