diff options
Diffstat (limited to 'fpga_interchange')
31 files changed, 231 insertions, 87 deletions
diff --git a/fpga_interchange/arch.cc b/fpga_interchange/arch.cc index c1446245..441c2e1f 100644 --- a/fpga_interchange/arch.cc +++ b/fpga_interchange/arch.cc @@ -727,6 +727,7 @@ bool Arch::pack() decode_lut_cells(); merge_constant_nets(); pack_ports(); + pack_default_conns(); return true; } @@ -1984,6 +1985,58 @@ DelayQuad Arch::getPipDelay(PipId pip) const return DelayQuad(100 * (1 + pip_data.pseudo_cell_wires.size())); } +const DefaultCellConnsPOD *Arch::get_default_conns(IdString cell_type) const +{ + for (const auto &conn : chip_info->constants->default_conns) { + if (IdString(conn.cell_type) == cell_type) + return &conn; + } + return nullptr; +} + +void Arch::pack_default_conns() +{ + IdString vcc_net_name(chip_info->constants->vcc_net_name); + IdString gnd_net_name(chip_info->constants->gnd_net_name); + Context *ctx = getCtx(); + + std::vector<IdString> dead_nets; + + for (auto cell : sorted(ctx->cells)) { + CellInfo *ci = cell.second; + const DefaultCellConnsPOD *conns = get_default_conns(ci->type); + if (conns == nullptr) + continue; + for (const auto &pin : conns->pins) { + IdString pin_name(pin.pin_name); + // pin missing, create it + if (!ci->ports.count(pin_name)) + ci->addInput(pin_name); + const NetInfo *net = ci->ports.at(pin_name).net; + if (net != nullptr) { + // pin is connected, and driven, nothing to do + if (net->driver.cell != nullptr) + continue; + // pin is connected but undriven, disconnect the existing net + ctx->disconnectPort(ci->name, pin_name); + // remove net if it has no remaining users + if (net->users.empty()) + dead_nets.push_back(net->name); + } + if (pin.value == PIN_VALUE_GND) + ctx->connectPort(gnd_net_name, ci->name, pin_name); + else if (pin.value == PIN_VALUE_VCC) + ctx->connectPort(vcc_net_name, ci->name, pin_name); + else + NPNR_ASSERT(pin.value == PIN_VALUE_FLOAT); + } + } + + // Remove any left-behind nets with no users and no drivers + for (auto net : dead_nets) + ctx->nets.erase(net); +} + // Instance constraint templates. template void Arch::ArchConstraints::bindBel(Arch::ArchConstraints::TagState *, const Arch::ConstraintRange); template void Arch::ArchConstraints::unbindBel(Arch::ArchConstraints::TagState *, const Arch::ConstraintRange); diff --git a/fpga_interchange/arch.h b/fpga_interchange/arch.h index 9b369c92..da620699 100644 --- a/fpga_interchange/arch.h +++ b/fpga_interchange/arch.h @@ -1100,6 +1100,9 @@ struct Arch : ArchAPI<ArchRanges> void unmask_bel_pins(); void explain_bel_status(BelId bel) const; + + const DefaultCellConnsPOD *get_default_conns(IdString cell_type) const; + void pack_default_conns(); }; NEXTPNR_NAMESPACE_END diff --git a/fpga_interchange/arch_pybindings.cc b/fpga_interchange/arch_pybindings.cc index 4fddad93..68619866 100644 --- a/fpga_interchange/arch_pybindings.cc +++ b/fpga_interchange/arch_pybindings.cc @@ -44,6 +44,11 @@ void arch_wrap_python(py::module &m) .def("place", &Context::place) .def("route", &Context::route); + fn_wrapper_0a_v<Context, decltype(&Context::remove_site_routing), &Context::remove_site_routing>::def_wrap( + ctx_cls, "remove_site_routing"); + fn_wrapper_1a_v<Context, decltype(&Context::explain_bel_status), &Context::explain_bel_status, + conv_from_str<BelId>>::def_wrap(ctx_cls, "explain_bel_status"); + typedef std::unordered_map<IdString, std::unique_ptr<CellInfo>> CellMap; typedef std::unordered_map<IdString, std::unique_ptr<NetInfo>> NetMap; typedef std::unordered_map<IdString, IdString> AliasMap; diff --git a/fpga_interchange/cell_parameters.h b/fpga_interchange/cell_parameters.h index 3507a81f..de82e76b 100644 --- a/fpga_interchange/cell_parameters.h +++ b/fpga_interchange/cell_parameters.h @@ -42,7 +42,7 @@ struct CellParameters bool compare_property(const Context *ctx, IdString cell_type, IdString parameter, const Property &property, IdString value_to_compare) const; - HashTables::HashMap<std::pair<IdString, IdString>, const CellParameterPOD *> parameters; + HashTables::HashMap<std::pair<IdString, IdString>, const CellParameterPOD *, PairHash> parameters; std::regex verilog_binary_re; std::regex verilog_hex_re; diff --git a/fpga_interchange/chipdb.h b/fpga_interchange/chipdb.h index 6c7b8c83..b66640e3 100644 --- a/fpga_interchange/chipdb.h +++ b/fpga_interchange/chipdb.h @@ -34,7 +34,7 @@ NEXTPNR_NAMESPACE_BEGIN * kExpectedChipInfoVersion */ -static constexpr int32_t kExpectedChipInfoVersion = 6; +static constexpr int32_t kExpectedChipInfoVersion = 7; // Flattened site indexing. // @@ -255,6 +255,26 @@ NPNR_PACKED_STRUCT(struct PackagePOD { RelSlice<PackagePinPOD> pins; }); +enum CellPinValue +{ + // leave floating + PIN_VALUE_FLOAT = 0, + // connect to ground + PIN_VALUE_GND = 1, + // connect to vcc + PIN_VALUE_VCC = 2, +}; + +NPNR_PACKED_STRUCT(struct DefaultCellConnPOD { + int32_t pin_name; // constid + int32_t value; // CellPinValue +}); + +NPNR_PACKED_STRUCT(struct DefaultCellConnsPOD { + int32_t cell_type; // constid + RelSlice<DefaultCellConnPOD> pins; +}); + NPNR_PACKED_STRUCT(struct ConstantsPOD { // Cell type and port for the GND and VCC global source. int32_t gnd_cell_name; // constid @@ -280,6 +300,9 @@ NPNR_PACKED_STRUCT(struct ConstantsPOD { // If a choice is available, which constant net should be used? // Can be ''/0 if either constant net are equivilent. int32_t best_constant_net; // constid + + // Default cell pin connections + RelSlice<DefaultCellConnsPOD> default_conns; }); NPNR_PACKED_STRUCT(struct ChipInfoPOD { diff --git a/fpga_interchange/cost_map.cc b/fpga_interchange/cost_map.cc index b42f115d..868fdca0 100644 --- a/fpga_interchange/cost_map.cc +++ b/fpga_interchange/cost_map.cc @@ -121,7 +121,7 @@ delay_t CostMap::get_delay(const Context *ctx, WireId src_wire, WireId dst_wire) } void CostMap::set_cost_map(const Context *ctx, const TypeWirePair &wire_pair, - const HashTables::HashMap<std::pair<int32_t, int32_t>, delay_t> &delays) + const HashTables::HashMap<std::pair<int32_t, int32_t>, delay_t, PairHash> &delays) { CostMapEntry delay_matrix; diff --git a/fpga_interchange/cost_map.h b/fpga_interchange/cost_map.h index e57a1027..810d0198 100644 --- a/fpga_interchange/cost_map.h +++ b/fpga_interchange/cost_map.h @@ -39,7 +39,7 @@ class CostMap public: delay_t get_delay(const Context *ctx, WireId src, WireId dst) const; void set_cost_map(const Context *ctx, const TypeWirePair &wire_pair, - const HashTables::HashMap<std::pair<int32_t, int32_t>, delay_t> &delays); + const HashTables::HashMap<std::pair<int32_t, int32_t>, delay_t, PairHash> &delays); void from_reader(lookahead_storage::CostMap::Reader reader); void to_builder(lookahead_storage::CostMap::Builder builder) const; diff --git a/fpga_interchange/examples/boards.cmake b/fpga_interchange/examples/boards.cmake index c44ab930..3639080b 100644 --- a/fpga_interchange/examples/boards.cmake +++ b/fpga_interchange/examples/boards.cmake @@ -2,6 +2,7 @@ function(add_board) # ~~~ # add_board( # name <board name> + # device_family <device family> # device <common device> # package <package> # ) @@ -12,6 +13,8 @@ function(add_board) # # Arguments: # - name: name of the board. E.g. arty + # - device_family: the name of the family this device belongs to. + # E.g. the xc7a35t device belongs to the xc7 family # - device: common device name of a set of parts. E.g. xc7a35tcsg324-1 and xc7a35tcpg236-1 # share the same xc7a35t device prefix # - package: one of the packages available for a given device. E.g. cpg236 @@ -20,7 +23,7 @@ function(add_board) # - board-<name> set(options) - set(oneValueArgs name device package) + set(oneValueArgs name device_family device package) set(multiValueArgs) cmake_parse_arguments( @@ -32,6 +35,7 @@ function(add_board) ) set(name ${add_board_name}) + set(device_family ${add_board_device_family}) set(device ${add_board_device}) set(package ${add_board_package}) @@ -39,6 +43,7 @@ function(add_board) set_target_properties( board-${name} PROPERTIES + DEVICE_FAMILY ${device_family} DEVICE ${device} PACKAGE ${package} ) diff --git a/fpga_interchange/examples/boards/CMakeLists.txt b/fpga_interchange/examples/boards/CMakeLists.txt index 18c8f96b..89951058 100644 --- a/fpga_interchange/examples/boards/CMakeLists.txt +++ b/fpga_interchange/examples/boards/CMakeLists.txt @@ -1,29 +1,34 @@ add_board( name arty35t + device_family xc7 device xc7a35t package csg324 ) add_board( name arty100t + device_family xc7 device xc7a100t package csg324 ) add_board( name nexys_video + device_family xc7 device xc7a200t package sbg484 ) add_board( name basys3 + device_family xc7 device xc7a35t package cpg236 ) add_board( name zybo + device_family xc7 device xc7z010 package clg400 ) diff --git a/fpga_interchange/examples/tests.cmake b/fpga_interchange/examples/tests.cmake index 86148729..a5c31d6f 100644 --- a/fpga_interchange/examples/tests.cmake +++ b/fpga_interchange/examples/tests.cmake @@ -10,6 +10,8 @@ function(add_interchange_test) # sources <sources list> # [top <top name>] # [techmap <techmap file>] + # [output_fasm] + # [device_family <device family>] # ) # # Generates targets to run desired tests @@ -18,6 +20,8 @@ function(add_interchange_test) # - name: test name. This must be unique and no other tests with the same # name should exist # - family: nextpnr architecture family (e.g. fpga_interchange) + # - device_family: common device name of a set of parts. E.g. xc7a35tcsg324-1 and xc7a35tcpg236-1 + # share the same xc7a35t device prefix # - device: common device name of a set of parts. E.g. xc7a35tcsg324-1 and xc7a35tcpg236-1 # share the same xc7a35t device prefix # - package: package among the ones available for the device @@ -27,6 +31,9 @@ function(add_interchange_test) # - top (optional): name of the top level module. # If not provided, "top" is assigned as top level module # - techmap (optional): techmap file used during synthesis + # - output_fasm (optional): generates a fasm output + # - device_family (optional): this information is used during FASM generation, therfore it is + # required only if the `output_fasm` option is enabled # # Targets generated: # - test-fpga_interchange-<name>-json : synthesis output @@ -34,8 +41,8 @@ function(add_interchange_test) # - test-fpga_interchange-<name>-phys : interchange physical netlist # - test-fpga_interchange-<name>-dcp : design checkpoint with RapidWright - set(options skip_dcp) - set(oneValueArgs name family device package tcl xdc top techmap) + set(options skip_dcp output_fasm) + set(oneValueArgs name family device package tcl xdc top techmap device_family) set(multiValueArgs sources) cmake_parse_arguments( @@ -51,10 +58,12 @@ function(add_interchange_test) set(device ${add_interchange_test_device}) set(package ${add_interchange_test_package}) set(skip_dcp ${add_interchange_test_skip_dcp}) + set(output_fasm ${add_interchange_test_output_fasm}) set(top ${add_interchange_test_top}) set(tcl ${CMAKE_CURRENT_SOURCE_DIR}/${add_interchange_test_tcl}) set(xdc ${CMAKE_CURRENT_SOURCE_DIR}/${add_interchange_test_xdc}) set(techmap ${CMAKE_CURRENT_SOURCE_DIR}/${add_interchange_test_techmap}) + set(device_family ${add_interchange_test_device_family}) set(sources) foreach(source ${add_interchange_test_sources}) @@ -247,9 +256,9 @@ function(add_interchange_test) add_custom_target(test-${family}-${name}-phys-yaml DEPENDS ${phys_yaml}) + set(last_target "") if(skip_dcp) - add_dependencies(all-${family}-tests test-${family}-${name}-phys-yaml) - add_dependencies(all-${device}-tests test-${family}-${name}-phys-yaml) + set(last_target test-${family}-${name}-phys) else() set(dcp ${CMAKE_CURRENT_BINARY_DIR}/${name}.dcp) add_custom_command( @@ -266,8 +275,38 @@ function(add_interchange_test) ) add_custom_target(test-${family}-${name}-dcp DEPENDS ${dcp}) - add_dependencies(all-${family}-tests test-${family}-${name}-dcp) - add_dependencies(all-${device}-tests test-${family}-${name}-dcp) + set(last_target test-${family}-${name}-dcp) + endif() + + add_dependencies(all-${device}-tests ${last_target}) + add_dependencies(all-${family}-tests ${last_target}) + + if(output_fasm) + if(NOT DEFINED device_family) + message(FATAL_ERROR "If FASM output is enabled, the device family must be provided as well!") + endif() + + # Output FASM target + set(fasm ${CMAKE_CURRENT_BINARY_DIR}/${name}.fasm) + add_custom_command( + OUTPUT ${fasm} + COMMAND + ${PYTHON_EXECUTABLE} -mfpga_interchange.fasm_generator + --schema_dir ${INTERCHANGE_SCHEMA_PATH} + --family ${device_family} + ${device_loc} + ${netlist} + ${phys} + ${fasm} + DEPENDS + ${device_target} + ${netlist} + ${phys} + ) + + add_custom_target(test-${family}-${name}-fasm DEPENDS ${fasm} ${last_target}) + add_dependencies(all-${device}-tests test-${family}-${name}-fasm) + add_dependencies(all-${family}-tests test-${family}-${name}-fasm) endif() endfunction() @@ -301,7 +340,7 @@ function(add_interchange_group_test) # Note: it is assumed that there exists an XDC file for each board, with the following naming # convention: <board>.xdc - set(options) + set(options output_fasm) set(oneValueArgs name family tcl top techmap) set(multiValueArgs sources board_list) @@ -319,6 +358,13 @@ function(add_interchange_group_test) set(tcl ${add_interchange_group_test_tcl}) set(techmap ${add_interchange_group_test_techmap}) set(sources ${add_interchange_group_test_sources}) + set(output_fasm ${add_interchange_group_test_output_fasm}) + + set(output_fasm_arg "") + if(output_fasm) + set(output_fasm_arg "output_fasm") + endif() + if (NOT DEFINED top) # Setting default top value @@ -326,6 +372,7 @@ function(add_interchange_group_test) endif() foreach(board ${add_interchange_group_test_board_list}) + get_property(device_family TARGET board-${board} PROPERTY DEVICE_FAMILY) get_property(device TARGET board-${board} PROPERTY DEVICE) get_property(package TARGET board-${board} PROPERTY PACKAGE) @@ -333,12 +380,14 @@ function(add_interchange_group_test) name ${name}_${board} family ${family} device ${device} + device_family ${device_family} package ${package} tcl ${tcl} xdc ${board}.xdc sources ${sources} top ${top} techmap ${techmap} + ${output_fasm_arg} ) endforeach() endfunction() diff --git a/fpga_interchange/examples/tests/const_wire/CMakeLists.txt b/fpga_interchange/examples/tests/const_wire/CMakeLists.txt index ba013e47..3fff5fbb 100644 --- a/fpga_interchange/examples/tests/const_wire/CMakeLists.txt +++ b/fpga_interchange/examples/tests/const_wire/CMakeLists.txt @@ -1,19 +1,7 @@ -add_interchange_test( - name const_wire_basys3 +add_interchange_group_test( + name const_wire family ${family} - device xc7a35t - package cpg236 + board_list basys3 arty35t arty100t tcl run.tcl - xdc wire_basys3.xdc - sources wire.v -) - -add_interchange_test( - name const_wire_arty - family ${family} - device xc7a35t - package csg324 - tcl run.tcl - xdc wire_arty.xdc sources wire.v ) diff --git a/fpga_interchange/examples/tests/const_wire/wire_arty.xdc b/fpga_interchange/examples/tests/const_wire/arty100t.xdc index 0d96fc45..a6e69de5 100644 --- a/fpga_interchange/examples/tests/const_wire/wire_arty.xdc +++ b/fpga_interchange/examples/tests/const_wire/arty100t.xdc @@ -1,7 +1,7 @@ -set_property PACKAGE_PIN N15 [get_ports o] -set_property PACKAGE_PIN N16 [get_ports o2] -set_property PACKAGE_PIN P17 [get_ports o3] -set_property PACKAGE_PIN R17 [get_ports o4] +set_property PACKAGE_PIN H5 [get_ports o] +set_property PACKAGE_PIN J5 [get_ports o2] +set_property PACKAGE_PIN T9 [get_ports o3] +set_property PACKAGE_PIN T10 [get_ports o4] set_property IOSTANDARD LVCMOS33 [get_ports o] set_property IOSTANDARD LVCMOS33 [get_ports o2] diff --git a/fpga_interchange/examples/tests/const_wire/arty35t.xdc b/fpga_interchange/examples/tests/const_wire/arty35t.xdc new file mode 100644 index 00000000..a6e69de5 --- /dev/null +++ b/fpga_interchange/examples/tests/const_wire/arty35t.xdc @@ -0,0 +1,9 @@ +set_property PACKAGE_PIN H5 [get_ports o] +set_property PACKAGE_PIN J5 [get_ports o2] +set_property PACKAGE_PIN T9 [get_ports o3] +set_property PACKAGE_PIN T10 [get_ports o4] + +set_property IOSTANDARD LVCMOS33 [get_ports o] +set_property IOSTANDARD LVCMOS33 [get_ports o2] +set_property IOSTANDARD LVCMOS33 [get_ports o3] +set_property IOSTANDARD LVCMOS33 [get_ports o4] diff --git a/fpga_interchange/examples/tests/const_wire/wire_basys3.xdc b/fpga_interchange/examples/tests/const_wire/basys3.xdc index f8435580..f8435580 100644 --- a/fpga_interchange/examples/tests/const_wire/wire_basys3.xdc +++ b/fpga_interchange/examples/tests/const_wire/basys3.xdc diff --git a/fpga_interchange/examples/tests/counter/CMakeLists.txt b/fpga_interchange/examples/tests/counter/CMakeLists.txt index 2f1509c2..38c104ff 100644 --- a/fpga_interchange/examples/tests/counter/CMakeLists.txt +++ b/fpga_interchange/examples/tests/counter/CMakeLists.txt @@ -1,8 +1,9 @@ add_interchange_group_test( name counter family ${family} - board_list basys3 arty35t arty100t + board_list basys3 arty35t arty100t zybo tcl run.tcl sources counter.v techmap ../../remap.v + output_fasm ) diff --git a/fpga_interchange/examples/tests/counter/zybo.xdc b/fpga_interchange/examples/tests/counter/zybo.xdc new file mode 100644 index 00000000..e7764d52 --- /dev/null +++ b/fpga_interchange/examples/tests/counter/zybo.xdc @@ -0,0 +1,14 @@ +# zybo board +set_property PACKAGE_PIN K17 [get_ports clk] +set_property PACKAGE_PIN K18 [get_ports rst] +set_property PACKAGE_PIN M14 [get_ports io_led[4]] +set_property PACKAGE_PIN M15 [get_ports io_led[5]] +set_property PACKAGE_PIN G14 [get_ports io_led[6]] +set_property PACKAGE_PIN D18 [get_ports io_led[7]] + +set_property IOSTANDARD LVCMOS33 [get_ports clk] +set_property IOSTANDARD LVCMOS33 [get_ports rst] +set_property IOSTANDARD LVCMOS33 [get_ports io_led[4]] +set_property IOSTANDARD LVCMOS33 [get_ports io_led[5]] +set_property IOSTANDARD LVCMOS33 [get_ports io_led[6]] +set_property IOSTANDARD LVCMOS33 [get_ports io_led[7]] diff --git a/fpga_interchange/examples/tests/ff/CMakeLists.txt b/fpga_interchange/examples/tests/ff/CMakeLists.txt index ccf16d44..e119b7c3 100644 --- a/fpga_interchange/examples/tests/ff/CMakeLists.txt +++ b/fpga_interchange/examples/tests/ff/CMakeLists.txt @@ -1,19 +1,8 @@ -add_interchange_test( - name ff_basys3 +add_interchange_group_test( + name ff family ${family} - device xc7a35t - package cpg236 + board_list basys3 arty35t arty100t tcl run.tcl - xdc ff_basys3.xdc - sources ff.v -) - -add_interchange_test( - name ff_arty - family ${family} - device xc7a35t - package csg324 - tcl run.tcl - xdc ff_arty.xdc sources ff.v + output_fasm ) diff --git a/fpga_interchange/examples/tests/ff/ff_arty.xdc b/fpga_interchange/examples/tests/ff/arty100t.xdc index 3c132f1d..29456f2a 100644 --- a/fpga_interchange/examples/tests/ff/ff_arty.xdc +++ b/fpga_interchange/examples/tests/ff/arty100t.xdc @@ -1,7 +1,7 @@ -set_property PACKAGE_PIN P17 [get_ports clk] -set_property PACKAGE_PIN N15 [get_ports d] -set_property PACKAGE_PIN N16 [get_ports r] -set_property PACKAGE_PIN M17 [get_ports q] +set_property PACKAGE_PIN E3 [get_ports clk] +set_property PACKAGE_PIN A8 [get_ports d] +set_property PACKAGE_PIN D9 [get_ports r] +set_property PACKAGE_PIN H5 [get_ports q] set_property IOSTANDARD LVCMOS33 [get_ports clk] set_property IOSTANDARD LVCMOS33 [get_ports d] diff --git a/fpga_interchange/examples/tests/ff/arty35t.xdc b/fpga_interchange/examples/tests/ff/arty35t.xdc new file mode 100644 index 00000000..29456f2a --- /dev/null +++ b/fpga_interchange/examples/tests/ff/arty35t.xdc @@ -0,0 +1,9 @@ +set_property PACKAGE_PIN E3 [get_ports clk] +set_property PACKAGE_PIN A8 [get_ports d] +set_property PACKAGE_PIN D9 [get_ports r] +set_property PACKAGE_PIN H5 [get_ports q] + +set_property IOSTANDARD LVCMOS33 [get_ports clk] +set_property IOSTANDARD LVCMOS33 [get_ports d] +set_property IOSTANDARD LVCMOS33 [get_ports r] +set_property IOSTANDARD LVCMOS33 [get_ports q] diff --git a/fpga_interchange/examples/tests/ff/ff_basys3.xdc b/fpga_interchange/examples/tests/ff/basys3.xdc index ef65112a..ef65112a 100644 --- a/fpga_interchange/examples/tests/ff/ff_basys3.xdc +++ b/fpga_interchange/examples/tests/ff/basys3.xdc diff --git a/fpga_interchange/examples/tests/lut/CMakeLists.txt b/fpga_interchange/examples/tests/lut/CMakeLists.txt index f5503f71..77a4b4da 100644 --- a/fpga_interchange/examples/tests/lut/CMakeLists.txt +++ b/fpga_interchange/examples/tests/lut/CMakeLists.txt @@ -1,19 +1,8 @@ -add_interchange_test( - name lut_basys3 +add_interchange_group_test( + name lut family ${family} - device xc7a35t - package cpg236 + board_list basys3 arty35t arty100t tcl run.tcl - xdc lut_basys3.xdc - sources lut.v -) - -add_interchange_test( - name lut_arty - family ${family} - device xc7a35t - package csg324 - tcl run.tcl - xdc lut_arty.xdc sources lut.v + output_fasm ) diff --git a/fpga_interchange/examples/tests/lut/lut_arty.xdc b/fpga_interchange/examples/tests/lut/arty100t.xdc index 4f390f25..1dba6574 100644 --- a/fpga_interchange/examples/tests/lut/lut_arty.xdc +++ b/fpga_interchange/examples/tests/lut/arty100t.xdc @@ -1,6 +1,6 @@ -set_property PACKAGE_PIN N16 [get_ports i0] -set_property PACKAGE_PIN N15 [get_ports i1] -set_property PACKAGE_PIN M17 [get_ports o] +set_property PACKAGE_PIN A8 [get_ports i0] +set_property PACKAGE_PIN C11 [get_ports i1] +set_property PACKAGE_PIN H5 [get_ports o] set_property IOSTANDARD LVCMOS33 [get_ports i0] set_property IOSTANDARD LVCMOS33 [get_ports i1] diff --git a/fpga_interchange/examples/tests/lut/arty35t.xdc b/fpga_interchange/examples/tests/lut/arty35t.xdc new file mode 100644 index 00000000..1dba6574 --- /dev/null +++ b/fpga_interchange/examples/tests/lut/arty35t.xdc @@ -0,0 +1,7 @@ +set_property PACKAGE_PIN A8 [get_ports i0] +set_property PACKAGE_PIN C11 [get_ports i1] +set_property PACKAGE_PIN H5 [get_ports o] + +set_property IOSTANDARD LVCMOS33 [get_ports i0] +set_property IOSTANDARD LVCMOS33 [get_ports i1] +set_property IOSTANDARD LVCMOS33 [get_ports o] diff --git a/fpga_interchange/examples/tests/lut/lut_basys3.xdc b/fpga_interchange/examples/tests/lut/basys3.xdc index aef287ee..aef287ee 100644 --- a/fpga_interchange/examples/tests/lut/lut_basys3.xdc +++ b/fpga_interchange/examples/tests/lut/basys3.xdc diff --git a/fpga_interchange/examples/tests/ram/CMakeLists.txt b/fpga_interchange/examples/tests/ram/CMakeLists.txt index 4625edb3..56db4870 100644 --- a/fpga_interchange/examples/tests/ram/CMakeLists.txt +++ b/fpga_interchange/examples/tests/ram/CMakeLists.txt @@ -1,10 +1,8 @@ -add_interchange_test( - name ram_basys3 +add_interchange_group_test( + name ram family ${family} - device xc7a35t - package cpg236 + board_list basys3 tcl run.tcl - xdc basys3.xdc sources ram.v ) diff --git a/fpga_interchange/examples/tests/wire/CMakeLists.txt b/fpga_interchange/examples/tests/wire/CMakeLists.txt index 7b6567ae..6308a6e9 100644 --- a/fpga_interchange/examples/tests/wire/CMakeLists.txt +++ b/fpga_interchange/examples/tests/wire/CMakeLists.txt @@ -4,4 +4,5 @@ add_interchange_group_test( board_list basys3 arty35t zybo arty100t nexys_video tcl run.tcl sources wire.v + output_fasm ) diff --git a/fpga_interchange/family.cmake b/fpga_interchange/family.cmake index fdfa7004..14d86563 100644 --- a/fpga_interchange/family.cmake +++ b/fpga_interchange/family.cmake @@ -24,6 +24,7 @@ set(chipdb_dir ${CMAKE_CURRENT_BINARY_DIR}/${family}/chipdb) file(MAKE_DIRECTORY ${chipdb_dir}) add_custom_target(all-${family}-tests) +add_custom_target(all-${family}-fasm) add_custom_target(all-${family}-archcheck-tests) add_subdirectory(${family}/examples/devices) add_subdirectory(${family}/examples/boards) diff --git a/fpga_interchange/fpga_interchange.cpp b/fpga_interchange/fpga_interchange.cpp index 52d49fa2..60331382 100644 --- a/fpga_interchange/fpga_interchange.cpp +++ b/fpga_interchange/fpga_interchange.cpp @@ -1065,12 +1065,6 @@ ModuleReader::ModuleReader(const LogicalNetlistImpl *root, if(iter == net_indicies.end()) { PortKey port_key = port_connections.first; auto port = ports[port_key.port_idx]; - if(port_key.inst_idx != -1 && port.getDir() != LogicalNetlist::Netlist::Direction::OUTPUT) { - log_error("Cell instance %s port %s is disconnected!\n", - root->strings.at(root->root.getInstList()[port_key.inst_idx].getName()).c_str(), - root->strings.at(ports[port_key.port_idx].getName()).c_str() - ); - } disconnected_nets[net_idx] = stringf("%s.%d", root->strings.at(port.getName()).c_str(), i); } } diff --git a/fpga_interchange/lookahead.cc b/fpga_interchange/lookahead.cc index cd05c16f..6dc8c43a 100644 --- a/fpga_interchange/lookahead.cc +++ b/fpga_interchange/lookahead.cc @@ -250,7 +250,7 @@ static void expand_input_type(const Context *ctx, DeterministicRNG *rng, const S struct DelayStorage { - HashTables::HashMap<TypeWirePair, HashTables::HashMap<std::pair<int32_t, int32_t>, delay_t>> storage; + HashTables::HashMap<TypeWirePair, HashTables::HashMap<std::pair<int32_t, int32_t>, delay_t, PairHash>> storage; int32_t max_explore_depth; }; @@ -996,7 +996,8 @@ void Lookahead::build_lookahead(const Context *ctx, DeterministicRNG *rng) #if defined(NEXTPNR_USE_TBB) // Run parallely tbb::parallel_for_each( all_tiles_storage.storage, - [&](const std::pair<TypeWirePair, HashTables::HashMap<std::pair<int32_t, int32_t>, delay_t>> &type_pair) { + [&](const std::pair<TypeWirePair, HashTables::HashMap<std::pair<int32_t, int32_t>, delay_t, PairHash>> + &type_pair) { #else for (const auto &type_pair : all_tiles_storage.storage) { #endif diff --git a/fpga_interchange/pseudo_pip_model.h b/fpga_interchange/pseudo_pip_model.h index 53e2b3a3..1e79071d 100644 --- a/fpga_interchange/pseudo_pip_model.h +++ b/fpga_interchange/pseudo_pip_model.h @@ -98,7 +98,7 @@ struct PseudoPipData const std::vector<PseudoPipBel> &get_logic_bels_for_pip(const Context *ctx, int32_t site, PipId pip) const; HashTables::HashMap<int32_t, size_t> max_pseudo_pip_for_tile_type; - HashTables::HashMap<std::pair<int32_t, int32_t>, std::vector<size_t>> possibles_sites_for_pip; + HashTables::HashMap<std::pair<int32_t, int32_t>, std::vector<size_t>, PairHash> possibles_sites_for_pip; HashTables::HashMap<LogicBelKey, std::vector<PseudoPipBel>> logic_bels_for_pip; }; diff --git a/fpga_interchange/site_router.cc b/fpga_interchange/site_router.cc index 51b8bef3..f8cc2208 100644 --- a/fpga_interchange/site_router.cc +++ b/fpga_interchange/site_router.cc @@ -988,7 +988,7 @@ static void apply_routing(Context *ctx, const SiteArch &site_arch) } static bool map_luts_in_site(const SiteInformation &site_info, - HashTables::HashSet<std::pair<IdString, IdString>> *blocked_wires) + HashTables::HashSet<std::pair<IdString, IdString>, PairHash> *blocked_wires) { const Context *ctx = site_info.ctx; const std::vector<LutElement> &lut_elements = ctx->lut_elements.at(site_info.tile_type); @@ -1031,7 +1031,7 @@ static bool map_luts_in_site(const SiteInformation &site_info, // Block outputs of unavailable LUTs to prevent site router from using them. static void block_lut_outputs(SiteArch *site_arch, - const HashTables::HashSet<std::pair<IdString, IdString>> &blocked_wires) + const HashTables::HashSet<std::pair<IdString, IdString>, PairHash> &blocked_wires) { const Context *ctx = site_arch->site_info->ctx; auto &tile_info = ctx->chip_info->tile_types[site_arch->site_info->tile_type]; @@ -1112,7 +1112,7 @@ bool SiteRouter::checkSiteRouting(const Context *ctx, const TileStatus &tile_sta } SiteInformation site_info(ctx, tile, site, cells_in_site); - HashTables::HashSet<std::pair<IdString, IdString>> blocked_wires; + HashTables::HashSet<std::pair<IdString, IdString>, PairHash> blocked_wires; if (!map_luts_in_site(site_info, &blocked_wires)) { site_ok = false; return site_ok; @@ -1190,7 +1190,7 @@ void SiteRouter::bindSiteRouting(Context *ctx) } SiteInformation site_info(ctx, tile, site, cells_in_site); - HashTables::HashSet<std::pair<IdString, IdString>> blocked_wires; + HashTables::HashSet<std::pair<IdString, IdString>, PairHash> blocked_wires; NPNR_ASSERT(map_luts_in_site(site_info, &blocked_wires)); SiteArch site_arch(&site_info); |