diff options
Diffstat (limited to 'fpga_interchange')
| -rw-r--r-- | fpga_interchange/arch_pack_clusters.cc | 2 | ||||
| -rw-r--r-- | fpga_interchange/macros.cc | 6 | ||||
| -rw-r--r-- | fpga_interchange/pseudo_pip_model.cc | 6 | ||||
| -rw-r--r-- | fpga_interchange/site_arch.cc | 4 | ||||
| -rw-r--r-- | fpga_interchange/site_router.cc | 2 |
5 files changed, 9 insertions, 11 deletions
diff --git a/fpga_interchange/arch_pack_clusters.cc b/fpga_interchange/arch_pack_clusters.cc index b003812e..31e0522b 100644 --- a/fpga_interchange/arch_pack_clusters.cc +++ b/fpga_interchange/arch_pack_clusters.cc @@ -901,7 +901,7 @@ void Arch::prepare_cluster(const ClusterPOD *cluster, uint32_t index) // reachable due to the fixed dedicated interconnect. // E.g.: The CI input of carry chains in 7series corresponds to the CIN bel port, // which can only be connected to the COUT output of the tile below. - disconnect_port(ctx, ci, sink_port); + ci->disconnectPort(sink_port); } } diff --git a/fpga_interchange/macros.cc b/fpga_interchange/macros.cc index aa7d3184..8f7f8231 100644 --- a/fpga_interchange/macros.cc +++ b/fpga_interchange/macros.cc @@ -99,9 +99,9 @@ void Arch::expand_macros() // TODO: case of multiple top level ports on the same net? NPNR_ASSERT(net == nullptr); // Use the corresponding pre-expansion port net - net = get_net_or_empty(cell, IdString(net_port.port)); + net = cell->getPort(IdString(net_port.port)); // Disconnect the original port pre-expansion - disconnect_port(ctx, cell, IdString(net_port.port)); + cell->disconnectPort(IdString(net_port.port)); } // If not on a top level port, create a new net if (net == nullptr) @@ -115,7 +115,7 @@ void Arch::expand_macros() ctx->cells.at(derived_name(ctx, cell->name, IdString(net_port.instance))).get(); inst_cell->ports[port_name].name = port_name; inst_cell->ports[port_name].type = PortType(net_port.dir); - connect_port(ctx, net, inst_cell, port_name); + inst_cell->connectPort(port_name, net); } } diff --git a/fpga_interchange/pseudo_pip_model.cc b/fpga_interchange/pseudo_pip_model.cc index 39718c65..7f2427c4 100644 --- a/fpga_interchange/pseudo_pip_model.cc +++ b/fpga_interchange/pseudo_pip_model.cc @@ -355,12 +355,11 @@ void PseudoPipModel::update_site(const Context *ctx, size_t site) NPNR_ASSERT(bel_data.lut_element != -1); - lut_thru_cells.emplace_back(); + lut_thru_cells.emplace_back(nullptr, IdString(), IdString(ctx->wire_lut->cell)); CellInfo &cell = lut_thru_cells.back(); cell.bel = bel; - cell.type = IdString(ctx->wire_lut->cell); NPNR_ASSERT(ctx->wire_lut->input_pins.size() == 1); cell.lut_cell.pins.push_back(IdString(ctx->wire_lut->input_pins[0])); @@ -384,7 +383,7 @@ void PseudoPipModel::update_site(const Context *ctx, size_t site) continue; } - lut_cells.emplace_back(); + lut_cells.emplace_back(nullptr, IdString(), ctx->wire_lut ? IdString(ctx->wire_lut->cell) : IdString()); CellInfo &cell = lut_cells.back(); cell.bel.tile = tile; @@ -393,7 +392,6 @@ void PseudoPipModel::update_site(const Context *ctx, size_t site) if (ctx->wire_lut == nullptr) continue; - cell.type = IdString(ctx->wire_lut->cell); NPNR_ASSERT(ctx->wire_lut->input_pins.size() == 1); cell.lut_cell.pins.push_back(IdString(ctx->wire_lut->input_pins[0])); diff --git a/fpga_interchange/site_arch.cc b/fpga_interchange/site_arch.cc index ac644465..f78e8af4 100644 --- a/fpga_interchange/site_arch.cc +++ b/fpga_interchange/site_arch.cc @@ -103,7 +103,8 @@ void SiteArch::archcheck() } } -SiteArch::SiteArch(const SiteInformation *site_info) : ctx(site_info->ctx), site_info(site_info) +SiteArch::SiteArch(const SiteInformation *site_info) + : ctx(site_info->ctx), site_info(site_info), blocking_net(site_info->ctx->id("$nextpnr_blocked_net")) { // Build list of input and output site ports // @@ -275,7 +276,6 @@ SiteArch::SiteArch(const SiteInformation *site_info) : ctx(site_info->ctx), site } } - blocking_net.name = ctx->id("$nextpnr_blocked_net"); blocking_site_net.net = &blocking_net; } diff --git a/fpga_interchange/site_router.cc b/fpga_interchange/site_router.cc index 08e950e2..4e3d460a 100644 --- a/fpga_interchange/site_router.cc +++ b/fpga_interchange/site_router.cc @@ -953,7 +953,7 @@ static void apply_constant_routing(Context *ctx, const SiteArch &site_arch, NetI new_cell->belStrength = STRENGTH_PLACER; ctx->tileStatus.at(inverting_bel.tile).boundcells[inverting_bel.index] = new_cell; - connect_port(ctx, net_before_inverter, new_cell, id_I); + new_cell->connectPort(id_I, net_before_inverter); // The original BEL pin is now routed, but only through the inverter. // Because the cell/net model doesn't allow for multiple source pins |