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-rw-r--r--generic/arch.h113
1 files changed, 68 insertions, 45 deletions
diff --git a/generic/arch.h b/generic/arch.h
index 2344d8b2..e96853f1 100644
--- a/generic/arch.h
+++ b/generic/arch.h
@@ -23,10 +23,12 @@
#include <map>
#include "arch_api.h"
+#include "base_arch.h"
#include "idstring.h"
#include "idstringlist.h"
#include "nextpnr_namespaces.h"
#include "nextpnr_types.h"
+#include "viaduct_api.h"
NEXTPNR_NAMESPACE_BEGIN
@@ -60,8 +62,6 @@ struct WireInfo
std::map<IdString, std::string> attrs;
NetInfo *bound_net;
std::vector<PipId> downhill, uphill;
- BelPin uphill_bel_pin;
- std::vector<BelPin> downhill_bel_pins;
std::vector<BelPin> bel_pins;
DecalXY decalxy;
int x, y;
@@ -111,23 +111,40 @@ struct CellTiming
dict<IdString, std::vector<TimingClockingInfo>> clockingInfo;
};
-struct ArchRanges
+template <typename TId> struct linear_range
+{
+ struct iterator
+ {
+ explicit iterator(int32_t index) : index(index){};
+ int32_t index;
+ bool operator==(const iterator &other) const { return index == other.index; }
+ bool operator!=(const iterator &other) const { return index != other.index; }
+ void operator++() { ++index; }
+ TId operator*() const { return TId(index); }
+ };
+ explicit linear_range(int32_t size) : size(size){};
+ int32_t size;
+ iterator begin() const { return iterator(0); }
+ iterator end() const { return iterator(size); }
+};
+
+struct ArchRanges : BaseArchRanges
{
using ArchArgsT = ArchArgs;
// Bels
- using AllBelsRangeT = const std::vector<BelId> &;
+ using AllBelsRangeT = linear_range<BelId>;
using TileBelsRangeT = const std::vector<BelId> &;
using BelAttrsRangeT = const std::map<IdString, std::string> &;
using BelPinsRangeT = std::vector<IdString>;
using CellBelPinRangeT = const std::vector<IdString> &;
// Wires
- using AllWiresRangeT = const std::vector<WireId> &;
+ using AllWiresRangeT = linear_range<WireId>;
using DownhillPipRangeT = const std::vector<PipId> &;
using UphillPipRangeT = const std::vector<PipId> &;
using WireBelPinRangeT = const std::vector<BelPin> &;
using WireAttrsRangeT = const std::map<IdString, std::string> &;
// Pips
- using AllPipsRangeT = const std::vector<PipId> &;
+ using AllPipsRangeT = linear_range<PipId>;
using PipAttrsRangeT = const std::map<IdString, std::string> &;
// Groups
using AllGroupsRangeT = std::vector<GroupId>;
@@ -143,21 +160,27 @@ struct ArchRanges
using BucketBelRangeT = std::vector<BelId>;
};
-struct Arch : ArchAPI<ArchRanges>
+struct Arch : BaseArch<ArchRanges>
{
std::string chipName;
+ std::unique_ptr<ViaductAPI> uarch{};
- dict<IdStringList, WireInfo> wires;
- dict<IdStringList, PipInfo> pips;
- dict<IdStringList, BelInfo> bels;
+ std::vector<WireInfo> wires;
+ std::vector<PipInfo> pips;
+ std::vector<BelInfo> bels;
dict<GroupId, GroupInfo> groups;
- // These functions include useful errors if not found
- WireInfo &wire_info(IdStringList wire);
- PipInfo &pip_info(IdStringList wire);
- BelInfo &bel_info(IdStringList wire);
+ WireInfo &wire_info(WireId wire) { return wires.at(wire.index); }
+ PipInfo &pip_info(PipId pip) { return pips.at(pip.index); }
+ BelInfo &bel_info(BelId bel) { return bels.at(bel.index); }
+
+ const WireInfo &wire_info(WireId wire) const { return wires.at(wire.index); }
+ const PipInfo &pip_info(PipId pip) const { return pips.at(pip.index); }
+ const BelInfo &bel_info(BelId bel) const { return bels.at(bel.index); }
- std::vector<IdStringList> bel_ids, wire_ids, pip_ids;
+ dict<IdStringList, WireId> wire_by_name;
+ dict<IdStringList, PipId> pip_by_name;
+ dict<IdStringList, BelId> bel_by_name;
dict<Loc, BelId> bel_by_loc;
std::vector<std::vector<std::vector<BelId>>> bels_by_tile;
@@ -170,17 +193,17 @@ struct Arch : ArchAPI<ArchRanges>
dict<IdString, CellTiming> cellTiming;
- void addWire(IdStringList name, IdString type, int x, int y);
- void addPip(IdStringList name, IdString type, IdStringList srcWire, IdStringList dstWire, delay_t delay, Loc loc);
+ WireId addWire(IdStringList name, IdString type, int x, int y);
+ PipId addPip(IdStringList name, IdString type, WireId srcWire, WireId dstWire, delay_t delay, Loc loc);
- void addBel(IdStringList name, IdString type, Loc loc, bool gb, bool hidden);
- void addBelInput(IdStringList bel, IdString name, IdStringList wire);
- void addBelOutput(IdStringList bel, IdString name, IdStringList wire);
- void addBelInout(IdStringList bel, IdString name, IdStringList wire);
+ BelId addBel(IdStringList name, IdString type, Loc loc, bool gb, bool hidden);
+ void addBelInput(BelId bel, IdString name, WireId wire);
+ void addBelOutput(BelId bel, IdString name, WireId wire);
+ void addBelInout(BelId bel, IdString name, WireId wire);
- void addGroupBel(IdStringList group, IdStringList bel);
- void addGroupWire(IdStringList group, IdStringList wire);
- void addGroupPip(IdStringList group, IdStringList pip);
+ void addGroupBel(IdStringList group, BelId bel);
+ void addGroupWire(IdStringList group, WireId wire);
+ void addGroupPip(IdStringList group, PipId pip);
void addGroupGroup(IdStringList group, IdStringList grp);
void addDecalGraphic(DecalId decal, const GraphicElement &graphic);
@@ -189,9 +212,9 @@ struct Arch : ArchAPI<ArchRanges>
void setBelDecal(BelId bel, DecalXY decalxy);
void setGroupDecal(GroupId group, DecalXY decalxy);
- void setWireAttr(IdStringList wire, IdString key, const std::string &value);
- void setPipAttr(IdStringList pip, IdString key, const std::string &value);
- void setBelAttr(IdStringList bel, IdString key, const std::string &value);
+ void setWireAttr(WireId wire, IdString key, const std::string &value);
+ void setPipAttr(PipId pip, IdString key, const std::string &value);
+ void setBelAttr(BelId bel, IdString key, const std::string &value);
void setLutK(int K);
void setDelayScaling(double scale, double offset);
@@ -234,7 +257,7 @@ struct Arch : ArchAPI<ArchRanges>
bool checkBelAvail(BelId bel) const override;
CellInfo *getBoundBelCell(BelId bel) const override;
CellInfo *getConflictingBelCell(BelId bel) const override;
- const std::vector<BelId> &getBels() const override;
+ linear_range<BelId> getBels() const override;
IdString getBelType(BelId bel) const override;
bool getBelHidden(BelId bel) const override;
const std::map<IdString, std::string> &getBelAttrs(BelId bel) const override;
@@ -255,7 +278,7 @@ struct Arch : ArchAPI<ArchRanges>
WireId getConflictingWireWire(WireId wire) const override { return wire; }
NetInfo *getConflictingWireNet(WireId wire) const override;
DelayQuad getWireDelay(WireId wire) const override { return DelayQuad(0); }
- const std::vector<WireId> &getWires() const override;
+ linear_range<WireId> getWires() const override;
const std::vector<BelPin> &getWireBelPins(WireId wire) const override;
PipId getPipByName(IdStringList name) const override;
@@ -270,7 +293,7 @@ struct Arch : ArchAPI<ArchRanges>
NetInfo *getBoundPipNet(PipId pip) const override;
WireId getConflictingPipWire(PipId pip) const override;
NetInfo *getConflictingPipNet(PipId pip) const override;
- const std::vector<PipId> &getPips() const override;
+ linear_range<PipId> getPips() const override;
Loc getPipLocation(PipId pip) const override;
WireId getPipSrcWire(PipId pip) const override;
WireId getPipDstWire(PipId pip) const override;
@@ -287,7 +310,7 @@ struct Arch : ArchAPI<ArchRanges>
const std::vector<GroupId> &getGroupGroups(GroupId group) const override;
delay_t estimateDelay(WireId src, WireId dst) const override;
- delay_t predictDelay(const NetInfo *net_info, const PortRef &sink) const override;
+ delay_t predictDelay(BelId src_bel, IdString src_pin, BelId dst_bel, IdString dst_pin) const override;
delay_t getDelayEpsilon() const override { return 0.001; }
delay_t getRipupDelayPenalty() const override { return 0.015; }
float getDelayNS(delay_t v) const override { return v; }
@@ -305,9 +328,11 @@ struct Arch : ArchAPI<ArchRanges>
std::vector<IdString> getCellTypes() const override
{
+ if (uarch)
+ return uarch->getCellTypes();
pool<IdString> cell_types;
for (auto bel : bels) {
- cell_types.insert(bel.second.type);
+ cell_types.insert(bel.type);
}
return std::vector<IdString>{cell_types.begin(), cell_types.end()};
@@ -319,9 +344,15 @@ struct Arch : ArchAPI<ArchRanges>
BelBucketId getBelBucketByName(IdString bucket) const override { return bucket; }
- BelBucketId getBelBucketForBel(BelId bel) const override { return getBelType(bel); }
+ BelBucketId getBelBucketForBel(BelId bel) const override
+ {
+ return uarch ? uarch->getBelBucketForBel(bel) : getBelType(bel);
+ }
- BelBucketId getBelBucketForCellType(IdString cell_type) const override { return cell_type; }
+ BelBucketId getBelBucketForCellType(IdString cell_type) const override
+ {
+ return uarch ? uarch->getBelBucketForCellType(cell_type) : cell_type;
+ }
std::vector<BelId> getBelsInBucket(BelBucketId bucket) const override
{
@@ -346,19 +377,11 @@ struct Arch : ArchAPI<ArchRanges>
// Get the TimingClockingInfo of a port
TimingClockingInfo getPortClockingInfo(const CellInfo *cell, IdString port, int index) const override;
- bool isValidBelForCellType(IdString cell_type, BelId bel) const override { return cell_type == getBelType(bel); }
- bool isBelLocationValid(BelId bel) const override;
-
- // TODO
- CellInfo *getClusterRootCell(ClusterId cluster) const override { NPNR_ASSERT_FALSE("unimplemented"); }
- ArcBounds getClusterBounds(ClusterId cluster) const override { NPNR_ASSERT_FALSE("unimplemented"); }
- Loc getClusterOffset(const CellInfo *cell) const override { NPNR_ASSERT_FALSE("unimplemented"); }
- bool isClusterStrict(const CellInfo *cell) const override { NPNR_ASSERT_FALSE("unimplemented"); }
- bool getClusterPlacement(ClusterId cluster, BelId root_bel,
- std::vector<std::pair<CellInfo *, BelId>> &placement) const override
+ bool isValidBelForCellType(IdString cell_type, BelId bel) const override
{
- NPNR_ASSERT_FALSE("unimplemented");
+ return uarch ? uarch->isValidBelForCellType(cell_type, bel) : cell_type == getBelType(bel);
}
+ bool isBelLocationValid(BelId bel) const override;
static const std::string defaultPlacer;
static const std::vector<std::string> availablePlacers;