diff options
Diffstat (limited to 'generic/examples')
| -rw-r--r-- | generic/examples/bitstream.py | 2 | ||||
| -rw-r--r-- | generic/examples/simple.py | 7 | ||||
| -rwxr-xr-x | generic/examples/simple.sh | 3 | ||||
| -rw-r--r-- | generic/examples/simple_timing.py | 26 |
4 files changed, 21 insertions, 17 deletions
diff --git a/generic/examples/bitstream.py b/generic/examples/bitstream.py index 1ab94f0c..7f0b5c07 100644 --- a/generic/examples/bitstream.py +++ b/generic/examples/bitstream.py @@ -14,4 +14,4 @@ param_map = { } with open("blinky.fasm", "w") as f: - write_fasm(ctx, param_map, f)
\ No newline at end of file + write_fasm(ctx, param_map, f) diff --git a/generic/examples/simple.py b/generic/examples/simple.py index 9339b68a..9379b505 100644 --- a/generic/examples/simple.py +++ b/generic/examples/simple.py @@ -9,6 +9,7 @@ for x in range(X): for z in range(N): ctx.addWire(name="X%dY%dZ%d_CLK" % (x, y, z), type="BEL_CLK", x=x, y=y) ctx.addWire(name="X%dY%dZ%d_Q" % (x, y, z), type="BEL_Q", x=x, y=y) + ctx.addWire(name="X%dY%dZ%d_F" % (x, y, z), type="BEL_F", x=x, y=y) for i in range(K): ctx.addWire(name="X%dY%dZ%d_I%d" % (x, y, z, i), type="BEL_I", x=x, y=y) # Local wires @@ -29,6 +30,7 @@ for x in range(X): ctx.addBelInput(bel="X%dY%d_SLICE%d" % (x, y, z), name="CLK", wire="X%dY%dZ%d_CLK" % (x, y, z)) for k in range(K): ctx.addBelInput(bel="X%dY%d_SLICE%d" % (x, y, z), name="I[%d]" % k, wire="X%dY%dZ%d_I%d" % (x, y, z, k)) + ctx.addBelOutput(bel="X%dY%d_SLICE%d" % (x, y, z), name="F", wire="X%dY%dZ%d_F" % (x, y, z)) ctx.addBelOutput(bel="X%dY%d_SLICE%d" % (x, y, z), name="Q", wire="X%dY%dZ%d_Q" % (x, y, z)) for x in range(X): @@ -48,6 +50,9 @@ for x in range(X): # Pips from bel outputs to locals def create_output_pips(dst, offset, skip): for i in range(offset % skip, N, skip): + src = "X%dY%dZ%d_F" % (x, y, i) + ctx.addPip(name="X%dY%d.%s.%s" % (x, y, src, dst), type="BEL_OUTPUT", + srcWire=src, dstWire=dst, delay=ctx.getDelayFromNS(0.05), loc=Loc(x, y, 0)) src = "X%dY%dZ%d_Q" % (x, y, i) ctx.addPip(name="X%dY%d.%s.%s" % (x, y, src, dst), type="BEL_OUTPUT", srcWire=src, dstWire=dst, delay=ctx.getDelayFromNS(0.05), loc=Loc(x, y, 0)) @@ -69,4 +74,4 @@ for x in range(X): create_neighbour_pips(dst, x, y+1, (l + 4) % Sl, Sl) create_neighbour_pips(dst, x+1, y-1, (l + 5) % Sl, Sl) create_neighbour_pips(dst, x+1, y, (l + 6) % Sl, Sl) - create_neighbour_pips(dst, x+1, y+1, (l + 7) % Sl, Sl)
\ No newline at end of file + create_neighbour_pips(dst, x+1, y+1, (l + 7) % Sl, Sl) diff --git a/generic/examples/simple.sh b/generic/examples/simple.sh index 8ae903f9..76bc6168 100755 --- a/generic/examples/simple.sh +++ b/generic/examples/simple.sh @@ -1,4 +1,5 @@ #!/usr/bin/env bash set -ex yosys -p "tcl ../synth/synth_generic.tcl 4 blinky.json" blinky.v -${NEXTPNR:-../../nextpnr-generic} --pre-pack simple.py --pre-place simple_timing.py --json blinky.json --post-route bitstream.py +${NEXTPNR:-../../nextpnr-generic} --pre-pack simple.py --pre-place simple_timing.py --json blinky.json --post-route bitstream.py --write pnrblinky.json +yosys -p "read_verilog -lib ../synth/prims.v; read_json pnrblinky.json; dump -o blinky.il; show -format png -prefix blinky" diff --git a/generic/examples/simple_timing.py b/generic/examples/simple_timing.py index 2ccb197e..1067b556 100644 --- a/generic/examples/simple_timing.py +++ b/generic/examples/simple_timing.py @@ -1,15 +1,13 @@ for cname, cell in ctx.cells: - if cell.type != "GENERIC_SLICE": - continue - if cname in ("$PACKER_GND", "$PACKER_VCC"): - continue - K = int(cell.params["K"]) - if int(cell.params["FF_USED"], 2) == 1: - ctx.addCellTimingClock(cell=cname, port="CLK") - for i in range(K): - ctx.addCellTimingSetupHold(cell=cname, port="I[%d]" % i, clock="CLK", - setup=ctx.getDelayFromNS(0.2), hold=ctx.getDelayFromNS(0)) - ctx.addCellTimingClockToOut(cell=cname, port="Q", clock="CLK", clktoq=ctx.getDelayFromNS(0.2)) - else: - for i in range(K): - ctx.addCellTimingDelay(cell=cname, fromPort="I[%d]" % i, toPort="Q", delay=ctx.getDelayFromNS(0.2))
\ No newline at end of file + if cell.type != "GENERIC_SLICE": + continue + if cname in ("$PACKER_GND", "$PACKER_VCC"): + continue + K = int(cell.params["K"]) + ctx.addCellTimingClock(cell=cname, port="CLK") + for i in range(K): + ctx.addCellTimingSetupHold(cell=cname, port="I[%d]" % i, clock="CLK", + setup=ctx.getDelayFromNS(0.2), hold=ctx.getDelayFromNS(0)) + ctx.addCellTimingClockToOut(cell=cname, port="Q", clock="CLK", clktoq=ctx.getDelayFromNS(0.2)) + for i in range(K): + ctx.addCellTimingDelay(cell=cname, fromPort="I[%d]" % i, toPort="F", delay=ctx.getDelayFromNS(0.2)) |