2 files changed, 6 insertions, 11 deletions
diff --git a/generic/arch.cc b/generic/arch.cc
index b7ec847e..447aaa35 100644
--- a/generic/arch.cc
+++ b/generic/arch.cc
@@ -62,28 +62,23 @@ void Arch::addAlias(IdString name, IdString srcWire, IdString dstWire, DelayInfo
     pip_ids.push_back(name);
 }
 
-void Arch::addBel(IdString name, IdString type, int x, int y, int z, bool gb)
+void Arch::addBel(IdString name, IdString type, Loc loc, bool gb)
 {
-    Loc loc;
-    loc.x = x;
-    loc.y = y;
-    loc.z = z;
-
     NPNR_ASSERT(bels.count(name) == 0);
     NPNR_ASSERT(bel_by_loc.count(loc) == 0);
     BelInfo &bi = bels[name];
     bi.name = name;
     bi.type = type;
-    bi.x = x;
-    bi.y = y;
-    bi.z = z;
+    bi.x = loc.x;
+    bi.y = loc.y;
+    bi.z = loc.z;
     bi.gb = gb;
 
     bel_ids.push_back(name);
     bel_ids_by_type[type].push_back(name);
 
     bel_by_loc[loc] = name;
-    bels_by_tile[x][y].push_back(name);
+    bels_by_tile[loc.x][loc.y].push_back(name);
 }
 
 void Arch::addBelInput(IdString bel, IdString name, IdString wire)
diff --git a/generic/arch.h b/generic/arch.h
index e1516569..f4ca4383 100644
--- a/generic/arch.h
+++ b/generic/arch.h
@@ -97,7 +97,7 @@ struct Arch : BaseCtx
     void addPip(IdString name, IdString srcWire, IdString dstWire, DelayInfo delay);
     void addAlias(IdString name, IdString srcWire, IdString dstWire, DelayInfo delay);
 
-    void addBel(IdString name, IdString type, int x, int y, int z, bool gb);
+    void addBel(IdString name, IdString type, Loc loc, bool gb);
     void addBelInput(IdString bel, IdString name, IdString wire);
     void addBelOutput(IdString bel, IdString name, IdString wire);
     void addBelInout(IdString bel, IdString name, IdString wire);