diff options
Diffstat (limited to 'generic')
| -rw-r--r-- | generic/arch.cc | 19 | ||||
| -rw-r--r-- | generic/arch.h | 10 | ||||
| -rw-r--r-- | generic/arch_pybindings.cc | 13 |
3 files changed, 19 insertions, 23 deletions
diff --git a/generic/arch.cc b/generic/arch.cc index 9b131959..ffbf00ba 100644 --- a/generic/arch.cc +++ b/generic/arch.cc @@ -129,7 +129,7 @@ void Arch::addBelInput(IdStringList bel, IdString name, IdStringList wire) { NPNR_ASSERT(bel_info(bel).pins.count(name) == 0); PinInfo &pi = bel_info(bel).pins[name]; - pi.name = name; + pi.name = IdStringList(name); pi.wire = wire; pi.type = PORT_IN; @@ -141,7 +141,7 @@ void Arch::addBelOutput(IdStringList bel, IdString name, IdStringList wire) { NPNR_ASSERT(bel_info(bel).pins.count(name) == 0); PinInfo &pi = bel_info(bel).pins[name]; - pi.name = name; + pi.name = IdStringList(name); pi.wire = wire; pi.type = PORT_OUT; @@ -153,7 +153,7 @@ void Arch::addBelInout(IdStringList bel, IdString name, IdStringList wire) { NPNR_ASSERT(bel_info(bel).pins.count(name) == 0); PinInfo &pi = bel_info(bel).pins[name]; - pi.name = name; + pi.name = IdStringList(name); pi.wire = wire; pi.type = PORT_INOUT; @@ -216,12 +216,9 @@ void Arch::setDelayScaling(double scale, double offset) args.delayOffset = offset; } -void Arch::addCellTimingClock(IdStringList cell, IdString port) -{ - cellTiming[cell].portClasses[port] = TMG_CLOCK_INPUT; -} +void Arch::addCellTimingClock(IdString cell, IdString port) { cellTiming[cell].portClasses[port] = TMG_CLOCK_INPUT; } -void Arch::addCellTimingDelay(IdStringList cell, IdString fromPort, IdString toPort, DelayInfo delay) +void Arch::addCellTimingDelay(IdString cell, IdString fromPort, IdString toPort, DelayInfo delay) { if (get_or_default(cellTiming[cell].portClasses, fromPort, TMG_IGNORE) == TMG_IGNORE) cellTiming[cell].portClasses[fromPort] = TMG_COMB_INPUT; @@ -230,7 +227,7 @@ void Arch::addCellTimingDelay(IdStringList cell, IdString fromPort, IdString toP cellTiming[cell].combDelays[CellDelayKey{fromPort, toPort}] = delay; } -void Arch::addCellTimingSetupHold(IdStringList cell, IdString port, IdString clock, DelayInfo setup, DelayInfo hold) +void Arch::addCellTimingSetupHold(IdString cell, IdString port, IdString clock, DelayInfo setup, DelayInfo hold) { TimingClockingInfo ci; ci.clock_port = clock; @@ -241,7 +238,7 @@ void Arch::addCellTimingSetupHold(IdStringList cell, IdString port, IdString clo cellTiming[cell].portClasses[port] = TMG_REGISTER_INPUT; } -void Arch::addCellTimingClockToOut(IdStringList cell, IdString port, IdString clock, DelayInfo clktoq) +void Arch::addCellTimingClockToOut(IdString cell, IdString port, IdString clock, DelayInfo clktoq) { TimingClockingInfo ci; ci.clock_port = clock; @@ -256,7 +253,7 @@ void Arch::addCellTimingClockToOut(IdStringList cell, IdString port, IdString cl Arch::Arch(ArchArgs args) : chipName("generic"), args(args) { // Dummy for empty decals - decal_graphics[IdString()]; + decal_graphics[DecalId()]; } void IdString::initialize_arch(const BaseCtx *ctx) {} diff --git a/generic/arch.h b/generic/arch.h index ab554d53..0d071078 100644 --- a/generic/arch.h +++ b/generic/arch.h @@ -141,7 +141,7 @@ struct Arch : BaseCtx std::vector<std::vector<int>> tileBelDimZ; std::vector<std::vector<int>> tilePipDimZ; - std::unordered_map<IdStringList, CellTiming> cellTiming; + std::unordered_map<IdString, CellTiming> cellTiming; void addWire(IdStringList name, IdString type, int x, int y); void addPip(IdStringList name, IdString type, IdStringList srcWire, IdStringList dstWire, DelayInfo delay, Loc loc); @@ -169,10 +169,10 @@ struct Arch : BaseCtx void setLutK(int K); void setDelayScaling(double scale, double offset); - void addCellTimingClock(IdStringList cell, IdString port); - void addCellTimingDelay(IdStringList cell, IdString fromPort, IdString toPort, DelayInfo delay); - void addCellTimingSetupHold(IdStringList cell, IdString port, IdString clock, DelayInfo setup, DelayInfo hold); - void addCellTimingClockToOut(IdStringList cell, IdString port, IdString clock, DelayInfo clktoq); + void addCellTimingClock(IdString cell, IdString port); + void addCellTimingDelay(IdString cell, IdString fromPort, IdString toPort, DelayInfo delay); + void addCellTimingSetupHold(IdString cell, IdString port, IdString clock, DelayInfo setup, DelayInfo hold); + void addCellTimingClockToOut(IdString cell, IdString port, IdString clock, DelayInfo clktoq); // --------------------------------------------------------------- // Common Arch API. Every arch must provide the following methods. diff --git a/generic/arch_pybindings.cc b/generic/arch_pybindings.cc index 4fc76c96..29e8bc53 100644 --- a/generic/arch_pybindings.cc +++ b/generic/arch_pybindings.cc @@ -212,17 +212,16 @@ void arch_wrap_python(py::module &m) pass_through<double>>::def_wrap(ctx_cls, "setDelayScaling", "scale"_a, "offset"_a); fn_wrapper_2a_v<Context, decltype(&Context::addCellTimingClock), &Context::addCellTimingClock, - conv_from_str<IdStringList>, conv_from_str<IdString>>::def_wrap(ctx_cls, "addCellTimingClock", - "cell"_a, "port"_a); + conv_from_str<IdString>, conv_from_str<IdString>>::def_wrap(ctx_cls, "addCellTimingClock", "cell"_a, + "port"_a); fn_wrapper_4a_v<Context, decltype(&Context::addCellTimingDelay), &Context::addCellTimingDelay, - conv_from_str<IdStringList>, conv_from_str<IdString>, conv_from_str<IdString>, + conv_from_str<IdString>, conv_from_str<IdString>, conv_from_str<IdString>, pass_through<DelayInfo>>::def_wrap(ctx_cls, "addCellTimingDelay", "cell"_a, "fromPort"_a, "toPort"_a, "delay"_a); fn_wrapper_5a_v<Context, decltype(&Context::addCellTimingSetupHold), &Context::addCellTimingSetupHold, - conv_from_str<IdStringList>, conv_from_str<IdString>, conv_from_str<IdString>, - pass_through<DelayInfo>, pass_through<DelayInfo>>::def_wrap(ctx_cls, "addCellTimingSetupHold", - "cell"_a, "port"_a, "clock"_a, - "setup"_a, "hold"_a); + conv_from_str<IdString>, conv_from_str<IdString>, conv_from_str<IdString>, pass_through<DelayInfo>, + pass_through<DelayInfo>>::def_wrap(ctx_cls, "addCellTimingSetupHold", "cell"_a, "port"_a, "clock"_a, + "setup"_a, "hold"_a); fn_wrapper_4a_v<Context, decltype(&Context::addCellTimingClockToOut), &Context::addCellTimingClockToOut, conv_from_str<IdString>, conv_from_str<IdString>, conv_from_str<IdString>, pass_through<DelayInfo>>::def_wrap(ctx_cls, "addCellTimingClockToOut", "cell"_a, "port"_a, |