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-rw-r--r--gowin/cells.cc82
1 files changed, 36 insertions, 46 deletions
diff --git a/gowin/cells.cc b/gowin/cells.cc
index dce3f456..d862458c 100644
--- a/gowin/cells.cc
+++ b/gowin/cells.cc
@@ -26,22 +26,12 @@
NEXTPNR_NAMESPACE_BEGIN
-void add_port(const Context *ctx, CellInfo *cell, IdString id, PortType dir)
-{
- NPNR_ASSERT(cell->ports.count(id) == 0);
- cell->ports[id] = PortInfo{id, nullptr, dir};
-}
-
std::unique_ptr<CellInfo> create_generic_cell(Context *ctx, IdString type, std::string name)
{
static int auto_idx = 0;
- std::unique_ptr<CellInfo> new_cell = std::unique_ptr<CellInfo>(new CellInfo());
- if (name.empty()) {
- new_cell->name = ctx->id("$nextpnr_" + type.str(ctx) + "_" + std::to_string(auto_idx++));
- } else {
- new_cell->name = ctx->id(name);
- }
- new_cell->type = type;
+ IdString name_id =
+ name.empty() ? ctx->id("$nextpnr_" + type.str(ctx) + "_" + std::to_string(auto_idx++)) : ctx->id(name);
+ auto new_cell = std::make_unique<CellInfo>(ctx, name_id, type);
if (type == id_SLICE) {
new_cell->params[id_INIT] = 0;
new_cell->params[id_FF_USED] = 0;
@@ -49,30 +39,30 @@ std::unique_ptr<CellInfo> create_generic_cell(Context *ctx, IdString type, std::
IdString names[4] = {id_A, id_B, id_C, id_D};
for (int i = 0; i < 4; i++) {
- add_port(ctx, new_cell.get(), names[i], PORT_IN);
+ new_cell->addInput(names[i]);
}
- add_port(ctx, new_cell.get(), id_CLK, PORT_IN);
+ new_cell->addInput(id_CLK);
- add_port(ctx, new_cell.get(), id_F, PORT_OUT);
- add_port(ctx, new_cell.get(), id_Q, PORT_OUT);
- add_port(ctx, new_cell.get(), id_CE, PORT_IN);
- add_port(ctx, new_cell.get(), id_LSR, PORT_IN);
+ new_cell->addOutput(id_F);
+ new_cell->addOutput(id_Q);
+ new_cell->addInput(id_CE);
+ new_cell->addInput(id_LSR);
} else if (type == id_GW_MUX2_LUT5 || type == id_GW_MUX2_LUT6 || type == id_GW_MUX2_LUT7 ||
type == id_GW_MUX2_LUT7 || type == id_GW_MUX2_LUT8) {
- add_port(ctx, new_cell.get(), id_I0, PORT_IN);
- add_port(ctx, new_cell.get(), id_I1, PORT_IN);
- add_port(ctx, new_cell.get(), id_SEL, PORT_IN);
- add_port(ctx, new_cell.get(), id_OF, PORT_OUT);
+ new_cell->addInput(id_I0);
+ new_cell->addInput(id_I1);
+ new_cell->addInput(id_SEL);
+ new_cell->addOutput(id_OF);
} else if (type == id_IOB || type == id_IOBS) {
new_cell->params[id_INPUT_USED] = 0;
new_cell->params[id_OUTPUT_USED] = 0;
new_cell->params[id_ENABLE_USED] = 0;
- add_port(ctx, new_cell.get(), id_PAD, PORT_INOUT);
- add_port(ctx, new_cell.get(), id_I, PORT_IN);
- add_port(ctx, new_cell.get(), id_OEN, PORT_IN);
- add_port(ctx, new_cell.get(), id_O, PORT_OUT);
+ new_cell->addInout(id_PAD);
+ new_cell->addInput(id_I);
+ new_cell->addInput(id_OEN);
+ new_cell->addOutput(id_O);
} else {
log_error("unable to create generic cell of type %s\n", type.c_str(ctx));
}
@@ -103,12 +93,12 @@ void lut_to_lc(const Context *ctx, CellInfo *lut, CellInfo *lc, bool no_dff)
IdString sim_names[4] = {id_I0, id_I1, id_I2, id_I3};
IdString wire_names[4] = {id_A, id_B, id_C, id_D};
for (int i = 0; i < 4; i++) {
- replace_port(lut, sim_names[i], lc, wire_names[i]);
+ lut->movePortTo(sim_names[i], lc, wire_names[i]);
}
if (no_dff) {
lc->params[id_FF_USED] = 0;
- replace_port(lut, id_F, lc, id_F);
+ lut->movePortTo(id_F, lc, id_F);
}
}
@@ -116,12 +106,12 @@ void dff_to_lc(const Context *ctx, CellInfo *dff, CellInfo *lc, bool pass_thru_l
{
lc->params[id_FF_USED] = 1;
lc->params[id_FF_TYPE] = dff->type.str(ctx);
- replace_port(dff, id_CLK, lc, id_CLK);
- replace_port(dff, id_CE, lc, id_CE);
- replace_port(dff, id_SET, lc, id_LSR);
- replace_port(dff, id_RESET, lc, id_LSR);
- replace_port(dff, id_CLEAR, lc, id_LSR);
- replace_port(dff, id_PRESET, lc, id_LSR);
+ dff->movePortTo(id_CLK, lc, id_CLK);
+ dff->movePortTo(id_CE, lc, id_CE);
+ dff->movePortTo(id_SET, lc, id_LSR);
+ dff->movePortTo(id_RESET, lc, id_LSR);
+ dff->movePortTo(id_CLEAR, lc, id_LSR);
+ dff->movePortTo(id_PRESET, lc, id_LSR);
if (pass_thru_lut) {
// Fill LUT with alternating 10
const int init_size = 1 << 4;
@@ -131,10 +121,10 @@ void dff_to_lc(const Context *ctx, CellInfo *dff, CellInfo *lc, bool pass_thru_l
init.append("10");
lc->params[id_INIT] = Property::from_string(init);
- replace_port(dff, id_D, lc, id_A);
+ dff->movePortTo(id_D, lc, id_A);
}
- replace_port(dff, id_Q, lc, id_Q);
+ dff->movePortTo(id_Q, lc, id_Q);
}
void gwio_to_iob(Context *ctx, CellInfo *nxio, CellInfo *iob, pool<IdString> &todelete_cells)
@@ -142,29 +132,29 @@ void gwio_to_iob(Context *ctx, CellInfo *nxio, CellInfo *iob, pool<IdString> &to
if (nxio->type == id_IBUF) {
if (iob->type == id_IOBS) {
// VCC -> OEN
- connect_port(ctx, ctx->nets[ctx->id("$PACKER_VCC_NET")].get(), iob, id_OEN);
+ iob->connectPort(id_OEN, ctx->nets[ctx->id("$PACKER_VCC_NET")].get());
}
iob->params[id_INPUT_USED] = 1;
- replace_port(nxio, id_O, iob, id_O);
+ nxio->movePortTo(id_O, iob, id_O);
} else if (nxio->type == id_OBUF) {
if (iob->type == id_IOBS) {
// VSS -> OEN
- connect_port(ctx, ctx->nets[ctx->id("$PACKER_GND_NET")].get(), iob, id_OEN);
+ iob->connectPort(id_OEN, ctx->nets[ctx->id("$PACKER_GND_NET")].get());
}
iob->params[id_OUTPUT_USED] = 1;
- replace_port(nxio, id_I, iob, id_I);
+ nxio->movePortTo(id_I, iob, id_I);
} else if (nxio->type == id_TBUF) {
iob->params[id_ENABLE_USED] = 1;
iob->params[id_OUTPUT_USED] = 1;
- replace_port(nxio, id_I, iob, id_I);
- replace_port(nxio, id_OEN, iob, id_OEN);
+ nxio->movePortTo(id_I, iob, id_I);
+ nxio->movePortTo(id_OEN, iob, id_OEN);
} else if (nxio->type == id_IOBUF) {
iob->params[id_ENABLE_USED] = 1;
iob->params[id_INPUT_USED] = 1;
iob->params[id_OUTPUT_USED] = 1;
- replace_port(nxio, id_I, iob, id_I);
- replace_port(nxio, id_O, iob, id_O);
- replace_port(nxio, id_OEN, iob, id_OEN);
+ nxio->movePortTo(id_I, iob, id_I);
+ nxio->movePortTo(id_O, iob, id_O);
+ nxio->movePortTo(id_OEN, iob, id_OEN);
} else {
NPNR_ASSERT(false);
}
generated by cgit v1.2.3 (git 2.25.1) at 2025-04-16 20:00:05 +0000