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-rw-r--r--ice40/arch.cc50
1 files changed, 43 insertions, 7 deletions
diff --git a/ice40/arch.cc b/ice40/arch.cc
index 91c20b42..4b28564a 100644
--- a/ice40/arch.cc
+++ b/ice40/arch.cc
@@ -141,18 +141,23 @@ Arch::Arch(ArchArgs args) : args(args)
#ifdef ICE40_HX1K_ONLY
if (args.type == ArchArgs::HX1K) {
+ fast_part = true;
chip_info = get_chip_info(reinterpret_cast<const RelPtr<ChipInfoPOD> *>(chipdb_blob_1k));
} else {
log_error("Unsupported iCE40 chip type.\n");
}
#else
if (args.type == ArchArgs::LP384) {
+ fast_part = false;
chip_info = get_chip_info(reinterpret_cast<const RelPtr<ChipInfoPOD> *>(chipdb_blob_384));
} else if (args.type == ArchArgs::LP1K || args.type == ArchArgs::HX1K) {
+ fast_part = args.type == ArchArgs::HX1K;
chip_info = get_chip_info(reinterpret_cast<const RelPtr<ChipInfoPOD> *>(chipdb_blob_1k));
} else if (args.type == ArchArgs::UP5K) {
+ fast_part = false;
chip_info = get_chip_info(reinterpret_cast<const RelPtr<ChipInfoPOD> *>(chipdb_blob_5k));
} else if (args.type == ArchArgs::LP8K || args.type == ArchArgs::HX8K) {
+ fast_part = args.type == ArchArgs::HX8K;
chip_info = get_chip_info(reinterpret_cast<const RelPtr<ChipInfoPOD> *>(chipdb_blob_8k));
} else {
log_error("Unsupported iCE40 chip type.\n");
@@ -600,9 +605,40 @@ delay_t Arch::predictDelay(WireId src, WireId dst) const
// offset = 500;
// }
+ // Estimate for output mux
+ for (const auto &bp : getWireBelPins(src)) {
+ if (bp.pin == PIN_O && getBelType(bp.bel) == TYPE_ICESTORM_LC) {
+ offset += 330;
+ break;
+ }
+ }
+
+ // Estimate for input mux
+ for (const auto &bp : getWireBelPins(dst)) {
+ if ((bp.pin == PIN_I0 || bp.pin == PIN_I1 || bp.pin == PIN_I2 || bp.pin == PIN_I3) &&
+ getBelType(bp.bel) == TYPE_ICESTORM_LC) {
+ offset += 260;
+ break;
+ }
+ }
+
return xscale * abs(xd) + yscale * abs(yd) + offset;
}
+delay_t Arch::getBudgetOverride(NetInfo *net_info, int user_idx, delay_t budget) const
+{
+ const auto &driver = net_info->driver;
+ if (driver.port == id_cout) {
+ const auto &sink = net_info->users[user_idx];
+ auto driver_loc = getBelLocation(driver.cell->bel);
+ auto sink_loc = getBelLocation(sink.cell->bel);
+ if (driver_loc.y == sink_loc.y)
+ return 0;
+ return 250;
+ }
+ return budget;
+}
+
// -----------------------------------------------------------------------
bool Arch::place() { return placer1(getCtx()); }
@@ -786,29 +822,29 @@ std::vector<GraphicElement> Arch::getDecalGraphics(DecalId decal) const
// -----------------------------------------------------------------------
-bool Arch::getCellDelay(const CellInfo *cell, IdString fromPort, IdString toPort, delay_t &delay) const
+bool Arch::getCellDelay(const CellInfo *cell, IdString fromPort, IdString toPort, DelayInfo &delay) const
{
if (cell->type == id_icestorm_lc) {
if ((fromPort == id_i0 || fromPort == id_i1 || fromPort == id_i2 || fromPort == id_i3) &&
(toPort == id_o || toPort == id_lo)) {
- delay = 450;
+ delay.delay = 450;
return true;
} else if (fromPort == id_cin && toPort == id_cout) {
- delay = 120;
+ delay.delay = 120;
return true;
} else if (fromPort == id_i1 && toPort == id_cout) {
- delay = 260;
+ delay.delay = 260;
return true;
} else if (fromPort == id_i2 && toPort == id_cout) {
- delay = 230;
+ delay.delay = 230;
return true;
} else if (fromPort == id_clk && toPort == id_o) {
- delay = 540;
+ delay.delay = 540;
return true;
}
} else if (cell->type == id_icestorm_ram) {
if (fromPort == id_rclk) {
- delay = 2140;
+ delay.delay = 2140;
return true;
}
}