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-rw-r--r--ice40/arch.h11
1 files changed, 9 insertions, 2 deletions
diff --git a/ice40/arch.h b/ice40/arch.h
index 2f2a0f30..871b25fb 100644
--- a/ice40/arch.h
+++ b/ice40/arch.h
@@ -108,6 +108,8 @@ NPNR_PACKED_STRUCT(struct WireInfoPOD {
};
RelPtr<char> name;
+ int32_t netidx;
+
int32_t num_uphill, num_downhill;
RelPtr<int32_t> pips_uphill, pips_downhill;
@@ -225,6 +227,7 @@ NPNR_PACKED_STRUCT(struct ChipInfoPOD {
RelPtr<BelConfigPOD> bel_config;
RelPtr<PackageInfoPOD> packages_data;
RelPtr<CellTimingPOD> cell_timing;
+ RelPtr<RelPtr<char>> tile_wire_names;
});
#if defined(_MSC_VER)
@@ -502,6 +505,8 @@ struct Arch : BaseCtx
return IdString(chip_info->bel_data[bel.index].type);
}
+ std::vector<std::pair<IdString, std::string>> getBelAttrs(BelId bel) const;
+
WireId getBelPinWire(BelId bel, IdString pin) const;
PortType getBelPinType(BelId bel, IdString pin) const;
std::vector<IdString> getBelPins(BelId bel) const;
@@ -517,6 +522,7 @@ struct Arch : BaseCtx
}
IdString getWireType(WireId wire) const;
+ std::vector<std::pair<IdString, std::string>> getWireAttrs(WireId wire) const;
uint32_t getWireChecksum(WireId wire) const { return wire.index; }
@@ -692,7 +698,8 @@ struct Arch : BaseCtx
IdString getPipName(PipId pip) const;
- IdString getPipType(PipId pip) const { return IdString(); }
+ IdString getPipType(PipId pip) const;
+ std::vector<std::pair<IdString, std::string>> getPipAttrs(PipId pip) const;
uint32_t getPipChecksum(PipId pip) const { return pip.index; }
@@ -812,7 +819,7 @@ struct Arch : BaseCtx
bool isBelLocationValid(BelId bel) const;
// Helper function for above
- bool logicCellsCompatible(const std::vector<const CellInfo *> &cells) const;
+ bool logicCellsCompatible(const CellInfo** it, const size_t size) const;
// -------------------------------------------------
// Assign architecure-specific arguments to nets and cells, which must be