1 files changed, 6 insertions, 7 deletions

diff --git a/ice40/bitstream.cc b/ice40/bitstream.cc
index 87a96a22..a62c6c09 100644
--- a/ice40/bitstream.cc
+++ b/ice40/bitstream.cc
@@ -92,7 +92,6 @@ char get_hexdigit(int i) { return std::string("0123456789ABCDEF").at(i); }
 
 void write_asc(const Context *ctx, std::ostream &out)
 {
-    auto &&proxy = ctx->rproxy();
     // [y][x][row][col]
     const ChipInfoPOD &ci = *ctx->chip_info;
     const BitstreamInfoPOD &bi = *ci.bits_info;
@@ -129,7 +128,7 @@ void write_asc(const Context *ctx, std::ostream &out)
     }
     // Set pips
     for (auto pip : ctx->getPips()) {
-        if (proxy.getBoundPipNet(pip) != IdString()) {
+        if (ctx->pip_to_net[pip.index] != IdString()) {
             const PipInfoPOD &pi = ci.pip_data[pip.index];
             const SwitchInfoPOD &swi = bi.switches[pi.switch_index];
             for (int i = 0; i < swi.num_bits; i++) {
@@ -200,8 +199,8 @@ void write_asc(const Context *ctx, std::ostream &out)
             NPNR_ASSERT(iez != -1);
 
             bool input_en = false;
-            if (!proxy.checkWireAvail(proxy.getWireBelPin(bel, PIN_D_IN_0)) ||
-                !proxy.checkWireAvail(proxy.getWireBelPin(bel, PIN_D_IN_1))) {
+            if ((ctx->wire_to_net[ctx->getWireBelPin(bel, PIN_D_IN_0).index] != IdString()) ||
+                (ctx->wire_to_net[ctx->getWireBelPin(bel, PIN_D_IN_1).index] != IdString())) {
                 input_en = true;
             }
 
@@ -272,7 +271,7 @@ void write_asc(const Context *ctx, std::ostream &out)
     }
     // Set config bits in unused IO and RAM
     for (auto bel : ctx->getBels()) {
-        if (proxy.checkBelAvail(bel) && ctx->getBelType(bel) == TYPE_SB_IO) {
+        if (ctx->bel_to_cell[bel.index] == IdString() && ctx->getBelType(bel) == TYPE_SB_IO) {
             const TileInfoPOD &ti = bi.tiles_nonrouting[TILE_IO];
             const BelInfoPOD &beli = ci.bel_data[bel.index];
             int x = beli.x, y = beli.y, z = beli.z;
@@ -285,7 +284,7 @@ void write_asc(const Context *ctx, std::ostream &out)
                     set_config(ti, config.at(iey).at(iex), "IoCtrl.REN_" + std::to_string(iez), false);
                 }
             }
-        } else if (proxy.checkBelAvail(bel) && ctx->getBelType(bel) == TYPE_ICESTORM_RAM) {
+        } else if (ctx->bel_to_cell[bel.index] == IdString() && ctx->getBelType(bel) == TYPE_ICESTORM_RAM) {
             const BelInfoPOD &beli = ci.bel_data[bel.index];
             int x = beli.x, y = beli.y;
             const TileInfoPOD &ti = bi.tiles_nonrouting[TILE_RAMB];
@@ -432,7 +431,7 @@ void write_asc(const Context *ctx, std::ostream &out)
     // Write symbols
     // const bool write_symbols = 1;
     for (auto wire : ctx->getWires()) {
-        IdString net = proxy.getBoundWireNet(wire);
+        IdString net = ctx->getBoundWireNet(wire);
         if (net != IdString())
             out << ".sym " << wire.index << " " << net.str(ctx) << std::endl;
     }