diff options
Diffstat (limited to 'ice40/bitstream.cc')
| -rw-r--r-- | ice40/bitstream.cc | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/ice40/bitstream.cc b/ice40/bitstream.cc index 23cd6af1..4991df5e 100644 --- a/ice40/bitstream.cc +++ b/ice40/bitstream.cc @@ -25,14 +25,14 @@ NEXTPNR_NAMESPACE_BEGIN inline TileType tile_at(const Chip &chip, int x, int y) { - return chip.chip_info.tile_grid[y * chip.chip_info.width + x]; + return chip.chip_info->tile_grid[y * chip.chip_info->width + x]; } const ConfigEntryPOD &find_config(const TileInfoPOD &tile, const std::string &name) { for (int i = 0; i < tile.num_config_entries; i++) { - if (std::string(tile.entries[i].name) == name) { + if (std::string(tile.entries[i].name.get()) == name) { return tile.entries[i]; } } @@ -99,7 +99,7 @@ void write_asc(const Design &design, std::ostream &out) { const Chip &chip = design.chip; // [y][x][row][col] - const ChipInfoPOD &ci = chip.chip_info; + const ChipInfoPOD &ci = *chip.chip_info; const BitstreamInfoPOD &bi = *ci.bits_info; std::vector<std::vector<std::vector<std::vector<int8_t>>>> config; config.resize(ci.height); @@ -161,7 +161,7 @@ void write_asc(const Design &design, std::ostream &out) const BelInfoPOD &beli = ci.bel_data[bel.index]; int x = beli.x, y = beli.y, z = beli.z; if (cell.second->type == "ICESTORM_LC") { - TileInfoPOD &ti = bi.tiles_nonrouting[TILE_LOGIC]; + const TileInfoPOD &ti = bi.tiles_nonrouting[TILE_LOGIC]; unsigned lut_init = get_param_or_def(cell.second, "LUT_INIT"); bool neg_clk = get_param_or_def(cell.second, "NEG_CLK"); bool dff_enable = get_param_or_def(cell.second, "DFF_ENABLE"); @@ -188,7 +188,7 @@ void write_asc(const Design &design, std::ostream &out) if (dff_enable) set_config(ti, config.at(y).at(x), "NegClk", neg_clk); } else if (cell.second->type == "SB_IO") { - TileInfoPOD &ti = bi.tiles_nonrouting[TILE_IO]; + const TileInfoPOD &ti = bi.tiles_nonrouting[TILE_IO]; unsigned pin_type = get_param_or_def(cell.second, "PIN_TYPE"); bool neg_trigger = get_param_or_def(cell.second, "NEG_TRIGGER"); bool pullup = get_param_or_def(cell.second, "PULLUP"); @@ -261,7 +261,7 @@ void write_asc(const Design &design, std::ostream &out) for (auto bel : chip.getBels()) { if (chip.bel_to_cell[bel.index] == IdString() && chip.getBelType(bel) == TYPE_SB_IO) { - TileInfoPOD &ti = bi.tiles_nonrouting[TILE_IO]; + const TileInfoPOD &ti = bi.tiles_nonrouting[TILE_IO]; const BelInfoPOD &beli = ci.bel_data[bel.index]; int x = beli.x, y = beli.y, z = beli.z; auto ieren = get_ieren(bi, x, y, z); @@ -280,7 +280,7 @@ void write_asc(const Design &design, std::ostream &out) chip.getBelType(bel) == TYPE_ICESTORM_RAM) { const BelInfoPOD &beli = ci.bel_data[bel.index]; int x = beli.x, y = beli.y; - TileInfoPOD &ti = bi.tiles_nonrouting[TILE_RAMB]; + const TileInfoPOD &ti = bi.tiles_nonrouting[TILE_RAMB]; if ((chip.args.type == ChipArgs::LP1K || chip.args.type == ChipArgs::HX1K)) { set_config(ti, config.at(y).at(x), "RamConfig.PowerUp", true); @@ -292,7 +292,7 @@ void write_asc(const Design &design, std::ostream &out) for (int y = 0; y < ci.height; y++) { for (int x = 0; x < ci.width; x++) { TileType tile = tile_at(chip, x, y); - TileInfoPOD &ti = bi.tiles_nonrouting[tile]; + const TileInfoPOD &ti = bi.tiles_nonrouting[tile]; // set all ColBufCtrl bits (FIXME) bool setColBufCtrl = true; |