3 files changed, 29 insertions, 11 deletions
diff --git a/ice40/carry_tests/.gitignore b/ice40/carry_tests/.gitignore
index 749cb303..427dd825 100644
--- a/ice40/carry_tests/.gitignore
+++ b/ice40/carry_tests/.gitignore
@@ -1,2 +1,4 @@
 *.vcd
 *_out.v
+*.out
+
diff --git a/ice40/carry_tests/counter_tb.v b/ice40/carry_tests/counter_tb.v
new file mode 100644
index 00000000..ede133a7
--- /dev/null
+++ b/ice40/carry_tests/counter_tb.v
@@ -0,0 +1,23 @@
+module counter_tb;
+    reg clk;
+    always #5 clk = (clk === 1'b0);
+
+    wire outa, outb, outc, outd;
+
+    chip uut (
+        .clk(clk),
+        .cen(1'b1),
+        .rst(1'b0),
+        .outa(outa),
+        .outb(outb),
+        .outc(outc),
+	.outd(outd)
+    );
+
+    initial begin
+        $dumpfile("counter_tb.vcd");
+        $dumpvars(0, counter_tb);
+        repeat (100000) @(posedge clk);
+        $finish;
+    end
+endmodule
diff --git a/ice40/carry_tests/test.sh b/ice40/carry_tests/test.sh
index 9f6b00b2..01aa4209 100755
--- a/ice40/carry_tests/test.sh
+++ b/ice40/carry_tests/test.sh
@@ -2,15 +2,8 @@
 set -ex
 NAME=${1%.v}
 yosys -p "synth_ice40 -top top; write_json ${NAME}.json" $1
-../../nextpnr-ice40 --force --json ${NAME}.json --pcf test.pcf --asc ${NAME}.asc --verbose ../../python/dump_design.py
-#icebox_vlog -p test.pcf ${NAME}.asc > ${NAME}_out.v
+../../nextpnr-ice40 --json ${NAME}.json --pcf test.pcf --asc ${NAME}.asc --verbose
+icebox_vlog -p test.pcf ${NAME}.asc > ${NAME}_out.v
+iverilog -o ${NAME}_sim.out ${NAME}_tb.v ${NAME}_out.v 
+vvp ${NAME}_sim.out
 
-#yosys -p "read_verilog +/ice40/cells_sim.v;\
-#          rename chip gate;\
-#          read_verilog $1;\
-#          rename top gold;\
-#          hierarchy;\
-#          proc;\
-#          clk2fflogic;\
-#          miter -equiv -flatten -ignore_gold_x -make_outputs -make_outcmp gold gate miter;\
-#          sat -dump_vcd equiv_${NAME}.vcd -verify-no-timeout -timeout 60 -seq 50 -prove trigger 0 -prove-skip 1 -show-inputs -show-outputs miter" ${NAME}_out.v