diff options
Diffstat (limited to 'ice40/chipdb.py')
| -rw-r--r-- | ice40/chipdb.py | 23 |
1 files changed, 22 insertions, 1 deletions
diff --git a/ice40/chipdb.py b/ice40/chipdb.py index 96231b26..42ca6ac1 100644 --- a/ice40/chipdb.py +++ b/ice40/chipdb.py @@ -492,7 +492,7 @@ def wiredelay(wire_idx, db): def init_tiletypes(device): global num_tile_types, tile_sizes, tile_bits - if device == "5k": + if device in ["5k", "u4k"]: num_tile_types = 10 else: num_tile_types = 5 @@ -954,6 +954,27 @@ def add_bel_ec(ec): add_pll_clock_output(bel, ec, entry) else: extra_cell_config[bel].append(entry) + if ectype == "MAC16": + if y == 5: + last_dsp_y = 0 # dummy, but the wire is needed + elif y == 10: + last_dsp_y = 5 + elif y == 13: + last_dsp_y = 5 + elif y == 15: + last_dsp_y = 10 + elif y == 23: + last_dsp_y = 23 + else: + assert False, "unknown DSP y " + str(y) + wire_signextin = add_wire(x, last_dsp_y, "dsp/signextout") + wire_signextout = add_wire(x, y, "dsp/signextout") + wire_accumci = add_wire(x, last_dsp_y, "dsp/accumco") + wire_accumco = add_wire(x, y, "dsp/accumco") + add_bel_input(bel, wire_signextin, "SIGNEXTIN") + add_bel_output(bel, wire_signextout, "SIGNEXTOUT") + add_bel_input(bel, wire_accumci, "ACCUMCI") + add_bel_output(bel, wire_accumco, "ACCUMCO") cell_timings = {} tmport_to_constids = { |