diff options
Diffstat (limited to 'ice40/chipdb.py')
| -rw-r--r-- | ice40/chipdb.py | 122 |
1 files changed, 82 insertions, 40 deletions
diff --git a/ice40/chipdb.py b/ice40/chipdb.py index 3b71a6b4..58dd0dd2 100644 --- a/ice40/chipdb.py +++ b/ice40/chipdb.py @@ -11,16 +11,18 @@ tiles = dict() wire_uphill = dict() wire_downhill = dict() -wire_bidir = dict() +pip_xy = dict() bel_name = list() bel_type = list() +bel_pos = list() wire_uphill_belport = dict() wire_downhill_belports = dict() wire_names = dict() wire_names_r = dict() +wire_xy = dict() def cmp_wire_names(newname, oldname): return newname < oldname @@ -46,11 +48,11 @@ with open(sys.argv[1], "r") as f: continue if line[0] == ".buffer": - mode = ("buffer", int(line[3])) + mode = ("buffer", int(line[3]), int(line[1]), int(line[2])) continue if line[0] == ".routing": - mode = ("routing", int(line[3])) + mode = ("routing", int(line[3]), int(line[1]), int(line[2])) continue if line[0] == ".io_tile": @@ -82,6 +84,9 @@ with open(sys.argv[1], "r") as f: wire_names[wname] = mode[1] if (mode[1] not in wire_names_r) or cmp_wire_names(wname, wire_names_r[mode[1]]): wire_names_r[mode[1]] = wname + if mode[1] not in wire_xy: + wire_xy[mode[1]] = list() + wire_xy[mode[1]].append((int(line[0]), int(line[1]))) continue if mode[0] == "buffer": @@ -93,17 +98,28 @@ with open(sys.argv[1], "r") as f: wire_uphill[wire_b] = set() wire_downhill[wire_a].add(wire_b) wire_uphill[wire_b].add(wire_a) + pip_xy[(wire_a, wire_b)] = (mode[2], mode[3]) continue if mode[0] == "routing": wire_a = int(line[1]) wire_b = mode[1] - if wire_a not in wire_bidir: - wire_bidir[wire_a] = set() - if wire_b not in wire_bidir: - wire_bidir[wire_b] = set() - wire_bidir[wire_a].add(wire_b) - wire_bidir[wire_b].add(wire_b) + + if wire_a not in wire_downhill: + wire_downhill[wire_a] = set() + if wire_b not in wire_uphill: + wire_uphill[wire_b] = set() + wire_downhill[wire_a].add(wire_b) + wire_uphill[wire_b].add(wire_a) + pip_xy[(wire_a, wire_b)] = (mode[2], mode[3]) + + if wire_b not in wire_downhill: + wire_downhill[wire_b] = set() + if wire_a not in wire_uphill: + wire_uphill[wire_a] = set() + wire_downhill[wire_b].add(wire_a) + wire_uphill[wire_a].add(wire_b) + pip_xy[(wire_b, wire_a)] = (mode[2], mode[3]) continue def add_bel_input(bel, wire, port): @@ -119,6 +135,7 @@ def add_bel_lc(x, y, z): bel = len(bel_name) bel_name.append("%d_%d_lc%d" % (x, y, z)) bel_type.append("ICESTORM_LC") + bel_pos.append((x, y, z)) wire_cen = wire_names[(x, y, "lutff_global/cen")] wire_clk = wire_names[(x, y, "lutff_global/clk")] @@ -157,6 +174,7 @@ def add_bel_io(x, y, z): bel = len(bel_name) bel_name.append("%d_%d_lc%d" % (x, y, z)) bel_type.append("SB_IO") + bel_pos.append((x, y, z)) wire_cen = wire_names[(x, y, "io_global/cen")] wire_iclk = wire_names[(x, y, "io_global/inclk")] @@ -185,6 +203,7 @@ def add_bel_ram(x, y): bel = len(bel_name) bel_name.append("%d_%d_ram" % (x, y)) bel_type.append("ICESTORM_RAM") + bel_pos.append((x, y, 0)) if (x, y, "ram/WE") in wire_names: # iCE40 1K-style memories @@ -222,63 +241,86 @@ for tile_xy, tile_type in sorted(tiles.items()): print('#include "chip.h"') -print("int num_bels_%s = %d;" % (dev_name, num_wires)) -print("BelInfoPOD bel_data_%s[%d] = {" % (dev_name, num_wires)) +print("BelInfoPOD bel_data_%s[%d] = {" % (dev_name, len(bel_name))) for bel in range(len(bel_name)): - print(" {\"%s\", TYPE_%s}%s" % (bel_name[bel], bel_type[bel], "," if bel+1 < len(bel_name) else "")) + print(" {\"%s\", TYPE_%s, %d, %d, %d}%s" % (bel_name[bel], bel_type[bel], + bel_pos[bel][0], bel_pos[bel][1], bel_pos[bel][2], + "," if bel+1 < len(bel_name) else "")) print("};") wireinfo = list() +pipinfo = list() +pipcache = dict() for wire in range(num_wires): - num_uphill = 0 - num_downhill = 0 - num_bidir = 0 - num_bels_downhill = 0 - if wire in wire_uphill: - num_uphill = len(wire_uphill[wire]) - print("static WireDelayPOD wire%d_uphill[] = {" % wire) - print(",\n".join([" {%d, 1.0}" % other_wire for other_wire in wire_uphill[wire]])) - print("};") + pips = list() + for src in wire_uphill[wire]: + if (src, wire) not in pipcache: + pipcache[(src, wire)] = len(pipinfo) + pipinfo.append(" {%d, %d, 1.0, %d, %d}" % (src, wire, pip_xy[(src, wire)][0], pip_xy[(src, wire)][1])) + pips.append("%d" % pipcache[(src, wire)]) + num_uphill = len(pips) + list_uphill = "wire%d_uppips" % wire + print("static int wire%d_uppips[] = {%s};" % (wire, ", ".join(pips))) + else: + num_uphill = 0 + list_uphill = "nullptr" if wire in wire_downhill: - num_downhill = len(wire_downhill[wire]) - print("static WireDelayPOD wire%d_downhill[] = {" % wire) - print(",\n".join([" {%d, 1.0}" % other_wire for other_wire in wire_downhill[wire]])) - print("};") - - if wire in wire_bidir: - num_bidir = len(wire_bidir[wire]) - print("static WireDelayPOD wire%d_bidir[] = {" % wire) - print(",\n".join([" {%d, 1.0}" % other_wire for other_wire in wire_bidir[wire]])) - print("};") + pips = list() + for dst in wire_downhill[wire]: + if (wire, dst) not in pipcache: + pipcache[(wire, dst)] = len(pipinfo) + pipinfo.append(" {%d, %d, 1.0, %d, %d}" % (wire, dst, pip_xy[(wire, dst)][0], pip_xy[(wire, dst)][1])) + pips.append("%d" % pipcache[(wire, dst)]) + num_downhill = len(pips) + list_downhill = "wire%d_downpips" % wire + print("static int wire%d_downpips[] = {%s};" % (wire, ", ".join(pips))) + else: + num_downhill = 0 + list_downhill = "nullptr" if wire in wire_downhill_belports: num_bels_downhill = len(wire_downhill_belports[wire]) print("static BelPortPOD wire%d_downbels[] = {" % wire) print(",\n".join([" {%d, PIN_%s}" % it for it in wire_downhill_belports[wire]])) print("};") + else: + num_bels_downhill = 0 info = " {" info += "\"%d_%d_%s\", " % wire_names_r[wire] - info += "%d, %d, %d, " % (num_uphill, num_downhill, num_bidir) - info += ("wire%d_uphill, " % wire) if num_uphill > 0 else "nullptr, " - info += ("wire%d_downhill, " % wire) if num_downhill > 0 else "nullptr, " - info += ("wire%d_bidir, " % wire) if num_bidir > 0 else "nullptr, " - info += "%d, " % (num_bels_downhill) + info += "%d, %d, %s, %s, %d, " % (num_uphill, num_downhill, list_uphill, list_downhill, num_bels_downhill) if wire in wire_uphill_belport: info += "{%d, PIN_%s}, " % wire_uphill_belport[wire] else: info += "{-1, PIN_NIL}, " - info += ("wire%d_downbels" % wire) if num_bels_downhill > 0 else "nullptr" - info += "}" + info += ("wire%d_downbels, " % wire) if num_bels_downhill > 0 else "nullptr, " + + avg_x, avg_y = 0, 0 + if wire in wire_xy: + for x, y in wire_xy[wire]: + avg_x += x + avg_y += y + avg_x /= len(wire_xy[wire]) + avg_y /= len(wire_xy[wire]) + + info += "%f, %f}" % (avg_x, avg_y) wireinfo.append(info) -print("int num_wires_%s = %d;" % (dev_name, num_wires)) -print("WireInfoPOD wire_data_%s[%d] = {" % (dev_name, num_wires)) +print("static WireInfoPOD wire_data_%s[%d] = {" % (dev_name, num_wires)) print(",\n".join(wireinfo)) print("};") + +print("static PipInfoPOD pip_data_%s[%d] = {" % (dev_name, len(pipinfo))) +print(",\n".join(pipinfo)) +print("};") + +print("ChipInfoPOD chip_info_%s = {" % dev_name) +print(" %d, %d, %d, %d, %d," % (dev_width, dev_height, len(bel_name), num_wires, len(pipinfo))) +print(" bel_data_%s, wire_data_%s, pip_data_%s" % (dev_name, dev_name, dev_name)) +print("};") |