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-rw-r--r--ice40/arch.cc52
-rw-r--r--ice40/arch.h6
-rw-r--r--ice40/bitstream.cc9
-rw-r--r--ice40/cells.cc4
-rw-r--r--ice40/family.cmake8
-rw-r--r--ice40/main.cc26
-rw-r--r--ice40/pack.cc27
-rw-r--r--ice40/place_legaliser.cc2
8 files changed, 101 insertions, 33 deletions
diff --git a/ice40/arch.cc b/ice40/arch.cc
index f3004155..5545ddf4 100644
--- a/ice40/arch.cc
+++ b/ice40/arch.cc
@@ -317,15 +317,15 @@ PortType Arch::getBelPinType(BelId bel, PortPin pin) const
return PortType(bel_wires[i].type);
}
} else {
- int b = 0, e = num_bel_wires-1;
+ int b = 0, e = num_bel_wires - 1;
while (b <= e) {
- int i = (b+e) / 2;
+ int i = (b + e) / 2;
if (bel_wires[i].port == pin)
return PortType(bel_wires[i].type);
if (bel_wires[i].port > pin)
- e = i-1;
+ e = i - 1;
else
- b = i+1;
+ b = i + 1;
}
}
@@ -349,17 +349,17 @@ WireId Arch::getBelPinWire(BelId bel, PortPin pin) const
}
}
} else {
- int b = 0, e = num_bel_wires-1;
+ int b = 0, e = num_bel_wires - 1;
while (b <= e) {
- int i = (b+e) / 2;
+ int i = (b + e) / 2;
if (bel_wires[i].port == pin) {
ret.index = bel_wires[i].wire_index;
break;
}
if (bel_wires[i].port > pin)
- e = i-1;
+ e = i - 1;
else
- b = i+1;
+ b = i + 1;
}
}
@@ -613,14 +613,50 @@ delay_t Arch::estimateDelay(WireId src, WireId dst) const
int xd = x2 - x1, yd = y2 - y1;
int xscale = 120, yscale = 120, offset = 0;
+ return xscale * abs(xd) + yscale * abs(yd) + offset;
+}
+
+delay_t Arch::predictDelay(const NetInfo *net_info, const PortRef &sink) const
+{
+ const auto &driver = net_info->driver;
+ auto driver_loc = getBelLocation(driver.cell->bel);
+ auto sink_loc = getBelLocation(sink.cell->bel);
+
+ if (driver.port == id_cout) {
+ if (driver_loc.y == sink_loc.y)
+ return 0;
+ return 250;
+ }
+
+ int xd = sink_loc.x - driver_loc.x, yd = sink_loc.y - driver_loc.y;
+ int xscale = 120, yscale = 120, offset = 0;
+
// if (chip_info->wire_data[src.index].type == WIRE_TYPE_SP4_VERT) {
// yd = yd < -4 ? yd + 4 : (yd < 0 ? 0 : yd);
// offset = 500;
// }
+ if (driver.port == id_o)
+ offset += 330;
+ if (sink.port == id_i0 || sink.port == id_i1 || sink.port == id_i2 || sink.port == id_i3)
+ offset += 260;
+
return xscale * abs(xd) + yscale * abs(yd) + offset;
}
+delay_t Arch::getBudgetOverride(const NetInfo *net_info, const PortRef &sink, delay_t budget) const
+{
+ const auto &driver = net_info->driver;
+ if (driver.port == id_cout) {
+ auto driver_loc = getBelLocation(driver.cell->bel);
+ auto sink_loc = getBelLocation(sink.cell->bel);
+ if (driver_loc.y == sink_loc.y)
+ return 0;
+ return 250;
+ }
+ return budget;
+}
+
// -----------------------------------------------------------------------
bool Arch::place() { return placer1(getCtx()); }
diff --git a/ice40/arch.h b/ice40/arch.h
index 7efa733c..07a8070a 100644
--- a/ice40/arch.h
+++ b/ice40/arch.h
@@ -531,9 +531,9 @@ struct Arch : BaseCtx
DelayInfo delay;
NPNR_ASSERT(wire != WireId());
if (fast_part)
- delay.delay = chip_info->wire_data[wire.index].fast_delay;
+ delay.delay = chip_info->wire_data[wire.index].fast_delay;
else
- delay.delay = chip_info->wire_data[wire.index].slow_delay;
+ delay.delay = chip_info->wire_data[wire.index].slow_delay;
return delay;
}
@@ -697,10 +697,12 @@ struct Arch : BaseCtx
// -------------------------------------------------
delay_t estimateDelay(WireId src, WireId dst) const;
+ delay_t predictDelay(const NetInfo *net_info, const PortRef &sink) const;
delay_t getDelayEpsilon() const { return 20; }
delay_t getRipupDelayPenalty() const { return 200; }
float getDelayNS(delay_t v) const { return v * 0.001; }
uint32_t getDelayChecksum(delay_t v) const { return v; }
+ delay_t getBudgetOverride(const NetInfo *net_info, const PortRef &sink, delay_t budget) const;
// -------------------------------------------------
diff --git a/ice40/bitstream.cc b/ice40/bitstream.cc
index af5febce..d0d6b205 100644
--- a/ice40/bitstream.cc
+++ b/ice40/bitstream.cc
@@ -425,6 +425,10 @@ void write_asc(const Context *ctx, std::ostream &out)
{"A_SIGNED", 1},
{"B_SIGNED", 1}};
configure_extra_cell(config, ctx, cell.second.get(), mac16_params, false, std::string("IpConfig."));
+ } else if (cell.second->type == ctx->id("ICESTORM_HFOSC")) {
+ const std::vector<std::pair<std::string, int>> hfosc_params = {{"CLKHF_DIV", 2}, {"TRIM_EN", 1}};
+ configure_extra_cell(config, ctx, cell.second.get(), hfosc_params, true, std::string("IpConfig."));
+
} else if (cell.second->type == ctx->id("ICESTORM_PLL")) {
const std::vector<std::pair<std::string, int>> pll_params = {{"DELAY_ADJMODE_FB", 1},
{"DELAY_ADJMODE_REL", 1},
@@ -566,8 +570,9 @@ void write_asc(const Context *ctx, std::ostream &out)
set_config(ti, config.at(y).at(x),
"Cascade.IPCON_LC0" + std::to_string(lc_idx) + "_inmux02_5", true);
else
- set_config(ti, config.at(y).at(x), "Cascade.MULT" + std::to_string(int(tile - TILE_DSP0)) +
- "_LC0" + std::to_string(lc_idx) + "_inmux02_5",
+ set_config(ti, config.at(y).at(x),
+ "Cascade.MULT" + std::to_string(int(tile - TILE_DSP0)) + "_LC0" +
+ std::to_string(lc_idx) + "_inmux02_5",
true);
}
}
diff --git a/ice40/cells.cc b/ice40/cells.cc
index 610bf85e..5bdc7990 100644
--- a/ice40/cells.cc
+++ b/ice40/cells.cc
@@ -113,8 +113,8 @@ std::unique_ptr<CellInfo> create_ice_cell(Context *ctx, IdString type, std::stri
add_port(ctx, new_cell.get(), "CLKLF", PORT_OUT);
add_port(ctx, new_cell.get(), "CLKLF_FABRIC", PORT_OUT);
} else if (type == ctx->id("ICESTORM_HFOSC")) {
- new_cell->params[ctx->id("CLKHF_DIV")] = "0";
- new_cell->params[ctx->id("TRIM_EN")] = "0";
+ new_cell->params[ctx->id("CLKHF_DIV")] = "0b00";
+ new_cell->params[ctx->id("TRIM_EN")] = "0b0";
add_port(ctx, new_cell.get(), "CLKHFEN", PORT_IN);
add_port(ctx, new_cell.get(), "CLKHFPU", PORT_IN);
diff --git a/ice40/family.cmake b/ice40/family.cmake
index 02d4b4d8..4f575b15 100644
--- a/ice40/family.cmake
+++ b/ice40/family.cmake
@@ -21,13 +21,13 @@ if (MSVC)
foreach (dev ${devices})
if (dev EQUAL "5k")
set(OPT_FAST "")
- set(OPT_SLOW --slow ${ICEBOX_ROOT}/timings-up5k.txt)
+ set(OPT_SLOW --slow ${ICEBOX_ROOT}/timings_up5k.txt)
elseif(dev EQUAL "384")
set(OPT_FAST "")
- set(OPT_SLOW --slow ${ICEBOX_ROOT}/timings-lp384.txt)
+ set(OPT_SLOW --slow ${ICEBOX_ROOT}/timings_lp384.txt)
else()
- set(OPT_FAST --fast ${ICEBOX_ROOT}/timings-hx${dev}.txt)
- set(OPT_SLOW --slow ${ICEBOX_ROOT}/timings-lp${dev}.txt)
+ set(OPT_FAST --fast ${ICEBOX_ROOT}/timings_hx${dev}.txt)
+ set(OPT_SLOW --slow ${ICEBOX_ROOT}/timings_lp${dev}.txt)
endif()
set(DEV_TXT_DB ${ICEBOX_ROOT}/chipdb-${dev}.txt)
set(DEV_CC_BBA_DB ${CMAKE_CURRENT_SOURCE_DIR}/ice40/chipdbs/chipdb-${dev}.bba)
diff --git a/ice40/main.cc b/ice40/main.cc
index 32815b26..6e8385e6 100644
--- a/ice40/main.cc
+++ b/ice40/main.cc
@@ -105,6 +105,8 @@ int main(int argc, char *argv[])
options.add_options()("asc", po::value<std::string>(), "asc bitstream file to write");
options.add_options()("read", po::value<std::string>(), "asc bitstream file to read");
options.add_options()("seed", po::value<int>(), "seed value for random number generator");
+ options.add_options()("slack_redist_iter", po::value<int>(),
+ "number of iterations between slack redistribution");
options.add_options()("version,V", "show version");
options.add_options()("tmfuzz", "run path delay estimate fuzzer");
options.add_options()("test", "check architecture database integrity");
@@ -144,16 +146,18 @@ int main(int argc, char *argv[])
#endif
if (vm.count("help") || argc == 1) {
help:
- std::cout << boost::filesystem::basename(argv[0]) << " -- Next Generation Place and Route (git "
- "sha1 " GIT_COMMIT_HASH_STR ")\n";
+ std::cout << boost::filesystem::basename(argv[0])
+ << " -- Next Generation Place and Route (git "
+ "sha1 " GIT_COMMIT_HASH_STR ")\n";
std::cout << "\n";
std::cout << options << "\n";
return argc != 1;
}
if (vm.count("version")) {
- std::cout << boost::filesystem::basename(argv[0]) << " -- Next Generation Place and Route (git "
- "sha1 " GIT_COMMIT_HASH_STR ")\n";
+ std::cout << boost::filesystem::basename(argv[0])
+ << " -- Next Generation Place and Route (git "
+ "sha1 " GIT_COMMIT_HASH_STR ")\n";
return 1;
}
@@ -302,6 +306,10 @@ int main(int argc, char *argv[])
ctx->rngseed(vm["seed"].as<int>());
}
+ if (vm.count("slack_redist_iter")) {
+ ctx->slack_redist_iter = vm["slack_redist_iter"].as<int>();
+ }
+
if (vm.count("svg")) {
std::cout << "<svg xmlns=\"http://www.w3.org/2000/svg\" "
"xmlns:xlink=\"http://www.w3.org/1999/xlink\">\n";
@@ -363,8 +371,15 @@ int main(int argc, char *argv[])
}
}
- if (vm.count("freq"))
+ if (vm.count("freq")) {
ctx->target_freq = vm["freq"].as<double>() * 1e6;
+ ctx->user_freq = true;
+ } else {
+#ifndef NO_GUI
+ if (!vm.count("gui"))
+#endif
+ log_warning("Target frequency not specified. Will optimise for max frequency.\n");
+ }
ctx->timing_driven = true;
if (vm.count("no-tmdriv"))
@@ -407,7 +422,6 @@ int main(int argc, char *argv[])
if (!ctx->pack() && !ctx->force)
log_error("Packing design failed.\n");
- assign_budget(ctx.get());
ctx->check();
print_utilisation(ctx.get());
if (!vm.count("pack-only")) {
diff --git a/ice40/pack.cc b/ice40/pack.cc
index 8182eb70..08f66369 100644
--- a/ice40/pack.cc
+++ b/ice40/pack.cc
@@ -607,12 +607,25 @@ static void pack_special(Context *ctx)
packed_cells.insert(ci->name);
replace_port(ci, ctx->id("CLKLFEN"), packed.get(), ctx->id("CLKLFEN"));
replace_port(ci, ctx->id("CLKLFPU"), packed.get(), ctx->id("CLKLFPU"));
- if (bool_or_default(ci->attrs, ctx->id("ROUTE_THROUGH_FABRIC"))) {
+ if (/*bool_or_default(ci->attrs, ctx->id("ROUTE_THROUGH_FABRIC"))*/ true) { // FIXME
replace_port(ci, ctx->id("CLKLF"), packed.get(), ctx->id("CLKLF_FABRIC"));
} else {
replace_port(ci, ctx->id("CLKLF"), packed.get(), ctx->id("CLKLF"));
}
new_cells.push_back(std::move(packed));
+ } else if (is_sb_hfosc(ctx, ci)) {
+ std::unique_ptr<CellInfo> packed =
+ create_ice_cell(ctx, ctx->id("ICESTORM_HFOSC"), ci->name.str(ctx) + "_OSC");
+ packed_cells.insert(ci->name);
+ packed->params[ctx->id("CLKHF_DIV")] = str_or_default(ci->params, ctx->id("CLKHF_DIV"), "0b00");
+ replace_port(ci, ctx->id("CLKHFEN"), packed.get(), ctx->id("CLKHFEN"));
+ replace_port(ci, ctx->id("CLKHFPU"), packed.get(), ctx->id("CLKHFPU"));
+ if (/*bool_or_default(ci->attrs, ctx->id("ROUTE_THROUGH_FABRIC"))*/ true) { // FIXME
+ replace_port(ci, ctx->id("CLKHF"), packed.get(), ctx->id("CLKHF_FABRIC"));
+ } else {
+ replace_port(ci, ctx->id("CLKHF"), packed.get(), ctx->id("CLKHF"));
+ }
+ new_cells.push_back(std::move(packed));
} else if (is_sb_spram(ctx, ci)) {
std::unique_ptr<CellInfo> packed =
create_ice_cell(ctx, ctx->id("ICESTORM_SPRAM"), ci->name.str(ctx) + "_RAM");
@@ -662,12 +675,12 @@ static void pack_special(Context *ctx)
auto feedback_path = packed->params[ctx->id("FEEDBACK_PATH")];
packed->params[ctx->id("FEEDBACK_PATH")] =
- feedback_path == "DELAY" ? "0" : feedback_path == "SIMPLE"
- ? "1"
- : feedback_path == "PHASE_AND_DELAY"
- ? "2"
- : feedback_path == "EXTERNAL" ? "6"
- : feedback_path;
+ feedback_path == "DELAY"
+ ? "0"
+ : feedback_path == "SIMPLE" ? "1"
+ : feedback_path == "PHASE_AND_DELAY"
+ ? "2"
+ : feedback_path == "EXTERNAL" ? "6" : feedback_path;
packed->params[ctx->id("PLLTYPE")] = std::to_string(sb_pll40_type(ctx, ci));
NetInfo *pad_packagepin_net = nullptr;
diff --git a/ice40/place_legaliser.cc b/ice40/place_legaliser.cc
index 0d14fb35..a498e5f4 100644
--- a/ice40/place_legaliser.cc
+++ b/ice40/place_legaliser.cc
@@ -164,8 +164,6 @@ class PlacementLegaliser
ctx->assignArchInfo();
-
-
return legalised_carries && replaced_cells;
}
generated by cgit v1.2.3 (git 2.25.1) at 2025-05-28 02:18:31 +0000