diff options
Diffstat (limited to 'mistral')
| -rw-r--r-- | mistral/arch.cc | 4 | ||||
| -rw-r--r-- | mistral/arch_pybindings.cc | 8 | ||||
| -rw-r--r-- | mistral/bitstream.cc | 10 | ||||
| -rw-r--r-- | mistral/pack.cc | 28 |
4 files changed, 25 insertions, 25 deletions
diff --git a/mistral/arch.cc b/mistral/arch.cc index cfa3e8b3..70e8f806 100644 --- a/mistral/arch.cc +++ b/mistral/arch.cc @@ -375,8 +375,8 @@ void Arch::assign_default_pinmap(CellInfo *cell) void Arch::assignArchInfo() { - for (auto cell : sorted(cells)) { - CellInfo *ci = cell.second; + for (auto &cell : cells) { + CellInfo *ci = cell.second.get(); if (is_comb_cell(ci->type)) assign_comb_info(ci); else if (ci->type == id_MISTRAL_FF) diff --git a/mistral/arch_pybindings.cc b/mistral/arch_pybindings.cc index 23716c93..c44a1fab 100644 --- a/mistral/arch_pybindings.cc +++ b/mistral/arch_pybindings.cc @@ -50,10 +50,10 @@ void arch_wrap_python(py::module &m) fn_wrapper_2a<Context, decltype(&Context::compute_lut_mask), &Context::compute_lut_mask, pass_through<uint64_t>, pass_through<uint32_t>, pass_through<uint8_t>>::def_wrap(ctx_cls, "compute_lut_mask"); - typedef std::unordered_map<IdString, std::unique_ptr<CellInfo>> CellMap; - typedef std::unordered_map<IdString, std::unique_ptr<NetInfo>> NetMap; - typedef std::unordered_map<IdString, IdString> AliasMap; - typedef std::unordered_map<IdString, HierarchicalCell> HierarchyMap; + typedef dict<IdString, std::unique_ptr<CellInfo>> CellMap; + typedef dict<IdString, std::unique_ptr<NetInfo>> NetMap; + typedef dict<IdString, IdString> AliasMap; + typedef dict<IdString, HierarchicalCell> HierarchyMap; auto belpin_cls = py::class_<ContextualWrapper<BelPin>>(m, "BelPin"); readonly_wrapper<BelPin, decltype(&BelPin::bel), &BelPin::bel, conv_to_str<BelId>>::def_wrap(belpin_cls, "bel"); diff --git a/mistral/bitstream.cc b/mistral/bitstream.cc index 340ba6b9..0e8b9c85 100644 --- a/mistral/bitstream.cc +++ b/mistral/bitstream.cc @@ -156,9 +156,9 @@ struct MistralBitgen void write_routing() { - for (auto net : sorted(ctx->nets)) { - NetInfo *ni = net.second; - for (auto wire : sorted_ref(ni->wires)) { + for (auto &net : ctx->nets) { + NetInfo *ni = net.second.get(); + for (auto &wire : ni->wires) { PipId pip = wire.second.pip; if (pip == PipId()) continue; @@ -200,8 +200,8 @@ struct MistralBitgen void write_cells() { - for (auto cell : sorted(ctx->cells)) { - CellInfo *ci = cell.second; + for (auto &cell : ctx->cells) { + CellInfo *ci = cell.second.get(); Loc loc = ctx->getBelLocation(ci->bel); int bi = ctx->bel_data(ci->bel).block_index; if (ctx->is_io_cell(ci->type)) diff --git a/mistral/pack.cc b/mistral/pack.cc index 90fbfd78..98ab22bf 100644 --- a/mistral/pack.cc +++ b/mistral/pack.cc @@ -133,8 +133,8 @@ struct MistralPacker // Remove unused inverters and high/low drivers std::vector<IdString> trim_cells; std::vector<IdString> trim_nets; - for (auto cell : sorted(ctx->cells)) { - CellInfo *ci = cell.second; + for (auto &cell : ctx->cells) { + CellInfo *ci = cell.second.get(); if (ci->type != id_MISTRAL_NOT && ci->type != id_GND && ci->type != id_VCC) continue; IdString port = (ci->type == id_MISTRAL_NOT) ? id_Q : id_Y; @@ -161,15 +161,15 @@ struct MistralPacker void pack_constants() { // Iterate through cells - for (auto cell : sorted(ctx->cells)) { - CellInfo *ci = cell.second; + for (auto &cell : ctx->cells) { + CellInfo *ci = cell.second.get(); // Skip certain cells at this point if (ci->type != id_MISTRAL_NOT && ci->type != id_GND && ci->type != id_VCC) - process_inv_constants(cell.second); + process_inv_constants(ci); } // Special case - SDATA can only be trimmed if SLOAD is low - for (auto cell : sorted(ctx->cells)) { - CellInfo *ci = cell.second; + for (auto &cell : ctx->cells) { + CellInfo *ci = cell.second.get(); if (ci->type != id_MISTRAL_FF) continue; if (ci->get_pin_state(id_SLOAD) != PIN_0) @@ -185,7 +185,7 @@ struct MistralPacker // Find the actual IO buffer corresponding to a port; and copy attributes across to it // Note that this relies on Yosys to do IO buffer inference, to avoid tristate issues once we get to synthesised // JSON. In all cases the nextpnr-inserted IO buffers are removed as redundant. - for (auto &port : sorted_ref(ctx->ports)) { + for (auto &port : ctx->ports) { if (!ctx->cells.count(port.first)) log_error("Port '%s' doesn't seem to have a corresponding top level IO\n", ctx->nameOf(port.first)); CellInfo *ci = ctx->cells.at(port.first).get(); @@ -256,8 +256,8 @@ struct MistralPacker // Step 0: deal with top level inserted IO buffers prepare_io(); // Stage 1: apply constraints - for (auto cell : sorted(ctx->cells)) { - CellInfo *ci = cell.second; + for (auto &cell : ctx->cells) { + CellInfo *ci = cell.second.get(); // Iterate through all IO buffer primitives if (!ctx->is_io_cell(ci->type)) continue; @@ -286,8 +286,8 @@ struct MistralPacker void constrain_carries() { - for (auto cell : sorted(ctx->cells)) { - CellInfo *ci = cell.second; + for (auto &cell : ctx->cells) { + CellInfo *ci = cell.second.get(); if (ci->type != id_MISTRAL_ALUT_ARITH) continue; const NetInfo *cin = get_net_or_empty(ci, id_CI); @@ -332,8 +332,8 @@ struct MistralPacker } } // Check we reached all the cells in the above pass - for (auto cell : sorted(ctx->cells)) { - CellInfo *ci = cell.second; + for (auto &cell : ctx->cells) { + CellInfo *ci = cell.second.get(); if (ci->type != id_MISTRAL_ALUT_ARITH) continue; if (ci->cluster == ClusterId()) |