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-rw-r--r--nexus/arch.cc2
-rw-r--r--nexus/pack.cc4
2 files changed, 3 insertions, 3 deletions
diff --git a/nexus/arch.cc b/nexus/arch.cc
index 39e51a5b..9679c3fb 100644
--- a/nexus/arch.cc
+++ b/nexus/arch.cc
@@ -486,7 +486,7 @@ bool Arch::getCellDelay(const CellInfo *cell, IdString fromPort, IdString toPort
if (fromPort == id_CLK)
return false; // don't include delays that are actually clock-to-out here
return lookup_cell_delay(cell->tmg_index, lookup_port(fromPort), lookup_port(toPort), delay);
- } else if(cell->type == id_DCS) {
+ } else if (cell->type == id_DCS) {
if (fromPort == id_SELFORCE || fromPort == id_SEL) {
return false;
}
diff --git a/nexus/pack.cc b/nexus/pack.cc
index bb62ec85..26da3dc5 100644
--- a/nexus/pack.cc
+++ b/nexus/pack.cc
@@ -2007,14 +2007,14 @@ struct NexusPacker
copy_constraint(ci, id_CLK0, id_DCSOUT);
} else if (!have_clk0 && have_clk1) {
copy_constraint(ci, id_CLK1, id_DCSOUT);
- } else if ( have_clk0 && have_clk1) {
+ } else if (have_clk0 && have_clk1) {
set_period(ci, id_DCSOUT, std::min(period_clk0, period_clk1));
}
} else if (ci->type == id_OSC_CORE) {
int div = int_or_default(ci->params, id_HF_CLK_DIV, 128);
const float tol = 1.07f; // OSCA has +/-7% frequency tolerance, assume the worst case.
set_period(ci, id_HFCLKOUT, delay_t((1.0e6 / 450) * (div + 1) / tol));
- set_period(ci, id_LFCLKOUT, delay_t((1.0e9 / 32) / tol));
+ set_period(ci, id_LFCLKOUT, delay_t((1.0e9 / 32) / tol));
} else if (ci->type == id_PLL_CORE) {
static const std::array<IdString, 6> div{id_DIVA, id_DIVB, id_DIVC, id_DIVD, id_DIVE, id_DIVF};
static const std::array<IdString, 6> output{id_CLKOP, id_CLKOS, id_CLKOS2,