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* mistral: Include mistral generated files in include dirsgatecat2021-08-151-1/+1
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* [interchange] Update chipdb and python-fpga-interchange versionsMaciej Dudek2021-07-141-1/+1
| | | | Signed-off-by: Maciej Dudek <mdudek@antmicro.com>
* interchange: bump python-interchange versionAlessandro Comodi2021-07-081-1/+1
| | | | Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
* ci: remove RapidWright patchingAlessandro Comodi2021-06-241-3/+0
| | | | Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
* interchange: Bump versionsgatecat2021-06-151-2/+2
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* interchange: ci: add RW patch for missing cell bel mapsAlessandro Comodi2021-06-111-0/+3
| | | | Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
* interchange: ci: update python-interchange tagAlessandro Comodi2021-06-111-1/+1
| | | | Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
* ci: Bump mistral versiongatecat2021-06-052-6/+2
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Remove redundant code after hashlib movegatecat2021-06-021-1/+1
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* interchange: Add LIFCL-40 EVN testsgatecat2021-06-012-3/+3
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* interchange: Bump versionsgatecat2021-05-271-1/+1
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* interchange: Bump versionsgatecat2021-05-211-1/+1
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* gh-actions: interchange: use commit sha as cache keyAlessandro Comodi2021-05-201-4/+10
| | | | Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
* ci: Use GH only for Mistral and fpga-interchangegatecat2021-05-152-0/+57
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* interchange: Bump versiongatecat2021-05-071-1/+1
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* interchange: Bump versionsgatecat2021-04-301-2/+2
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* interchange: Bump versionsgatecat2021-04-201-1/+1
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Merge pull request #678 from acomodi/initial-fasm-generationgatecat2021-04-141-1/+1
|\ | | | | interchange: add FASM generation target and clean-up tests
| * gh-actions: increase python-fpga-interchange tag versionAlessandro Comodi2021-04-141-1/+1
| | | | | | | | Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
* | ci: Re-enable abseil for interchange CIgatecat2021-04-141-1/+1
|/ | | | Signed-off-by: gatecat <gatecat@ds0.me>
* interchange: Pin prjoxide commitgatecat2021-04-092-0/+3
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Don't fail-fast for GH actions to allow for easier CI debugging.Keith Rothman2021-04-061-0/+3
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* [interchange] Update interchange CI for new chipdb change.Keith Rothman2021-04-012-3/+2
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* interchange: Fix nexus cmake review commentsgatecat2021-03-311-7/+7
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* ci: Build prjoxide only for LIFCLgatecat2021-03-302-7/+8
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* interchange: Add Nexus LUT testgatecat2021-03-301-1/+1
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* interchange: Add Nexus to CIgatecat2021-03-302-1/+10
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* gh-actions: better yosys caching based on versionAlessandro Comodi2021-03-262-6/+35
| | | | Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
* interchange: add archcheck tests to all-device-test targetAlessandro Comodi2021-03-261-2/+0
| | | | | | | This increases parallelism and should make the FPGA interchange CI faster Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
* gh-actions: use ccache and build tools before running testsAlessandro Comodi2021-03-252-40/+105
| | | | Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
* gh-actions: interchange: multiple jobs, one for each deviceAlessandro Comodi2021-03-242-7/+12
| | | | Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
* gh-actions: remove multi-process arch generationAlessandro Comodi2021-03-231-1/+1
| | | | Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
* [FPGA interchange] Add support for global buffers from chipdb.Keith Rothman2021-03-231-1/+1
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Use new parameter definition data in FPGA interchange processing.Keith Rothman2021-03-231-1/+1
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Increment required python-fpga-interchange version.Keith Rothman2021-03-221-1/+1
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* fpga_interchange: address review commentsAlessandro Comodi2021-03-161-2/+4
| | | | Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
* github-actions: use capnp v0.8.0Alessandro Comodi2021-03-161-3/+3
| | | | | | This also updates the note in the README for the FPGA interchange Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
* github-actions: pin python-fpga-interchange to tagAlessandro Comodi2021-03-161-1/+2
| | | | Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
* github-actions: add basic CI to test FPGA interchangeAlessandro Comodi2021-03-162-0/+74
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-10-30 11:41:03 +0000