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* Updates from clangformatClifford Wolf2018-06-172-9/+13
* Improve router log messagesClifford Wolf2018-06-171-3/+29
* Merge branch 'master' of gitlab.com:SymbioticEDA/nextpnr into chipdbngClifford Wolf2018-06-172-6/+2
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| * Speed up placerDavid Shah2018-06-172-6/+2
* | Refactore ice40 chipdb to use a super-large C-string as output formatClifford Wolf2018-06-173-27/+85
* | Minor chipdb.py improvementClifford Wolf2018-06-171-2/+17
* | Merge branch 'master' of gitlab.com:SymbioticEDA/nextpnr into chipdbngClifford Wolf2018-06-177-58/+111
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| * Minor performance tweaks and fixesDavid Shah2018-06-173-24/+30
| * ice40: Fixing negative clock bitstream generationDavid Shah2018-06-171-1/+8
| * place_sa: Adding seed optionDavid Shah2018-06-174-13/+23
| * place_sa: Add a rip-up feature when initial placement failsDavid Shah2018-06-173-29/+59
* | Updates from clangformatClifford Wolf2018-06-172-22/+25
* | Move top-level ChipInfoPOD into ice40 chipdb blobClifford Wolf2018-06-174-126/+139
* | Move PackageInfoPOD to ice40 chipdb blobClifford Wolf2018-06-173-10/+12
* | Move TileType array to ice40 chipdb blobClifford Wolf2018-06-172-7/+14
* | Move BitstreamInfoPOD to ice40 chipdb blobClifford Wolf2018-06-173-17/+23
* | Move IerenInfoPOD to ice40 chipdb blobClifford Wolf2018-06-171-12/+11
* | Move TileInfoPOD to chipdb blobClifford Wolf2018-06-172-8/+16
* | Move SwitchInfoPOD to chipdb blobClifford Wolf2018-06-172-15/+25
* | Move PipInfoPOD into ChipDB binary blobClifford Wolf2018-06-171-6/+28
* | Merge branch 'master' of gitlab.com:SymbioticEDA/nextpnr into chipdbngClifford Wolf2018-06-1722-84/+387
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| * place_sa: Make placement independant of unordered_map orderingDavid Shah2018-06-171-4/+8
| * General reformattingDavid Shah2018-06-174-4/+3
| * frontend/json: Look up netnames properly instead of using numberDavid Shah2018-06-171-7/+43
| * ice40: Add symbol output to bitstream generationDavid Shah2018-06-171-6/+8
| * Updating copyrightsDavid Shah2018-06-1717-7/+21
| * Improving the placer outputDavid Shah2018-06-176-15/+42
| * place_sa: Ignore Bels locked by manual placement for SA swapsDavid Shah2018-06-171-2/+8
| * Add 'get or default' functionsDavid Shah2018-06-172-3/+67
| * place_sa: Run a validity check at the end of placementDavid Shah2018-06-171-0/+9
| * ice40: Fixing buildDavid Shah2018-06-172-2/+2
| * Merge branch 'master' of gitlab.com:SymbioticEDA/nextpnrDavid Shah2018-06-162-1/+1
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| | * Renamed place.h to place_sa.h in place_sa.ccZipCPU2018-06-161-1/+1
| | * Changed place.h place_sa.hZipCPU2018-06-161-0/+0
| * | place: Fix placer validity checksDavid Shah2018-06-163-6/+33
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| * Renamed placer to Simulated-Annealing placerZipCPU2018-06-161-0/+0
| * ice40: Proper global promotionDavid Shah2018-06-164-24/+83
| * ice40: Promote reset signalDavid Shah2018-06-165-36/+89
| * Tweaking placer and routerDavid Shah2018-06-162-4/+7
* | Move WireInfoPOD into ChipDB binary blobClifford Wolf2018-06-173-39/+61
* | Minor refactoring of BinaryBlobAssembler, fix alignmentsClifford Wolf2018-06-174-84/+145
* | Progress with chipdb refactoringClifford Wolf2018-06-164-23/+39
* | Progress with chipdb refactoringClifford Wolf2018-06-163-42/+37
* | Progress with chipdb refactoringClifford Wolf2018-06-163-33/+175
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* Update placer for new Chip APIClifford Wolf2018-06-161-6/+6
* Update clangformatClifford Wolf2018-06-161-1/+1
* Merge remote-tracking branch 'origin/master' into chipdbngClifford Wolf2018-06-1612-76/+440
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| * router: Fixing loop issueDavid Shah2018-06-161-0/+1
| * Merge branch 'simann'David Shah2018-06-1611-76/+439
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| | * ice40: Fix RAM config in packerDavid Shah2018-06-161-1/+2
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