aboutsummaryrefslogtreecommitdiffstats
Commit message (Expand)AuthorAgeFilesLines
* Merge pull request #575 from YosysHQ/gatecat/belpin-2gatecat2021-02-1512-174/+272
|\
| * router2: Support for multiple bel pins per cell pingatecat2021-02-101-85/+95
| * router1: Support for multiple bel pins per cell pingatecat2021-02-101-62/+78
| * Start making use of getBelPinsForCellPin APIgatecat2021-02-106-38/+84
| * Add getBelPinsForCellPin to Arch APIgatecat2021-02-107-0/+26
* | Merge pull request #582 from litghost/add_xdc_parsergatecat2021-02-128-4/+238
|\ \
| * | Add FPGA interchange tests to CI.Keith Rothman2021-02-121-1/+2
| * | Update tests to include XDC unit test.Keith Rothman2021-02-121-0/+0
| * | Run "make clangformat".Keith Rothman2021-02-124-66/+53
| * | Remove capnp and libz for XDC parser PR.Keith Rothman2021-02-121-4/+0
| * | Refactor XDC parser into a little class for testing purposes.Keith Rothman2021-02-123-14/+52
| * | Add unknown handles to convert [0] to "[0]".Keith Rothman2021-02-121-0/+11
| * | Add FPGA interchange XDC parser.Keith Rothman2021-02-125-3/+204
|/ /
* | Merge pull request #579 from litghost/add_control_for_split_iogatecat2021-02-124-18/+28
|\ \
| * | Update docs.Keith Rothman2021-02-121-0/+1
| * | Add control to whether GenericFrontend splits IO ports.Keith Rothman2021-02-113-18/+27
* | | Make BaseArch getDecalGraphics return an empty rangegatecat2021-02-122-2/+2
* | | Merge pull request #580 from litghost/add_design_loaded_state_variablegatecat2021-02-123-1/+8
|\ \ \
| * | | Add design_loaded state variable.Keith Rothman2021-02-113-1/+8
| |/ /
* | | Merge pull request #581 from litghost/add_isbelhiddengatecat2021-02-1211-16/+30
|\ \ \ | |/ / |/| |
| * | Add getBelHidden and add some missing "override" statements.Keith Rothman2021-02-1111-16/+30
|/ /
* | Merge pull request #574 from YosysHQ/gatecat/belpin-1gatecat2021-02-104-37/+0
|\|
| * Remove the unused CellInfo::pins fieldgatecat2021-02-104-37/+0
|/
* Merge pull request #573 from YosysHQ/gatecat/basearchrangesgatecat2021-02-095-49/+25
|\
| * Add BaseArchRanges for default ArchRanges typesgatecat2021-02-095-49/+25
* | Add nextpnr-gowin binary to gitignoregatecat2021-02-091-0/+1
|/
* Merge pull request #568 from YosysHQ/dave/arch-overridegatecat2021-02-0820-1145/+1334
|\
| * Make BaseCtx destructor virtualgatecat2021-02-081-1/+1
| * Update docs with API changesD. Shah2021-02-081-21/+160
| * interchange: Base on ArchAPID. Shah2021-02-082-106/+135
| * Use 'T' postfix to disambiguate LHS and RHS of usingD. Shah2021-02-086-147/+153
| * Add archArgs and archArgsToId to Arch APID. Shah2021-02-057-11/+27
| * gowin: Switch to BaseArchD. Shah2021-02-052-150/+107
| * generic: Base upon ArchAPID. Shah2021-02-051-102/+132
| * nexus: Switch to BaseArchD. Shah2021-02-055-301/+103
| * ice40: Switch to BaseArchD. Shah2021-02-055-182/+115
| * Add pure-virtual ArchAPI interfaceD. Shah2021-02-051-104/+198
| * Rename ArchBase to BaseArch for consistency with BaseCtxD. Shah2021-02-053-7/+7
| * Add default implementation of bel bucket functionsD. Shah2021-02-055-88/+94
| * Add default implementation of some range-returning functionsD. Shah2021-02-052-17/+27
| * Add a few more functions to ArchBaseD. Shah2021-02-052-11/+18
| * ecp5: Use common wire/pip bindingD. Shah2021-02-052-83/+7
| * Fix now-illegal use of reinterpret_castD. Shah2021-02-051-3/+5
| * nextpnr: Example of shared wire/bel/pip binding codeD. Shah2021-02-051-13/+106
| * nextpnr: Use templates to specify range typesD. Shah2021-02-052-18/+67
| * nextpnr: Add base virtual functions for non-range Arch APID. Shah2021-02-052-84/+176
* | Update prjoxide URLD. Shah2021-02-082-4/+4
* | Merge pull request #572 from YosysHQ/dave/more-ssizeDavid Shah2021-02-084-23/+23
|\ \ | |/ |/|
| * Use RelSlice::ssize instead of cast-to-int throughoutD. Shah2021-02-084-23/+23
|/
* Merge pull request #567 from litghost/initial_fpga_interchangeDavid Shah2021-02-0515-2/+2582
|\
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-15 07:24:22 +0000