Commit message (Collapse) | Author | Age | Files | Lines | |
---|---|---|---|---|---|
* | timing_opt: Implement the BFS-based path optimisation | David Shah | 2018-12-06 | 2 | -35/+154 |
| | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
* | timing_opt: Implement critical path finder | David Shah | 2018-12-06 | 1 | -0/+114 |
| | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
* | timing_opt: Neigbour bel validity checking | David Shah | 2018-12-06 | 1 | -5/+48 |
| | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
* | timing_opt: Functions to calculate arc delay limits | David Shah | 2018-12-06 | 3 | -11/+74 |
| | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
* | timing_opt: Implement neighbour Bel finder | David Shah | 2018-12-06 | 3 | -0/+83 |
| | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
* | timing: Add criticality calculation to timing analysis | David Shah | 2018-12-06 | 3 | -2/+220 |
| | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
* | clangformat | David Shah | 2018-12-06 | 2 | -2/+3 |
| | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
* | Merge pull request #164 from YosysHQ/carry_opt | David Shah | 2018-12-06 | 1 | -31/+78 |
|\ | | | | | ice40: Carry chain optimisations | ||||
| * | ice40: Put debug logging behind ctx->debug | David Shah | 2018-12-06 | 1 | -3/+5 |
| | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
| * | ice40: Fix carry chain splitting | David Shah | 2018-12-05 | 1 | -1/+1 |
| | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
| * | ice40: Don't split carry chain in simple feed-out cases | David Shah | 2018-12-04 | 1 | -7/+50 |
| | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
| * | ice40: Include I3 connectivity in chain | David Shah | 2018-12-04 | 1 | -23/+25 |
| | | | | | | | | | | | | Thanks @smunaut Signed-off-by: David Shah <dave@ds0.me> | ||||
* | | Fix crash exiting nextpnr gui | Miodrag Milanovic | 2018-12-06 | 1 | -0/+1 |
| | | |||||
* | | Renamed LogLevel members, to prevent issue with system defines on Windows | Miodrag Milanovic | 2018-12-05 | 3 | -17/+17 |
| | | |||||
* | | Merge pull request #165 from smunaut/build_pipe | Miodrag Milanović | 2018-12-05 | 1 | -2/+2 |
|\ \ | | | | | | | build: Make use of the pipe option to avoid temporary files | ||||
| * | | build: Make use of the pipe option to avoid temporary files | Sylvain Munaut | 2018-12-04 | 1 | -2/+2 |
| |/ | | | | | | | | | | | | | | | This is really useful when building the ice40 with the gigantic .cc files that generate multi gigabyte .s temporary files ... this way the assembler just processed it in streaming way. Signed-off-by: Sylvain Munaut <tnt@246tNt.com> | ||||
* | | Merge pull request #166 from ajeakins/master | Miodrag Milanović | 2018-12-05 | 1 | -0/+1 |
|\ \ | |/ |/| | Fix crash starting the GUI on macOS where we must request a core profile | ||||
| * | Fix crash starting the GUI on macOS where we must request a core profile. | Adrian Jeakins | 2018-12-04 | 1 | -0/+1 |
|/ | | | | See http://doc.qt.io/qt-5/qabstractopenglfunctions.html | ||||
* | Merge pull request #162 from whitequark/reset-fanout | David Shah | 2018-12-04 | 1 | -1/+3 |
|\ | | | | | ice40: add reset global promotion threshold | ||||
| * | ice40: add reset global promotion threshold. | whitequark | 2018-12-04 | 1 | -1/+3 |
|/ | |||||
* | Merge pull request #160 from dmsc/sb_ledda_ip | David Shah | 2018-12-02 | 5 | -1/+26 |
|\ | | | | | ice40: Add support for placing SB_LEDDA_IP block. | ||||
| * | ice40: Add support for placing SB_LEDDA_IP block. | Daniel Serpell | 2018-12-01 | 5 | -1/+26 |
|/ | | | | Signed-off-by: Daniel Serpell <daniel.serpell@gmail.com> | ||||
* | Merge pull request #159 from YosysHQ/ecp5_pllplace | David Shah | 2018-12-01 | 2 | -2/+59 |
|\ | | | | | ecp5: Pre-place PLLs and use dedicated routes into globals | ||||
| * | ecp5: Pre-place PLLs and use dedicated routes into globals | David Shah | 2018-11-30 | 2 | -2/+59 |
| | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
* | | Merge pull request #158 from YosysHQ/improve_error | David Shah | 2018-11-29 | 5 | -10/+14 |
|\ \ | |/ |/| | Error reporting improvements | ||||
| * | ice40: Add a warning for unconstrained IO | David Shah | 2018-11-29 | 1 | -6/+5 |
| | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
| * | rulecheck: Improve message printed at start | David Shah | 2018-11-29 | 1 | -1/+1 |
| | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
| * | Improve reporting of unknown cell types | David Shah | 2018-11-29 | 2 | -2/+3 |
| | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
| * | json: Improve reporting of multiple drivers | David Shah | 2018-11-29 | 1 | -1/+5 |
|/ | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
* | Merge pull request #157 from whitequark/fanout-thresh | David Shah | 2018-11-29 | 1 | -1/+1 |
|\ | | | | | ice40: raise CE global promotion threshold | ||||
| * | ice40: raise CE global promotion threshold. | whitequark | 2018-11-29 | 1 | -1/+1 |
| | | |||||
* | | Merge pull request #156 from whitequark/fanout | David Shah | 2018-11-29 | 1 | -7/+11 |
|\ \ | |/ |/| | ice40: print fanout of nets promoted to globals | ||||
| * | ice40: print fanout of nets promoted to globals. | whitequark | 2018-11-28 | 1 | -7/+11 |
|/ | |||||
* | Merge pull request #155 from smunaut/issue_151 | David Shah | 2018-11-28 | 1 | -48/+48 |
|\ | | | | | ice40: Update the way LVDS inputs are handled during bitstream generation | ||||
| * | ice40: Update the way LVDS inputs are handled during bitstream generation | Sylvain Munaut | 2018-11-28 | 1 | -48/+48 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * Instead of "patching" input_en, we completely separate config for normal and LVDS pair. - For normal pair, nothing changes - For LVDS pairs, the IE/REN bits are always set as if the input buffer are disabled. Then if input_en was set to 1 (i.e. the input is actually for something), then we set the IoCtrl.LVDS bit. - Also for LVDS, if input is used, pullups are forcibly disabled. * When scanning for unused IOs, never process those part of a LVDS pair. They will have been configured by the complement Signed-off-by: Sylvain Munaut <tnt@246tNt.com> | ||||
* | | Merge pull request #154 from smunaut/issue_141 | David Shah | 2018-11-28 | 1 | -72/+212 |
|\ \ | |/ |/| | ice40: Complete rework of the way PLLs are placed and validity checks | ||||
| * | ice40: Try to be helpful and suggest using PAD PLL instead of CORE | Sylvain Munaut | 2018-11-28 | 1 | -2/+14 |
| | | | | | | | | Signed-off-by: Sylvain Munaut <tnt@246tNt.com> | ||||
| * | ice40: Revamp the whole PLL placement/validity check logic | Sylvain Munaut | 2018-11-28 | 1 | -72/+200 |
|/ | | | | | | | | | | | | | | | | | We do a pre-pass on all the PLLs to place them before packing. To place them: - First pass with all the PADs PLLs since those can only fit at one specific BEL depending on the input connection - Second pass with all the dual outputs CORE PLLs. Those can go anywhere where there is no conflicts with their A & B outputs and used IO pins - Third pass with the single output CORE PLLs. Those have the least constrains. During theses passes, we also check the validity of all their connections. Signed-off-by: Sylvain Munaut <tnt@246tNt.com> | ||||
* | Merge pull request #153 from YosysHQ/global-options | David Shah | 2018-11-28 | 2 | -3/+14 |
|\ | | | | | ice40: Finer-grained control of global promotion | ||||
| * | ice40: Finer-grained control of global promotion | David Shah | 2018-11-27 | 2 | -3/+14 |
|/ | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
* | Merge pull request #152 from YosysHQ/compile_fix | David Shah | 2018-11-27 | 1 | -0/+10 |
|\ | | | | | Fix compile on GCC 5.5 or older | ||||
| * | Fix compile on GCC 5.5 or older | Miodrag Milanovic | 2018-11-27 | 1 | -0/+10 |
|/ | |||||
* | Merge pull request #150 from YosysHQ/err_warn_count | David Shah | 2018-11-26 | 4 | -2/+19 |
|\ | | | | | Print warning and error count at end of execution | ||||
| * | Print warning and error count at end of execution | David Shah | 2018-11-26 | 4 | -2/+19 |
|/ | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
* | timing: Improve clock constraint log output | David Shah | 2018-11-26 | 1 | -2/+6 |
| | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
* | Merge pull request #149 from smunaut/issue_148 | David Shah | 2018-11-26 | 4 | -10/+43 |
|\ | | | | | Fixes for global promotion | ||||
| * | ice40: During global promotion, only promote if this will actually fit ! | Sylvain Munaut | 2018-11-26 | 1 | -6/+32 |
| | | | | | | | | | | | | | | | | We need to take into account the global networks that are already used and possibly locked to know what we can promote since all networks can't drive resets / clock-enables Signed-off-by: Sylvain Munaut <tnt@246tNt.com> | ||||
| * | ice40: Add helper to know which global network is driven by a SB_GB Bel | Sylvain Munaut | 2018-11-26 | 2 | -2/+8 |
| | | | | | | | | Signed-off-by: Sylvain Munaut <tnt@246tNt.com> | ||||
| * | placer1: During initial placement, don't rip-up strongly binded cells | Sylvain Munaut | 2018-11-26 | 1 | -2/+3 |
| | | | | | | | | Signed-off-by: Sylvain Munaut <tnt@246tNt.com> | ||||
* | | ecp5: Fix UR PLL tile coordinates | David Shah | 2018-11-26 | 1 | -2/+2 |
|/ | | | | Signed-off-by: David Shah <dave@ds0.me> |