Commit message (Collapse) | Author | Age | Files | Lines | ||
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* | Merge pull request #839 from yrabbit/wide-luts | gatecat | 2021-10-07 | 7 | -9/+434 | |
|\ | | | | | gowin: add support for wide LUTs. | |||||
| * | gowin: add support for wide LUTs. | YRabbit | 2021-10-07 | 7 | -9/+434 | |
|/ | | | | | | | | | * A hardwired MUX within each logical cell is used. * The delay is equal 0. * No user placement constraints. * The output route contains dummy PIPs. They are ignored by gowin_pack, but it may be worth removing them. Signed-off-by: YRabbit <rabbit@yrabbit.cyou> | |||||
* | Merge pull request #837 from YosysHQ/gatecat/mistral-mlab-2 | gatecat | 2021-10-05 | 8 | -21/+235 | |
|\ | | | | | mistral: Adding support for MLABs as memory | |||||
| * | mistral: Adding support for MLABs as memory | gatecat | 2021-10-05 | 8 | -21/+235 | |
| | | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | |||||
* | | Merge pull request #836 from YosysHQ/gatecat/mistral-mlab | gatecat | 2021-10-03 | 2 | -19/+38 | |
|\| | | | | | mistral: Add bel pins for MLAB write port | |||||
| * | mistral: Add bel pins for MLAB write port | gatecat | 2021-10-03 | 2 | -19/+38 | |
|/ | | | | Signed-off-by: gatecat <gatecat@ds0.me> | |||||
* | Merge pull request #834 from YosysHQ/gatecat/cygwin | gatecat | 2021-10-01 | 1 | -1/+1 | |
|\ | | | | | Fix Cygwin build | |||||
| * | Fix Cygwin build | gatecat | 2021-10-01 | 1 | -1/+1 | |
| | | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | |||||
* | | Merge pull request #833 from antmicro/interchange-fix-uninitialized-memory-bug | gatecat | 2021-10-01 | 1 | -1/+1 | |
|\ \ | |/ |/| | interchange: fix uninitialized memory bug in cluster placement | |||||
| * | interchange: fix uninitialized memory bug in cluster placement | Alessandro Comodi | 2021-10-01 | 1 | -1/+1 | |
|/ | | | | Signed-off-by: Alessandro Comodi <acomodi@antmicro.com> | |||||
* | Merge pull request #828 from YosysHQ/gatecat/interchange-warn-fix | gatecat | 2021-09-30 | 3 | -7/+10 | |
|\ | | | | | interchange: Enable Werror on CI and fix some compile warnings | |||||
| * | interchange: Fix compile warnings | gatecat | 2021-09-28 | 2 | -6/+9 | |
| | | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | |||||
| * | ci: Enable -Werror for interchange arch | gatecat | 2021-09-28 | 1 | -1/+1 | |
| | | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | |||||
* | | Merge pull request #810 from antmicro/write-timing-report | gatecat | 2021-09-29 | 7 | -158/+539 | |
|\ \ | | | | | | | Timing report in JSON format | |||||
| * | | Code formatting | Maciej Kurc | 2021-09-29 | 4 | -119/+87 | |
| | | | | | | | | | | | | Signed-off-by: Maciej Kurc <mkurc@antmicro.com> | |||||
| * | | Brought back printout of critical path source file references, added ↵ | Maciej Kurc | 2021-09-29 | 3 | -28/+74 | |
| | | | | | | | | | | | | | | | | | | clk-to-q, source and setup segment types Signed-off-by: Maciej Kurc <mkurc@antmicro.com> | |||||
| * | | Shifted moving of data containers after printing | Maciej Kurc | 2021-09-28 | 1 | -11/+11 | |
| | | | | | | | | | | | | Signed-off-by: Maciej Kurc <mkurc@antmicro.com> | |||||
| * | | Added a commandline option controlled writeout of per-net timing details | Maciej Kurc | 2021-09-28 | 4 | -9/+22 | |
| | | | | | | | | | | | | Signed-off-by: Maciej Kurc <mkurc@antmicro.com> | |||||
| * | | Added description of the JSON report structure. | Maciej Kurc | 2021-09-28 | 1 | -1/+73 | |
| | | | | | | | | | | | | Signed-off-by: Maciej Kurc <mkurc@antmicro.com> | |||||
| * | | Moved timing result report storage to the context, added its writeout to the ↵ | Maciej Kurc | 2021-09-28 | 6 | -282/+279 | |
| | | | | | | | | | | | | | | | | | | current utilization and fmax report Signed-off-by: Maciej Kurc <mkurc@antmicro.com> | |||||
| * | | Added reporting critical paths in JSON format | Maciej Kurc | 2021-09-28 | 1 | -25/+49 | |
| | | | | | | | | | | | | Signed-off-by: Maciej Kurc <mkurc@antmicro.com> | |||||
| * | | Decoupled critical path report generation from its printing | Maciej Kurc | 2021-09-28 | 1 | -134/+264 | |
| | | | | | | | | | | | | Signed-off-by: Maciej Kurc <mkurc@antmicro.com> | |||||
| * | | Switched to JSON format for timing analysis report | Maciej Kurc | 2021-09-28 | 1 | -33/+81 | |
| | | | | | | | | | | | | Signed-off-by: Maciej Kurc <mkurc@antmicro.com> | |||||
| * | | Added writing a CSV report with timing analysis of each net branch | Maciej Kurc | 2021-09-28 | 4 | -6/+89 | |
| |/ | | | | | | | Signed-off-by: Maciej Kurc <mkurc@antmicro.com> | |||||
* | | Merge pull request #830 from yrabbit/mistype | gatecat | 2021-09-29 | 1 | -1/+1 | |
|\ \ | |/ |/| | Fix mistype. | |||||
| * | Fix mistype. | YRabbit | 2021-09-29 | 1 | -1/+1 | |
|/ | | | | Signed-off-by: YRabbit <rabbit@yrabbit.cyou> | |||||
* | Merge pull request #827 from YosysHQ/gatecat/idstring-in | gatecat | 2021-09-27 | 1 | -0/+10 | |
|\ | | | | | idstring: Add 'in' function from Yosys | |||||
| * | idstring: Add 'in' function | gatecat | 2021-09-27 | 1 | -0/+10 | |
|/ | | | | Signed-off-by: gatecat <gatecat@ds0.me> | |||||
* | Merge pull request #812 from antmicro/MacroCells | gatecat | 2021-09-27 | 7 | -22/+572 | |
|\ | | | | | Convert macros to clusters for better placement | |||||
| * | Fix small isses and code formatting | Maciej Dudek | 2021-09-27 | 5 | -148/+150 | |
| | | | | | | | | Signed-off-by: Maciej Dudek <mdudek@antmicro.com> | |||||
| * | Break up macro_cluster_placement into smaller functions | Maciej Dudek | 2021-09-24 | 1 | -20/+33 | |
| | | | | | | | | Signed-off-by: Maciej Dudek <mdudek@antmicro.com> | |||||
| * | Update python-fpga-interchange to v0.0.20 | Maciej Dudek | 2021-09-23 | 1 | -1/+1 | |
| | | | | | | | | Signed-off-by: Maciej Dudek <mdudek@antmicro.com> | |||||
| * | Fix AC-3 algorithm | Maciej Dudek | 2021-09-23 | 1 | -9/+17 | |
| | | | | | | | | Signed-off-by: Maciej Dudek <mdudek@antmicro.com> | |||||
| * | Improve macro cluster placement | Maciej Dudek | 2021-09-23 | 1 | -235/+41 | |
| | | | | | | | | Signed-off-by: Maciej Dudek <mdudek@antmicro.com> | |||||
| * | Change Cluster placement algorithm | Maciej Dudek | 2021-09-23 | 3 | -123/+133 | |
| | | | | | | | | | | | | | | Use physical placement from device DB It should reduce runtime Signed-off-by: Maciej Dudek <mdudek@antmicro.com> | |||||
| * | Adding MacroCell placement | Maciej Dudek | 2021-09-23 | 4 | -21/+353 | |
| | | | | | | | | Signed-off-by: Maciej Dudek <mdudek@antmicro.com> | |||||
| * | Adding support for MacroCells | Maciej Dudek | 2021-09-23 | 5 | -6/+385 | |
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* | | ci: Bump prjoxide version | gatecat | 2021-09-24 | 1 | -1/+1 | |
| | | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | |||||
* | | Merge pull request #826 from YosysHQ/gatecat/nexus-lutperm | gatecat | 2021-09-24 | 6 | -6/+100 | |
|\ \ | |/ |/| | nexus: Add LUT permutation support | |||||
| * | nexus: Add resource cost overrides | gatecat | 2021-09-24 | 2 | -2/+21 | |
| | | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | |||||
| * | router2: Allow overriding resource costs | gatecat | 2021-09-24 | 2 | -2/+9 | |
| | | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | |||||
| * | nexus: LUT permutation support | gatecat | 2021-09-24 | 4 | -4/+72 | |
|/ | | | | Signed-off-by: gatecat <gatecat@ds0.me> | |||||
* | Merge pull request #825 from antmicro/chain_swap_fix | gatecat | 2021-09-23 | 1 | -2/+15 | |
|\ | | | | | Fix chain swap | |||||
| * | Fix chain swap | Maciej Dudek | 2021-09-23 | 1 | -2/+15 | |
| | | | | | | | | | | | | | | | | | | | | | | | | Issue was due to dest_bels being not cleared between clusters unbindes, causing newly bind bels to be unbinded and having their old bel value changed to new bel value. Then when swap failed 2 cells were being bind to a single bel. I tested leaving dest_bels in the function scope and moving it to the loop scope. Code with dest_bels in the loop scope was faster than leaving it in the function scope, and checking if the cell is in the processed cluster. Signed-off-by: Maciej Dudek <mdudek@antmicro.com> | |||||
* | | Merge pull request #822 from YosysHQ/gatecat/nexus-split-vcc | gatecat | 2021-09-23 | 3 | -0/+7 | |
|\ \ | | | | | | | nexus: Support for split Vcc routing | |||||
| * | | nexus: Support for split Vcc routing | gatecat | 2021-09-22 | 3 | -0/+7 | |
| | | | | | | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | |||||
* | | | Merge pull request #824 from YosysHQ/gatecat/py-sigint | gatecat | 2021-09-23 | 1 | -1/+7 | |
|\ \ \ | |_|/ |/| | | python: Restore SIGINT handler while running a Python script | |||||
| * | | python: Restore SIGINT handler while running a Python script | gatecat | 2021-09-22 | 1 | -1/+7 | |
| | | | | | | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | |||||
* | | | Merge pull request #823 from YosysHQ/gatecat/nexus-r1-tweaks | gatecat | 2021-09-22 | 2 | -2/+4 | |
|\ \ \ | |/ / |/| | | nexus: Tweaks for router1 performance | |||||
| * | | nexus: Tweaks for router1 performance | gatecat | 2021-09-22 | 2 | -2/+4 | |
| |/ | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me> |